KR20080105288A - Liquid crystal display and driving method thereof - Google Patents

Abstract

A liquid crystal display and a driving method thereof are provided to improve display quality by preventing a DC image sticking. A plurality of data lines to which the data voltage is supplied and a plurality of gate lines to which the scan pulse is supplied are formed on a liquid crystal display panel. The liquid crystal display panel includes a plurality of liquid crystal cells. A logic circuit generates a first polarity control signal and a second polarity control signal, a third polarity control signal including an inverse phase with the first polarity control signal, and a fourth polarity control signal including the inverse phase with the second polarity control signal. The logic circuit generates a horizontal output inverse signal to invert the logic in one frame period unit. A data driving circuit shifts the polarity of data voltage supplied to data lines in 1 frame period unit according to the column direction of the liquid crystal cells in response to polarity control signals. The data driving circuit shifts the polarity of data voltage in 1 frame period unit according to a row direction of the liquid crystal cells in response to the horizontal output inverse signal. A gate driving circuit supplies the scan pulse to gate lines.

Description

Liquid Crystal Display and Driving Method

1 is an equivalent circuit diagram showing a liquid crystal cell of a liquid crystal display device.

2 is a waveform diagram showing an example of interlaced data;

3 is an experimental result screen showing a DC afterimage due to interlaced data.

4 is an experimental result screen showing a DC afterimage due to scroll data.

5 is a view for explaining a method of driving a liquid crystal display device according to an embodiment of the present invention;

FIG. 6 is a waveform diagram showing an effect of preventing direct current afterimage of the liquid crystal display shown in FIG. 5; FIG.

7 is a view illustrating a polar pattern of data voltage supplied to a liquid crystal display according to an exemplary embodiment of the present invention.

8 is a waveform diagram showing an experimental result of data voltages as shown in FIG. 7.

FIG. 9 is an optical waveform diagram showing an experimental result of a liquid crystal display panel to which data voltages as shown in FIG. 7 are supplied.

10 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention.

FIG. 11 is a block diagram illustrating the logic circuit shown in FIG. 10 in detail.

12 is a block diagram showing in detail the POL generation circuit shown in FIG.

FIG. 13 is a block diagram showing in detail the data driving circuit shown in FIG. 10; FIG.

14 is a circuit diagram showing in detail the digital-to-analog converter shown in FIG.

FIG. 13 is a waveform diagram showing a polarity control signal and a horizontal output switching signal for controlling the digital-to-analog converter shown in FIG.

15 is a view showing another polar pattern of the data voltage supplied to the liquid crystal display according to the exemplary embodiment of the present invention.

16 is a waveform diagram illustrating a reference polarity control signal, first to fourth polarity control signals, and a horizontal output inversion signal.

17 is a flowchart for explaining a method of driving a liquid crystal display according to a second embodiment of the present invention.

18 is a block diagram illustrating a liquid crystal display according to a second exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100: liquid crystal display panel 101: timing controller

102, 182: logic circuit 103, 183: data drive circuit

104: gate driving circuit 105: system

181: image analysis circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof to improve display quality by preventing direct current afterimage and flicker.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. The active matrix type liquid crystal display device actively converts data by switching data voltages supplied to the liquid crystal cells by using a thin film transistor (TFT) formed for each liquid crystal cell (Clc) as shown in FIG. 1. By controlling, the display quality of a moving image can be improved. In FIG. 1, reference numeral “Cst” denotes a storage capacitor Cst for maintaining a data voltage charged in the liquid crystal cell Clc, “DL1” denotes a data line to which a data voltage is supplied, and “GL1”. Denotes a gate line to which a scan voltage is supplied.

In order to reduce the DC offset component and reduce the deterioration of the liquid crystal, the liquid crystal display device is driven in an inversion method in which polarities are inverted between neighboring liquid crystal cells and polarities are inverted in units of frame periods. However, if any one of the two polarities of the data voltage is supplied dominant for a long time, an afterimage occurs. This afterimage is referred to as "DC image sticking" because the liquid crystal cell is repeatedly charged with the same polarity. One example of such an example is when interlace data voltages are supplied to a liquid crystal display. Interlaced data (hereinafter referred to as "interlaced data") includes only the odd line data voltages to be displayed on the liquid crystal cells of the odd horizontal lines in the odd frame period, and is displayed on the liquid crystal cells of the even horizontal lines in the even frame period. Only the data voltage to be included is included.

2 is a waveform diagram illustrating an example of interlace data supplied to a liquid crystal cell Clc. It is assumed that the liquid crystal cell Clc supplied with the data voltage as shown in FIG. 2 is any one of the liquid crystal cells arranged in the odd horizontal line.

Referring to FIG. 2, the liquid crystal cell Clc is supplied with a positive voltage during the odd frame period and a negative voltage during the even frame period. In the interlace method, since the high positive data voltage is supplied only to the liquid crystal cell Clc arranged on the odd horizontal line during the odd frame period, the positive data voltage is negatively divided like the waveform in the box during the four frame periods. It is predominant compared to that of the direct current afterimage. Figure 3 is an image showing the experimental results of the DC afterimage resulting from the interlace data. When the original image as shown in the left image of FIG. 3 is supplied to the liquid crystal display panel in an interlaced manner for a predetermined time, the amplitude of the data voltage whose polarity changes in units of frame periods varies in the odd frame and the even frame, resulting in the original image as shown in the left image. After the image is supplied with a data voltage of intermediate gradation, that is, 127 gradations, to all the liquid crystal cells Clc of the liquid crystal display panel, a direct current afterimage in which a pattern of the original image is faint appears as shown in the right image.

As another example of a DC residual image, when the same image is moved or scrolled at a constant speed, the voltage of the same polarity is repeatedly generated in the liquid crystal cell Clc according to the correlation between the size of the scrolled picture and the scroll speed (moving speed). Accumulation may cause a DC afterimage. This example is shown in FIG. 4. Figure 4 is an image showing the experimental results of the DC afterimage appearing when moving the diagonal pattern and the character pattern at a constant speed.

In a liquid crystal display device, not only the display quality of a moving image is deteriorated by the afterimage of DC, but also the display quality is deteriorated by a flicker phenomenon in which the luminance difference is periodically observed by the naked eye. Therefore, in order to improve the display quality of the liquid crystal display device, it is necessary to solve the DC afterimage and to prevent the flicker phenomenon.

Disclosure of Invention An object of the present invention is to provide a liquid crystal display device and a method of driving the same, which are designed to solve the problems of the prior art and to improve display quality by preventing direct current afterimage and flicker.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention comprises a liquid crystal display panel having a plurality of liquid crystal cells formed with a plurality of data lines supplied with a data voltage and a plurality of gate lines supplied with a scan pulse; Generating a first polarity control signal, a second polarity control signal different from the first polarity control signal, and a third polarity control signal that is in phase out of the first polarity control signal and an inverse phase of the second polarity control signal; A logic circuit for generating a polarity control signal and a horizontal output inversion signal in which logic is inverted in units of one frame period; In response to the polarity control signals, the polarity of the data voltages to be supplied to the data lines is shifted along the column direction of the liquid crystal cells in units of one frame period, and the polarity of the data voltages is adjusted in response to the horizontal output inversion signal. A data driving circuit shifting the liquid crystal cells along the row direction in units of one frame period; And a gate driving circuit supplying the scan pulses to the gate lines.

The logic of the polarity control signal is inverted in units of two horizontal periods.

The liquid crystal cells arranged in rows 4j (j are integers greater than 0) +1 and 4j + 2 in columns 4i (i are integers greater than 0) +1 and 4i + 2 during the Nth frame period have positive polarity. A data voltage is supplied, and a negative data voltage is supplied to the liquid crystal cells arranged in rows 4j + 1 and 4j + 2 in columns 4i + 3 and 4i + 4. The negative data voltages are supplied to the liquid crystal cells arranged in rows 4j + 3 and 4j + 4 in columns 4i + 2 and the fourth j + 3 in columns 4i + 3 and 4i + 4. And a data voltage of positive polarity is supplied to the liquid crystal cells arranged in the fourth j + 4th row.

During the N + 1th frame period, the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 4 rows in the fourth i + 2 and fourth i + 3 columns, and the fifth The negative data voltages are supplied to the liquid crystal cells arranged in rows 4j + 1 and 4j + 4 in columns 4i + 1 and 4i + 4, and columns 4i + 2 and 4i + 3 are provided. The negative data voltage is supplied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 rows, and the fourth j + 2 and the fourth j in the fourth i + 1 and fourth i + 4 columns. The positive data voltages are supplied to the liquid crystal cells arranged in a +3 row.

During the N + 2th frame period, the positive data voltages are supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 2 rows in the fourth i + 3 and fourth i + 4 columns. The negative data voltages are supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 rows in the 4i + 1 and 4i + 2 columns, and the 4i + 3 and 4i + 4 columns are supplied. The negative data voltages are supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows, and the fourth j + 3 and the fourth j + in the fourth i + 1 and fourth i + 2 columns. The positive data voltages are supplied to the liquid crystal cells arranged in four rows.

During the N + 3th frame period, the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 4 rows in the fourth i + 1 and fourth i + 4 columns, and the fifth The negative data voltages are supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 4 rows in the 4i + 2 and 4i + 3 columns, and the 4i + 1 and 4i + 4 columns are provided. The negative data voltages are supplied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 rows, and the fourth j + 2 and fourth j in the fourth i + 2 and fourth i + 3 columns. The positive data voltage is supplied to the liquid crystal cells arranged in a +3 row.

The liquid crystal cells may include a first liquid crystal cell group in which voltages of the same polarity are continuously supplied for two frame periods; And a second liquid crystal cell group in which the voltage of the first polarity and the voltage of the second polarity are continuously supplied during the two frame periods.

In each of the frame periods, the liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged along a row direction and a column direction; The position of the first liquid crystal cell group and the position of the second liquid crystal cell group are changed in units of one frame period.

During the Nth frame period, positive electrodes are included in the liquid crystal cells arranged in rows 4j (j is an integer of 0 or more) +1 and 4j + 2 in columns 4i (i is an integer of 0 or more) +1 and 4i + 4. A negative data voltage is supplied, a negative data voltage is supplied to the liquid crystal cells arranged in rows 4j + 1 and 4j + 2 in columns 4i + 2 and 4i + 3, and the 4i + 1 And the negative data voltage is supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows in the fourth i + 4 column, and the fourth j in the fourth i + 2 and fourth i + 3 columns. The positive data voltages are supplied to the liquid crystal cells arranged in the +3 and 4j + 4 rows.

During the N + 1th frame period, the positive data voltages are supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 4 rows in the fourth i + 3 and fourth i + 4 columns. The negative data voltages are supplied to the liquid crystal cells arranged in rows 4j + 1 and 4j + 4 in columns 4i + 1 and 4i + 2, and columns 4i + 3 and 4i + 4 are provided. The negative data voltage is supplied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 rows, and the fourth j + 2 and the fourth j in the fourth i + 1 and fourth i + 2 columns. The positive data voltages are supplied to the liquid crystal cells arranged in a +3 row.

During the N + 2th frame period, the positive data voltages are supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 4 rows in the fourth i + 2 and fourth i + 3 columns, The negative data voltages are supplied to the liquid crystal cells arranged in rows 4j + 1 and 4j + 4 in columns 4i + 1 and 4i + 4, and columns 4i + 2 and 4i + 3 are provided. The negative data voltage is supplied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 rows, and the fourth j + 2 and the fourth j in the fourth i + 1 and fourth i + 4 columns. The positive data voltages are supplied to the liquid crystal cells arranged in a +3 row.

During the N + 3th frame period, the positive data voltages are supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 2 rows in the fourth i + 1 and fourth i + 2 columns, The negative data voltages are supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 rows in the 4i + 3 and 4i + 4 columns, and the 4i + 1 and 4i + 2 columns are provided. The negative data voltage is supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows, and the fourth j + 3 and fourth j in the fourth i + 3 and fourth i + 4 columns. The positive data voltages are supplied to the liquid crystal cells arranged in a +4 row.

The first liquid crystal cell group includes liquid crystal cells arranged in the fourth i + 1 and fourth i + 3 columns during the Nth frame period and the N + 2th frame period, and the second liquid crystal cell group includes the fourth i + 2 and Liquid crystal cells arranged in a fourth i + 4 column.

The liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged in each of the row direction and the column direction during the N + 1th frame period and the N + 3th frame period.

According to another exemplary embodiment of the present invention, a liquid crystal display includes: a liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with scan pulses, and having a plurality of liquid crystal cells; An image analysis circuit for analyzing digital video data of the input image; The first polarity control signal and the second polarity control signal different from the first polarity control signal are generated when data that may cause a DC residual image is input according to the output of the image analysis circuit. A logic circuit for generating a third polarity control signal that is in phase and a fourth polarity control signal that is in phase of the second polarity control signal and a horizontal output inversion signal in which logic is inverted in units of one frame period; In response to the polarity control signals, the polarity of the data voltages to be supplied to the data lines is shifted along the column direction of the liquid crystal cells in units of one frame period, and the polarity of the data voltages is adjusted in response to the horizontal output inversion signal. A data driving circuit shifting along the row direction of the liquid crystal cells in units of one frame period; And a gate driving circuit supplying the scan pulses to the gate lines.

According to an exemplary embodiment of the present invention, a driving method of a liquid crystal display device generates a first polarity control signal, a second polarity control signal different from the first polarity control signal, and has a third polarity which is an inverse phase of the first polarity control signal. Generating a fourth polarity control signal that is in phase of a control signal and the second polarity control signal and generating a horizontal output inversion signal in which logic is inverted in units of one frame period; In response to the polarity control signals, the polarity of the data voltages to be supplied to the data lines is shifted along the column direction of the liquid crystal cells in units of one frame period, and the polarity of the data voltages is adjusted in response to the horizontal output inversion signal. Shifting along the row direction of the liquid crystal cells in units of one frame period; And supplying the scan pulse to the gate lines.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display, comprising: analyzing digital video data of an input image; As a result of the image analysis, when data in which a direct current residual image may appear is generated, a first polarity control signal and a second polarity control signal different from the first polarity control signal are generated, and the reverse phase of the first polarity control signal is generated. Generating a fourth polarity control signal that is in phase of the third polarity control signal and the second polarity control signal and a horizontal output inversion signal in which logic is inverted in units of one frame period; In response to the polarity control signals, the polarity of the data voltages to be supplied to the data lines is shifted along the column direction of the liquid crystal cells in units of one frame period, and the polarity of the data voltages is adjusted in response to the horizontal output inversion signal. Shifting along the row direction of the liquid crystal cells in units of one frame period; Supplying the scan pulse to the gate lines.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 18.

Referring to FIG. 5, the driving method of the liquid crystal display according to the exemplary embodiment of the present invention inverts the polarity of the data voltage charged in the liquid crystal cell in units of two frame periods, and also includes a pixel row in which the liquid crystal cells are arranged in the horizontal direction. The polarity inversion periods of the data voltages supplied to the neighboring liquid crystal cells are controlled to be offset from each other. In addition, the driving method of the liquid crystal display according to the exemplary embodiment of the present invention inverts the polarity of the pixel column in which the liquid crystal cells are arranged vertically in units of two horizontal lines (or low lines), and reverses the polarity of the pixel column every one frame period. Shift by line As a result, the liquid crystal cell of the first liquid crystal cell group to which data voltages of the same polarity are supplied for two frame periods in each of the pixel row and the pixel column, and the liquid crystal of the second liquid crystal cell group to which data voltages of different polarity are supplied to the two pixel periods. The cell is neighboring. The positions of the liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the second liquid crystal cell group are changed in units of one frame period.

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention provides a data voltage having the same polarity to a liquid crystal cell for two frame periods to prevent direct current afterimage, and surrounds a liquid crystal cell in which the polarity of the data voltage is maintained for two frame periods. The polarization of the data voltages of other liquid crystal cells present in the circuit is reversed once to prevent flicker. Referring to FIG. 6, the effects of no direct-current afterimage appearing when the data voltage supplied to the liquid crystal cell is inverted every two frame periods will be described.

Referring to FIG. 6, it is assumed that a high data voltage is supplied to a liquid crystal cell during an odd frame period and a relatively low data voltage is supplied during an even frame period, and the data voltages change polarity every two frame periods. Then, like the waveforms in the box, the positive data voltages supplied to the liquid crystal cell during the Nth frame period and the N + 1th frame period and the negative polarity supplied to the same liquid crystal cell during the N + 2 and N + 3th frame periods. The data voltages are neutralized so that voltages of polarized polarities are not accumulated in the liquid crystal cell. Accordingly, the liquid crystal display of the present invention does not appear to have a DC afterimage when interlace data is generated in which a high voltage of a specific polarity is generated during one of the odd frame and the even frame.

However, when all of the liquid crystal cells are inverted at the same time in two frame periods as shown in FIG. 6, flicker may appear in two frame periods. If the flicker shortens the period of change in brightness, the observer does not feel the flicker. Therefore, in the method of driving the liquid crystal display according to the exemplary embodiment of the present invention, the polarity of the data voltage supplied to other liquid crystal cells existing around the liquid crystal cell charged with the data voltage of the same polarity for two frame periods is determined by one frame period. Inverting the signal to increase the spatial frequency of the display screen so that the viewer hardly feels flicker.

FIG. 7 is a diagram illustrating polarities of data voltages supplied to 8x7 liquid crystal cells during Nth through Nth + 3th frame periods.

Referring to FIG. 7, 4j (j is an integer of 0 or more) +1 in 4i (i is an integer of 0 or more) +1 and 4i + 2 in columns C1, C2, C5, and C6 during the Nth frame period. The liquid crystal cells disposed in the fourth j + 2 rows R1, R2, R5, and R6 are supplied with positive data voltages, and the fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, fourth, third, third, fourth, fourth, fourth, third, third, fourth, fourth, third, fourth, fourth, fourth, third, fourth, fourth, third, third, third, fourth, fourthmost stages of the: In C8), the liquid crystal cells arranged in the fourth j + 1 and fourth j + 2 rows R1, R2, R5, and R6 are supplied with a negative data voltage. During the Nth frame period, the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows R3, R4, and R7 in the fourth i + 1 and fourth i + 2 columns C1, C2, C5, and C6 are included in the liquid crystal cells. A negative data voltage is supplied to the fourth j + 3 and fourth j + 4 rows R3, R4, and R7 in the fourth and fourth i + 3 and fourth i + 4 columns C3, C4, C7, and C8. The arranged liquid crystal cells are supplied with a positive data voltage.

Liquid crystal cells arranged in rows 4j + 1 and 4j + 4 (R1, R4, and R5) in columns 4i + 2 and 4i + 3 (C2, C3, C6, and C7) during the N + 1th frame period. Field is supplied with a positive data voltage, and the fourth j + 1 and fourth j + 4 rows R1, R4, and R5 in the fourth i + 1 and fourth i + 4 columns C1, C4, C5, and C8. Negative data voltages are supplied to the liquid crystal cells disposed in the N-axis. During the N + 1th frame period, rows 4j + 2 and 4j + 3 are arranged in rows 4j + 2 and 4j + 3 in columns 4i + 2 and 4i + 3 (C2, C3, C6, and C7). The liquid crystal cells are supplied with a negative data voltage, and the fourth j + 2 and fourth j + 3 rows R2 and R3 are arranged in columns 4i + 1 and 4i + 4 (C1, C4, C5, and C8). The data voltages of the positive polarity are supplied to the liquid crystal cells disposed at R6 and R7.

During the N + 2th frame period, rows 4j + 1 and 4j + 2 are arranged in rows 4j + 1 and 4j + 2 in columns 4i + 3 and 4i + 4 (C3, C4, C7, and C8). The liquid crystal cells are supplied with a positive data voltage, and the fourth j + 1 and fourth j + 2 rows R1 and R2 are arranged in columns 4i + 1 and 4i + 2 (C1, C2, C5, and C6). , The data voltage of negative polarity is supplied to the liquid crystal cells arranged in R6). Liquid crystal cells arranged in rows 4j + 3 and 4j + 4 (R3, R4, and R7) in the 4i + 3 and 4i + 4 columns C3, C4, C7, and C8 during the N + 2th frame period. Field is supplied with a negative data voltage, and the fourth j + 3 and fourth j + 4 rows R3, R4, and R7 in the fourth i + 1 and fourth i + 2 columns C1, C2, C5, and C6. The liquid crystal cells disposed in the C1 are supplied with a positive data voltage.

Liquid crystal cells arranged in rows 4j + 1 and 4j + 4 (R1, R4, and R5) in columns 4i + 1 and 4i + 4 (C1, C4, C5, and C8) during the N + 3th frame period. Field is supplied with a positive data voltage, and the 4j + 1 and 4j + 4 rows (R1, R4, R5) in the 4i + 2 and 4i + 3 columns C2, C3, C6, and C7. Negative data voltages are supplied to the liquid crystal cells disposed in the N-axis. During the N + 3th frame period, rows 4j + 2 and 4j + 3 are arranged in rows 4j + 2 and 4j + 3 in columns 4i + 1 and 4i + 4 (C1, C4, C5, and C8). The liquid crystal cells are supplied with a negative data voltage, and the fourth j + 2 and fourth j + 3 rows R2 and R3 are arranged in columns 4i + 2 and 4i + 3 (C2, C3, C6, and C7). The data voltages of the positive polarity are supplied to the liquid crystal cells disposed at R6 and R7.

In each of the frame periods, the liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged in the row direction and the column direction, respectively, and the positions thereof are changed in units of one frame period.

In the N + 4th frame period, the data voltages are supplied to the liquid crystal cells in the same polar pattern as the Nth frame period, and in the N + 5th frame period, the data voltages are applied in the same polar pattern as the N + 1 frame period. Supplied to the field. In the N + 6th frame period, the data voltages are supplied to the liquid crystal cells in the same polar pattern as the N + 2th frame period, and in the N + 7th frame period, the data voltages are applied in the same polar pattern as the N + 3th frame period. It is supplied to liquid crystal cells.

As can be seen in FIG. 7, in the liquid crystal display according to the exemplary embodiment of the present invention, data voltages whose polarities are inverted in units of two liquid crystal cells adjacent to each other in the row direction and the column direction are supplied to the liquid crystal cells. The liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged in the row direction and the column direction, respectively.

FIG. 8 illustrates an experimental result of supplying a data voltage of 127 gray levels to a liquid crystal display panel in the same polar pattern as in FIG. 7 and measuring a voltage waveform of the liquid crystal display panel. In this experiment, the data frequency is 30 Hz. The liquid crystal cell of the first liquid crystal cell group and the liquid crystal cell of the second liquid crystal cell group are alternately arranged in each of the row direction and the column direction. Accordingly, the spatial frequency at which the polarity of the data voltage changes on the screen of the liquid crystal display panel due to the second liquid crystal cell group is 60 Hz, and this result is confirmed on the test result screen of FIG. 8. In addition, as a result of measuring the optical waveform by installing an optical sensor on the liquid crystal display panel in this experiment, the optical waveform was also measured at 60 Hz due to the spatial frequency including the liquid crystal cells adjacent to the left and right as shown in FIG.

10 to 14 show a liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 10, a liquid crystal display device according to an exemplary embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a logic circuit 102, a data driving circuit 103, and a gate driving circuit 104. ).

In the liquid crystal display panel 100, liquid crystal molecules are injected between two glass substrates. The m data lines D1 to Dm and the n gate lines G1 to Gn cross the lower glass substrate of the liquid crystal display panel 100. The liquid crystal display panel 100 includes m × n liquid crystal cells Clc arranged in a matrix form by the cross structure of the data lines D1 to Dm and the n gate lines G1 to Gn. As described above, the liquid crystal cells Clc include a first liquid crystal cell group and a second liquid crystal cell group driven at different data voltage frequencies within two frame periods. The lower glass substrate of the liquid crystal display panel 100 includes data lines D1 to Dm, gate lines G1 to Gn, TFTs, pixel electrodes 1 of a liquid crystal cell Clc connected to a TFT, and The storage capacitor Cst and the like are formed.

The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 100. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate. Polarizing plates having optical axes orthogonal to each other are attached to the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on an inner surface of the liquid crystal display panel 100 in contact with the liquid crystal.

The timing controller 101 receives a timing signal such as a vertical / horizontal synchronization signal (Vsync, Hsync), a data enable (Data Enable), a clock signal (CLK), and the like, and the data driving circuit 103 and the gate driving circuit 104. And control signals for controlling the operation timing of the logic circuit 102. These control signals include a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and a source start pulse (SSP). , A source sampling clock (SSC), a source output enable signal (SOE), and a reference polarity control signal (Polarity: POL). The gate start pulse GSP indicates a starting horizontal line at which scanning starts in one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to a shift register in the gate driving circuit 104 and is a timing control signal for sequentially shifting the gate start pulse GSP. The gate shift clock signal GSC is generated at a pulse width corresponding to the ON period of the TFT. do. The gate output enable signal GOE indicates the output of the gate driving circuit 104. The source start pulse SSP indicates a start pixel on one horizontal line in which data is to be displayed. The source sampling clock SSC instructs the latching operation of data in the data driving circuit 103 based on a rising or falling edge. The source output enable signal SOE indicates the output of the data driving circuit 103. The reference polarity control signal POL indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 100. The reference polarity control signal POL is generated as either a polarity control signal of one dot inversion in which logic is inverted in one horizontal period or a polarity control signal of two dot inversion in which logic is inverted in two horizontal periods. In addition, the timing controller 101 separates the input digital video data RGB into the odd pixel data RGBodd and the even pixel data RGBeven in order to lower the transmission frequency of the digital video data, and the data RGBodd and RGBeven. ) Is supplied to the data driving circuit 103 through the six data buses.

The logic circuit 102 receives the gate start pulse GSP, the source output enable signal SOE, and the reference polarity control signal POL, and includes first and fourth polarity control signals as shown in FIG. 7 and FIG. 15 to be described later. Fields POL2a to POL2d are sequentially output or the reference polarity control signal POL is output. As shown in FIGS. 7 and 15, the first to fourth polarity control signals POL2a to POL2d shift the polarity of the data voltage by one liquid crystal cell along the column direction (or vertical line direction) every frame. In addition, the logic circuit 102 generates a horizontal output inversion signal HINV for inverting the polarity of the data voltage output from some of the output channels of the output channel of the data driving circuit so that the row direction (or horizontal) is performed every frame. Along the line direction) by one liquid crystal cell. The logic circuit 102 may be embedded in the timing controller 101.

The data driving circuit 103 latches the digital video data RGBodd and RGBeven under the control of the timing controller 101 and polarizes the digital video data RGBodd and RGBeven from the logic circuit 102 POL / POL2a. In response to ˜POL2d), an analog positive / negative gamma compensation voltage is converted to generate a positive / negative analog data voltage, and the data voltage is supplied to the data lines D1 to Dm. The data driving circuit 103 inverts the polarity of the data voltage in units of one horizontal period or two horizontal periods in response to the polarity control signals POL / POL2a to POL2d from the logic circuit 102. In addition, the data driving circuit 103 inverts the polarities of the data voltages output through the adjacent output channels in response to the horizontal output inversion signal HINV from the logic circuit 102.

The gate driving circuit 104 has a shift register and a level shifter for converting the output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to Gn, respectively. Comprising a plurality of gate drive integrated circuits comprising a sequentially output scan pulses having a pulse width of approximately one horizontal period.

The liquid crystal display according to the exemplary embodiment of the present invention further includes a system 105 for supplying the digital video data RGB and the timing signals Vsync, Hsync, DE, and CLK to the timing controller 101.

The system 105 extracts video data from a broadcast signal or an image source input from an external device, including a broadcast signal, an external device interface circuit, a graphic processing circuit, a line memory 106, and converts the video data into digital. Supply to timing controller 101. The interlace broadcast signal received by the system 106 is stored in the line memory 106 and then output. The video data of the interlace broadcast signal exists only in the odd line in the odd frame period and only in the even line in the even frame period. Accordingly, when the system 105 receives the interlace broadcast signal, the system 105 generates even line data of the odd frame period and odd line line data of the even frame as an average value or black data value of valid data stored in the line memory 106. The system 105 supplies timing signals 101 and timing signals Vsync, Hsync, DE, and CLK together with the digital video data.

11 and 12 are circuit diagrams showing the logic circuit 102 in detail.

11 and 12, the logic circuit 102 includes a frame counter 111, a line counter 112, a POL generating circuit 113, and a multiplexer 114.

The frame counter 111 indicates a frame count indicating the number of frames of an image to be displayed on the liquid crystal display panel 100 in response to the gate start pulse GSP, which is generated once during one frame period and coincided with the start of one frame period. Outputs information Fcnt. The frame count information Fcnt is generated as 2-bit information so that each of the four frame periods can be identified assuming that the polarity pattern of the data voltage is repeated in four frame period periods as shown in FIGS. 7 and 15.

The line counter 112 is a row in which the data is to be displayed on the liquid crystal display panel 100 in response to the source output enable signal SOE indicative of the output point of the data voltage from the data driving circuit 103 every horizontal period. Outputs line count information Lcnt indicating a horizontal line). Line count information Fcnt is generated with 2-bit information.

The POL generating circuit 113 generates the 1-bit horizontal output inversion signal HINV using the frame count information Fcnt, and the first POL generating circuit 121 and the second POL generating circuit 122 as shown in FIG. 12. The first to fourth polarity control signals POL2a to POL2d are sequentially generated using the first and second inverters 123 and 124 and the multiplexer 125. As shown in FIG. 16, the horizontal output inversion signal HINV inverts logic in units of one frame period so that the polarity patterns in the horizontal 2 dot and vertical 2 dot directions are shifted in the row direction as shown in FIGS. 7 and 15. ) To control the output. In order to generate the polarity pattern as shown in FIG. 7, the horizontal output inversion signal HINV is generated in low logic in the Nth and N + 2th frame periods as in the solid line waveform of FIG. It occurs in high logic in three frame periods. In order to generate the polar pattern shown in FIG. 15, the horizontal output inversion signal HINV is generated in high logic in the Nth and N + 2th frame periods as in the dotted waveform of FIG. It occurs in low logic in three frame periods. The horizontal two dot inversion method is an inversion method of supplying data voltages whose polarities are inverted in units of two horizontally neighboring liquid crystal cells as shown in FIGS. 7 and 15. The vertical two-dot inversion method is an inversion method of supplying data voltages whose polarities are inverted in units of two vertically neighboring liquid crystal cells as shown in FIGS. 7 and 15.

The first POL generation circuit 121 generates the first polarity control signal POL2a in which logic is inverted according to the line counter information Lcnt and the frame counter information Fcnt. The first polarity control signal POL2a is generated with high logic indicating positive polarity (+) of the data voltage in the first row R1 and the second row R2 as shown in FIGS. 7 and 15, and the first row. The logic is reversed in units of two rows from the nth to the nth row. The first inverter 123 inverts the first polarity control signal POL2a to generate the third polarity control signal POL2c in the reverse phase of the first polarity control signal POL2a. Therefore, the third polarity control signal POL2c is generated in a low logic indicating negative polarity (−) of the data voltage in the first row R1 and the second row R2, and the first to nth rows. The logic is reversed in units of two rows.

The second POL generation circuit 122 generates a second polarity control signal POL2b whose logic is inverted according to the line counter information Lcnt and the frame counter information Fcnt. As shown in FIGS. 7 and 15, the second polarity control signal POL2b is generated in a low logic indicating negative polarity (−) of the data voltage in the first row R1, and the second row to the second to nth rows. The logic is reversed in units. The second inverter 124 inverts the second polarity control signal POL2b to generate the fourth polarity control signal POL2d in the reverse phase of the second polarity control signal POL2b. Therefore, the fourth polarity control signal POL2d is generated in high logic indicating positive polarity (+) of the data voltage in the first row R1, and the logic is inverted in units of two rows from the second row to the nth row. do.

The multiplexer 125 outputs the first polarity control signal POL2a during the N-th frame period in response to the 2-bit frame count information Fcnt, and then outputs the second polarity control signal POL2b during the N + 1th frame period. Next, the third polarity control signal POL2c is output during the N + 2th frame period. The multiplexer 125 outputs the fourth polarity control signal POL2d during the N + 3th frame period.

One of the first to fourth polarity control signals POL2a to POLd output from the POL generation circuit 113 and the reference polarity control signal POL generated by the internal circuit of the timing controller 101 are illustrated in FIG. As selected by the multiplexer 114. The multiplexer 114 selects the polarity control signals POL2a to POL2d and POL to be supplied to the data driving circuit 103 according to the logic value of the control terminal connected to the POL selection option pin. The POL selection option pin may be connected to the control terminal of the multiplexer 114 and may be selectively connected to the ground voltage GND or the power supply voltage Vcc by the manufacturer or the user. For example, when the POL selection option pin is connected to the base voltage GND and the control terminal of the multiplexer 114, the multiplexer 114 is supplied with a selection control signal SEL of "0" to its control terminal to control the reference polarity. Outputs the signal POL, and when the POL selection option pin is connected to the control voltage of the power supply voltage Vcc and the multiplexer 114, the multiplexer 114 has a selection control signal SEL of '1' at its control terminal. Supplied to output the first to fourth polarity control signals POL2a to POL2d from the POL generation circuit 113. The selection control signal SEL of the multiplexer 114 may be replaced by a user selection signal input through a user interface, or a selection control signal automatically generated according to a data analysis result as in the second embodiment described later.

13 and 14 are circuit diagrams showing the data driving circuit 103 in detail.

Referring to FIGS. 13 and 14, the data driving circuit 103 includes a plurality of integrated circuits (ICs) for driving k data lines D1 to Dk (k is an integer smaller than m), respectively. Each of the integrated circuits includes a shift register 131, a data register 132, a first latch 133, a second latch 134, a digital-to-analog converter (hereinafter referred to as a “DAC”) 135, and a charge. A charge share circuit 136 and an output circuit 137 are included.

The shift register 131 shifts the source start pulse SSP from the timing controller 101 according to the source sampling clock SSC to generate a sampling signal. In addition, the shift register 131 shifts the source start pulse SSP to transfer the carry signal CAR to the shift register 131 of the next stage integrated circuit. The data register 132 temporarily stores odd digital video data RGBodd and even digital video data RGBeven separated by the timing controller 101, and stores the stored data RGBodd and RGBeven in the first latch 133. To feed. The first latch 133 samples the digital video data RGBeven and RGBodd from the data register 132 in response to a sampling signal sequentially input from the shift register 131, and stores the data RGBeven and RGBodd. ) Is latched by one horizontal line, and then data for one horizontal line is output at the same time. The second latch 134 latches one horizontal line of data input from the first latch 133 and then second latches 134 of other integrated circuits during the low logic period of the source output enable signal SOE. And latched digital video data at the same time.

The DAC 135 includes a P-decoder (PDEC) 141 supplied with the positive gamma reference voltage GH and an N-decoder (NDEC) 142 supplied with the negative gamma reference voltage GL, as shown in FIG. 14. First to fourth multiplexers 143a to 143d for selecting the output of the P-decoder 141 and the output of the N-decoder 142 in response to the polarity control signals POL / POL2a to POL2d. The horizontal polarity control circuits 150a and 150b inverting the logic of the polarity control signals POL / POL2a to POL2d supplied to the control terminals of the second and fourth multiplexers 143b and 143d in response to the signal HINV. Include. The P-decoder 141 decodes the digital video data input from the second latch 134 and outputs a positive gamma compensation voltage corresponding to the gray value of the data. The N-decoder 142 decodes the digital video data input from the second latch 134 and outputs a negative gamma compensation voltage corresponding to the gray value of the data.

The multiplexers 143 are controlled by the outputs of the first and third multiplexers 143a and 143c directly controlled by the polarity control signals POL / POL2a to POL2d and the horizontal polarity control circuits 150a and 150b. And second and fourth multiplexers 143b and 143d. The first multiplexer 143a alternately selects the positive gamma compensation voltage and the negative gamma compensation voltage in two horizontal periods in response to the polarity control signals POL / POL2a to POL2d supplied to its non-inverting control terminal. Then, the selected positive / negative gamma compensation voltage is output as an analog data voltage. The second multiplexer 143b alternately selects a positive gamma compensation voltage and a negative gamma compensation voltage in units of two horizontal periods in response to the output of the horizontal polarity control circuit 150a supplied to its non-inverting control terminal. Outputs the selected positive / negative gamma compensation voltage as an analog data voltage. The third multiplexer 143c alternately selects a positive gamma compensation voltage and a negative gamma compensation voltage in units of two horizontal periods in response to the polarity control signals POL / POL2a to POL2d supplied to its inversion control terminal. Outputs the selected positive / negative gamma compensation voltage as an analog data voltage. The fourth multiplexer 143d alternately selects a positive gamma compensation voltage and a negative gamma compensation voltage in two horizontal periods in response to the output of the horizontal polarity control circuit 150b supplied to its inversion control terminal. Outputs positive / negative gamma compensation voltage as analog data voltage.

The horizontal polarity control circuits 150a and 150b include switch elements S1 and S2 and an inverter 144. The horizontal polarity control circuits 150a and 150b are used to control the selection control signal supplied to the non-inverting control terminal of the second multiplexer 143b and the inverting control terminal of the fourth multiplexer 143d in response to the horizontal polarity inversion signal HINV. Control the logic value. The input terminal of the first switch element S1 is connected to the polarity control signal supply line 151 and the output terminal of the first switch element S1 is an inverting / non-inverting control terminal of the second or fourth multiplexers 143b and 143d. Is connected to. The non-inverting control terminal of the first switch element S1 is connected to the horizontal output inverted signal supply line 152. The input terminal of the second switch element S2 is connected to the polarity control signal supply line 151 and the output terminal of the second switch element S2 is connected to the inverter 144. The inversion control terminal of the second switch element S2 is connected to the horizontal output inversion signal supply line 152. The inverter 144 is connected to the output terminal of the second switch element S2 and the inverting / non-inverting control terminal of the second or fourth multiplexers 143b and 143d.

7, 15, and 16, when the horizontal output inversion signal HINV is high, the second switch element S2 is turned on and the first switch element S1 is turned off. Then, the inverted polarity control signals POL / POL2a to POL2d are supplied to the non-inverting control terminal of the second multiplexer 143b, and the inverted polarity control signals POL / to the inverting control terminal of the fourth multiplexer 143d. POL2a to POL2d) are supplied. As a result, when the polarity control signals POL / POL2a to POL2d are high logic and the horizontal output inversion signal HINV is high logic, the second multiplexer 143b receives the negative gamma compensation voltage from the N-decoder 142. Outputs the data voltage to be supplied to the fourth i + 2 data lines D2, D6, ..., Dm-2, and the fourth multiplexer 143d removes the positive gamma compensation voltage from the P-decoder 141. Outputs the data voltage to be supplied to the 4i + 4 data lines D4, D8, ..., Dm. When the polarity control signals POL / POL2a to POL2d are low logic and the horizontal output inversion signal HINV is high logic, the second multiplexer 143b receives the positive gamma compensation voltage from the P-decoder 141 as the fourth i +. Outputs the data voltage to be supplied to the two data lines D2, D6, ..., Dm-2, and the fourth multiplexer 143d outputs the negative gamma compensation voltage from the N-decoder 142 to the fourth i + 4. Outputs the data voltage to be supplied to the data lines D4, D8, ..., Dm.

When the horizontal output inversion signal HINV is low, the first switch element S1 is turned on and the second switch element S2 is turned off. Then, the non-inverted polarity control signals POL / POL2a to POL2d are supplied to the non-inverted control terminal of the second multiplexer 143b, and the non-inverted polarity control signals (the inverted control terminal of the fourth multiplexer 143d) POL / POL2a to POL2d) are supplied. As a result, when the polarity control signals POL / POL2a to POL2d are high logic and the horizontal output inversion signal HINV is low logic, the second multiplexer 143b receives the positive gamma compensation voltage from the P-decoder 141. Outputs the data voltage to be supplied to the fourth i + 2 data lines D2, D6, ..., Dm-2, and the fourth multiplexer 143d removes the negative gamma compensation voltage from the N-decoder 142. Outputs the data voltage to be supplied to the 4i + 4 data lines D4, D8, ..., Dm. When the polarity control signals POL / POL2a to POL2d are low logic and the horizontal output inversion signal HINV is low logic, the second multiplexer 143b receives the negative gamma compensation voltage from the N-decoder 142 as 4i +. Outputs the data voltage to be supplied to the two data lines D2, D6, ..., Dm-2, and the fourth multiplexer 143d outputs the negative gamma compensation voltage from the P-decoder 141 to the fourth i + 4. Outputs the data voltage to be supplied to the data lines D4, D8, ..., Dm. Accordingly, the present invention uses the horizontal output inversion signal (HINV) and the polarity control signals (POL / POL2a to POL2d) to the liquid crystal cells in the polar pattern of the horizontal two dots and vertical two dots inversion as shown in FIGS. 7 and 15. The data voltage to be supplied can be controlled.

15 illustrates a polar pattern of a data voltage according to another embodiment of the present invention. FIG. 15 illustrates polarities of data voltages supplied to 8x7 liquid crystal cells during the Nth through Nth + 3th frame periods.

Referring to FIG. 15, during the Nth frame period, the fourth j + 1 and fourth j + 2 rows R1, R2, R5, and R6 in the fourth i + 1 and fourth i + 4 columns C1, C4, C5, and C8. Are supplied with positive data voltages and are arranged in rows 4j + 1 and 4j + 2 in columns 4i + 2 and 4i + 3 (C2, C3, C6, and C7). The liquid crystal cells arranged at (R1, R2, R5, R6) are supplied with a negative data voltage. During the Nth frame period, the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows R3, R4, and R7 in the fourth i + 1 and fourth i + 4 columns C1, C4, C5, and C8 are included in the liquid crystal cells. A negative data voltage is supplied to the fourth j + 3 and fourth j + 4 rows R3, R4, and R7 in the fourth i + 2 and fourth i + 3 columns C2, C3, C6, and C7. The arranged liquid crystal cells are supplied with a positive data voltage. The first liquid crystal cell group that charges data voltages having the same polarity from the N-1 frame period having the same polarity pattern as the N + 3 frame period during the Nth frame period includes the 4i + 1 and 4i + 3 columns (C1, The second liquid crystal cell group including liquid crystal cells C3, C5, and C7, and which charges data voltages having polarities and opposite polarities in the N-1th frame period during the Nth frame period are referred to as 4i + 2 and 4i +. Liquid crystal cells arranged in four columns C2, C4, C6, and C8.

Liquid crystal cells arranged in rows 4j + 1 and 4j + 4 (R1, R4, and R5) in columns 4i + 3 and 4i + 4 (C3, C4, C7, and C8) during the N + 1th frame period. Field is supplied with a positive data voltage, and the fourth j + 1 and fourth j + 4 rows R1, R4, and R5 in the fourth i + 1 and fourth i + 2 columns C1, C2, C5, and C6. Negative data voltages are supplied to the liquid crystal cells disposed in the N-axis. During the N + 1th frame period, rows 4j + 2 and 4j + 3 are disposed in rows 4j + 2 and 4j + 3 in columns 4i + 3 and 4i + 4 (C3, C4, C7, and C8). The liquid crystal cells are supplied with a negative data voltage, and the fourth j + 2 and fourth j + 3 rows R2 and R3 are arranged in columns 4i + 1 and 4i + 2 (C1, C2, C5, and C6). The data voltages of the positive polarity (+) are supplied to the liquid crystal cells disposed in the R6 and R7. During the N + 1 frame period, the liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged in the row direction and the column direction, respectively.

Liquid crystal cells arranged in rows 4j + 1 and 4j + 4 (R1, R4, and R5) in columns 4i + 2 and 4i + 3 (C2, C3, C6, and C7) during the N + 2th frame period. Field is supplied with a positive data voltage, and the fourth j + 1 and fourth j + 4 rows R1, R4, and R5 in the fourth i + 1 and fourth i + 4 columns C1, C4, C5, and C8. Negative data voltages are supplied to the liquid crystal cells disposed in the N-axis. During the N + 2th frame period, rows 4j + 2 and 4j + 3 are disposed in rows 4j + 2 and 4j + 3 in columns 4i + 2 and 4i + 3 (C2, C3, C6, and C7). The liquid crystal cells are supplied with a negative data voltage, and the fourth j + 2 and fourth j + 3 rows R2 and R3 are arranged in columns 4i + 1 and 4i + 4 (C1, C4, C5, and C8). The data voltages of the positive polarity are supplied to the liquid crystal cells disposed at R6 and R7. The first liquid crystal cell group charging the data voltages having the same polarity from the N + 1 frame period for the N + 2 frame period is the liquid crystal disposed in the columns 4i + 1 and 4i + 3 (C1, C3, C5, C7). The second liquid crystal cell group including the cells and charging the data voltages having polarities opposite to the polarities of the N + 1 frame periods during the N + 2th frame period is arranged in columns 4i + 2 and 4i + 4 (C2, C4, C6). And liquid crystal cells arranged in C8).

During the N + 3th frame period, rows 4j + 1 and 4j + 2 are arranged in rows 4j + 1 and 4j + 2 in the 4i + 1 and 4i + 2 columns C1, C2, C5, and C6. The liquid crystal cells are supplied with a positive data voltage, and the fourth j + 1 and fourth j + 2 rows R1 and R2 are arranged in columns 4i + 3 and 4i + 4 (C3, C4, C7, and C8). The data voltages of the negative polarity (-) are supplied to the liquid crystal cells disposed in the R5 and R6. Liquid crystal cells arranged in rows 4j + 3 and 4j + 4 (R3, R4, and R7) in columns 4i + 1 and 4i + 2 (C1, C2, C5, and C6) during the N + 3th frame period. Are supplied with a negative data voltage, and the fourth j + 3 and fourth j + 4 rows R3, R4, and R7 in the fourth i + 3 and fourth i + 4 columns C3, C4, C7, and C8. The liquid crystal cells disposed in the C1 are supplied with a positive data voltage. During the N + 3 frame period, the liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged in the row direction and the column direction, respectively.

In the N + 4th frame period, data voltages are supplied to the liquid crystal cells in the same polar pattern as the Nth frame period, and in the N + 5th frame period, the data voltages are supplied in the same polar pattern as the N + 1 frame period. Supplied to. In the N + 6th frame period, the data voltages are supplied to the liquid crystal cells in the same polar pattern as the N + 2th frame period, and in the N + 7th frame period, the data voltages are applied in the same polar pattern as the N + 3th frame period. It is supplied to liquid crystal cells.

17 is a flowchart illustrating a method of driving a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 17, a method of driving a liquid crystal display according to another exemplary embodiment of the present invention analyzes input data and determines whether the input data is data in which a DC residual image may appear, such as interlace data or scroll data. (S1, S2)

In operation S2, when it is determined that the data currently input is data that may cause a DC residual image, the present invention sequentially generates the first to fourth polarity control signals POL2a to POL2d in frame period units for two frame periods. The data voltage driving frequency of the first liquid crystal cell group is controlled to be lower than the data voltage driving frequency of the second liquid crystal cell group. In addition, the present invention generates a horizontal output inversion signal (HINV) to control the polarity of the data voltages to be charged in the horizontally adjacent liquid crystal cells in a unit of one frame period.

In operation S2, when the current input data is determined to be the data in which the DC residual image does not appear, the present invention generates a reference polarity control signal POL as shown in FIG. 16 in which the polarity is inverted in every frame period in every frame period. And control the data voltage driving frequency of the second liquid crystal cell group in the same manner (S4).

18 illustrates a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 18, a liquid crystal display according to another exemplary embodiment of the present invention may include a system 105, a liquid crystal display panel 100, an image analysis circuit 181, a timing controller 101, a logic circuit 182, and data. The driving circuit 183 and the gate driving circuit 104 are provided. In this embodiment, the system 105, the liquid crystal display panel 100, the timing controller 101, and the gate driving circuit 104 are substantially the same as the above-described embodiments, and the same reference numerals are used to describe the detailed description thereof. It will be omitted.

The image analysis circuit 181 determines whether direct current afterimage may occur with respect to the digital video data of the currently input image. The image analysis circuit 181 compares data between neighboring lines in one frame image, and determines the currently input data as interlace data when the data between the lines is larger than a predetermined threshold. In addition, the image analysis circuit 181 compares the data of each pixel on a frame-by-frame basis to detect a moving image and a moving speed of the image in the display image, and if the moving image moves at a preset speed, the moving image is included. Determine frame data as scroll data. As a result of the image analysis, the image analysis circuit 181 generates a selection signal SEL2 indicating interlace data or scroll data and controls the logic circuit 182 as shown in FIG. 11 by using the selection signal SEL2. do.

The logic circuit 182 sequentially generates the first to fourth polarity control signals POL2a to POL2d as shown in FIG. 11 in response to the first logic value of the selection signal SEL2 from the image analysis circuit 181. Generates an output inversion signal (HINV). In addition, the logic circuit 182 transfers the reference polarity control signal POL to the data driving circuit 103 as it is when data other than interlace data and scroll data are input in response to the second logic value of the selection signal SEL2. do.

The data driving circuit 183 latches the digital video data RGBodd and RGBeven under the control of the timing controller 101 and polarizes the digital video data RGBodd and RGBeven from the logic circuit 182 (POL / POL2a). In response to ˜POL2d), an analog positive / negative gamma compensation voltage is converted to generate a positive / negative analog data voltage, and the data voltage is supplied to the data lines D1 to Dm. The data driving circuit 183 inverts the polarities of the data voltages in the polarity pattern as shown in FIGS. 7 and 15 in response to the polarity control signals POL / POL2a to POL2d from the logic circuit 182 to generate the data voltages in the column direction. Shift the polarity. In addition, the data driving circuit 183 shifts the polarities of the data voltages along the row direction in response to the horizontal output inversion signal HINV from the logic circuit 182 as shown in FIG. 16.

The timing controller 101, the image analysis circuit 181, and the logic circuit 182 may be integrated into one chip.

As described above, the liquid crystal display device and the driving method thereof according to the embodiment of the present invention invert the polarity of the data voltage supplied to the liquid crystal cells in units of two frame periods, and the data voltage in a horizontal two dot and vertical two dot manner. The polarity of is controlled and the polarity of the data voltage is shifted in the row direction and the column direction by one frame period. As a result, the data voltage supplied to the liquid crystal cell is inverted in units of two frame periods to prevent direct current afterimage, and the liquid crystal cells around the liquid crystal cell are inverted in units of one frame period so that the spatial frequency of the data voltage on the display screen is increased. Since it is faster, flicker can be prevented.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with scan pulses and having a plurality of liquid crystal cells; Generating a first polarity control signal, a second polarity control signal different from the first polarity control signal, and a third polarity control signal that is in phase out of the first polarity control signal and an inverse phase of the second polarity control signal; A logic circuit for generating a polarity control signal and a horizontal output inversion signal in which logic is inverted in units of one frame period; In response to the polarity control signals, the polarity of the data voltages to be supplied to the data lines is shifted along the column direction of the liquid crystal cells in units of one frame period, and the polarity of the data voltages is adjusted in response to the horizontal output inversion signal. A data driving circuit shifting the liquid crystal cells along the row direction in units of one frame period; And And a gate driving circuit for supplying the scan pulses to the gate lines. The method of claim 1, The polarity control signal, Liquid crystal display device characterized in that the logic is reversed in units of two horizontal periods. The method of claim 1, The liquid crystal cells arranged in rows 4j (j are integers greater than 0) +1 and 4j + 2 in columns 4i (i are integers greater than 0) +1 and 4i + 2 during the Nth frame period have positive polarity. A data voltage is supplied, and a negative data voltage is supplied to the liquid crystal cells arranged in rows 4j + 1 and 4j + 2 in columns 4i + 3 and 4i + 4. The negative data voltages are supplied to the liquid crystal cells arranged in rows 4j + 3 and 4j + 4 in columns 4i + 2 and the fourth j + 3 in columns 4i + 3 and 4i + 4. And the data voltages having a positive polarity are supplied to the liquid crystal cells arranged in the fourth j + 4th row. During the N + 1th frame period, the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 4 rows in the fourth i + 2 and fourth i + 3 columns, and the fifth The negative data voltages are supplied to the liquid crystal cells arranged in rows 4j + 1 and 4j + 4 in columns 4i + 1 and 4i + 4, and columns 4i + 2 and 4i + 3 are provided. The negative data voltage is supplied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 rows, and the fourth j + 2 and the fourth j in the fourth i + 1 and fourth i + 4 columns. The positive data voltages are supplied to the liquid crystal cells arranged in a +3 row. During the N + 2th frame period, the positive data voltages are supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 2 rows in the fourth i + 3 and fourth i + 4 columns. The negative data voltages are supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 rows in the 4i + 1 and 4i + 2 columns, and the 4i + 3 and 4i + 4 columns are supplied. The negative data voltages are supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows, and the fourth j + 3 and the fourth j + in the fourth i + 1 and fourth i + 2 columns. The positive data voltages are supplied to the liquid crystal cells arranged in four rows. During the N + 3th frame period, the positive data voltage is supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 4 rows in the fourth i + 1 and fourth i + 4 columns, and the fifth The negative data voltages are supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 4 rows in the 4i + 2 and 4i + 3 columns, and the 4i + 1 and 4i + 4 columns are provided. The negative data voltages are supplied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 rows, and the fourth j + 2 and fourth j in the fourth i + 2 and fourth i + 3 columns. And the data voltage of the positive polarity is supplied to the liquid crystal cells arranged in a +3 row. The method of claim 3, wherein The liquid crystal cells, A first liquid crystal cell group continuously supplied with the same polarity voltage for two frame periods; A second liquid crystal cell group continuously supplied with a voltage of a first polarity and a voltage of a second polarity during the two frame periods; In each of the frame periods, the liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged along a row direction and a column direction; And the position of the first liquid crystal cell group and the position of the second liquid crystal cell group are changed in units of one frame period. The method of claim 1, During the Nth frame period, positive electrodes are included in the liquid crystal cells arranged in rows 4j (j is an integer of 0 or more) +1 and 4j + 2 in columns 4i (i is an integer of 0 or more) +1 and 4i + 4. A negative data voltage is supplied, a negative data voltage is supplied to the liquid crystal cells arranged in rows 4j + 1 and 4j + 2 in columns 4i + 2 and 4i + 3, and the 4i + 1 And the negative data voltage is supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows in the fourth i + 4 column, and the fourth j in the fourth i + 2 and fourth i + 3 columns. The liquid crystal cells arranged in the +3 and 4j + 4 rows are supplied with the positive data voltage, During the N + 1th frame period, the positive data voltages are supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 4 rows in the fourth i + 3 and fourth i + 4 columns. The negative data voltages are supplied to the liquid crystal cells arranged in rows 4j + 1 and 4j + 4 in columns 4i + 1 and 4i + 2, and columns 4i + 3 and 4i + 4 are provided. The negative data voltage is supplied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 rows, and the fourth j + 2 and the fourth j in the fourth i + 1 and fourth i + 2 columns. The positive data voltages are supplied to the liquid crystal cells arranged in a +3 row. During the N + 2th frame period, the positive data voltages are supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 4 rows in the fourth i + 2 and fourth i + 3 columns, The negative data voltages are supplied to the liquid crystal cells arranged in rows 4j + 1 and 4j + 4 in columns 4i + 1 and 4i + 4, and columns 4i + 2 and 4i + 3 are provided. The negative data voltage is supplied to the liquid crystal cells arranged in the fourth j + 2 and fourth j + 3 rows, and the fourth j + 2 and the fourth j in the fourth i + 1 and fourth i + 4 columns. The positive data voltages are supplied to the liquid crystal cells arranged in a +3 row. During the N + 3th frame period, the positive data voltages are supplied to the liquid crystal cells arranged in the fourth j + 1 and fourth j + 2 rows in the fourth i + 1 and fourth i + 2 columns, The negative data voltages are supplied to the liquid crystal cells arranged in the 4j + 1 and 4j + 2 rows in the 4i + 3 and 4i + 4 columns, and the 4i + 1 and 4i + 2 columns are provided. The negative data voltage is supplied to the liquid crystal cells arranged in the fourth j + 3 and fourth j + 4 rows, and the fourth j + 3 and fourth j in the fourth i + 3 and fourth i + 4 columns. And the positive data voltage is supplied to the liquid crystal cells arranged in a +4 row. The method of claim 5, wherein The liquid crystal cells, A first liquid crystal cell group continuously supplied with the same polarity voltage for two frame periods; A second liquid crystal cell group in which a voltage of a first polarity and a voltage of a second polarity are continuously supplied during the two frame periods, The first liquid crystal cell group includes liquid crystal cells arranged in the fourth i + 1 and fourth i + 3 columns during the Nth frame period and the N + 2th frame period, and the second liquid crystal cell group includes the fourth i + 2 and Liquid crystal cells arranged in a fourth i + 4 column, And the liquid crystal cells of the first liquid crystal cell group and the liquid crystal cells of the second liquid crystal cell group are alternately arranged in row and column directions, respectively, during the N + 1th frame period and the N + 3th frame period. . A liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with scan pulses and having a plurality of liquid crystal cells; An image analysis circuit for analyzing digital video data of the input image; The first polarity control signal and the second polarity control signal different from the first polarity control signal are generated when data that may cause a DC residual image is input according to the output of the image analysis circuit. A logic circuit for generating a third polarity control signal that is in phase and a fourth polarity control signal that is in phase of the second polarity control signal and a horizontal output inversion signal in which logic is inverted in units of one frame period; In response to the polarity control signals, the polarity of the data voltages to be supplied to the data lines is shifted along the column direction of the liquid crystal cells in units of one frame period, and the polarity of the data voltages is adjusted in response to the horizontal output inversion signal. A data driving circuit shifting along the row direction of the liquid crystal cells in units of one frame period; And And a gate driving circuit for supplying the scan pulses to the gate lines. A method of driving a liquid crystal display device having a liquid crystal display panel having a plurality of data lines supplied with a data voltage and a plurality of gate lines supplied with a scan pulse and having a plurality of liquid crystal cells, Generating a first polarity control signal, a second polarity control signal different from the first polarity control signal, and a third polarity control signal that is in phase out of the first polarity control signal and an inverse phase of the second polarity control signal; Generating a polarity control signal and generating a horizontal output inversion signal in which logic is inverted in units of one frame period; In response to the polarity control signals, the polarity of the data voltages to be supplied to the data lines is shifted along the column direction of the liquid crystal cells in units of one frame period, and the polarity of the data voltages is adjusted in response to the horizontal output inversion signal. Shifting along the row direction of the liquid crystal cells in units of one frame period; And And supplying the scan pulses to the gate lines. A driving method of a liquid crystal display apparatus having a liquid crystal display panel having a plurality of data lines supplied with a data voltage and a plurality of gate lines supplied with a scan pulse and having a plurality of liquid crystal cells, Analyzing digital video data of the input image; As a result of the image analysis, when data in which a direct current residual image may appear is generated, a first polarity control signal and a second polarity control signal different from the first polarity control signal are generated, Generating a fourth polarity control signal that is in phase of the third polarity control signal and the second polarity control signal and a horizontal output inversion signal in which logic is inverted in units of one frame period; In response to the polarity control signals, the polarity of the data voltages to be supplied to the data lines is shifted along the column direction of the liquid crystal cells in units of one frame period, and the polarity of the data voltages is adjusted in response to the horizontal output inversion signal. Shifting the liquid crystal cell along the liquid crystal cell direction in units of one frame period; And supplying the scan pulses to the gate lines.

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