KR20080099484A - Transistor in semiconductor device and method for manufacturing the same - Google Patents

Transistor in semiconductor device and method for manufacturing the same Download PDF

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Publication number
KR20080099484A
KR20080099484A KR1020070045063A KR20070045063A KR20080099484A KR 20080099484 A KR20080099484 A KR 20080099484A KR 1020070045063 A KR1020070045063 A KR 1020070045063A KR 20070045063 A KR20070045063 A KR 20070045063A KR 20080099484 A KR20080099484 A KR 20080099484A
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South Korea
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width
pattern
height
gate
conductive film
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KR1020070045063A
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Korean (ko)
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이상현
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주식회사 하이닉스반도체
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Priority to KR1020070045063A priority Critical patent/KR20080099484A/en
Publication of KR20080099484A publication Critical patent/KR20080099484A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

The RC delay(RC delay) is decreased according to the gate resistance reduction by increasing the total area of the gate electrode. And the IDRIVE(current drivability) is improved. The transistor of the semiconductor device comprises a semiconductor substrate(10): a gate insulating layer(11) formed on the semiconductor substrate; a first conductive layer pattern(12) having the first width same as the gate length determined in advance, formed on the gate insulating layer; a second conductive layer pattern having the second width which is greater than the first width(13); a gate electrode having a third conductive layer pattern(14) having the third width smaller than the second width.

Description

Transistor of semiconductor device and manufacturing method therefor {TRANSISTOR IN SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view for comparing a transistor structure according to an embodiment of the present invention with a transistor structure according to the prior art.

2A through 2K are cross-sectional views illustrating a method of manufacturing a transistor in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10 semiconductor substrate 11 gate insulating film

12: first polysilicon film pattern 13: second polysilicon film pattern

14 third polysilicon film pattern 15 buffer oxide film

16 gate spacer 100 polysilicon gate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a transistor of a semiconductor device and a method of manufacturing the same.

As the degree of integration of semiconductor devices increases, the channel length of the transistors decreases as the size of the device decreases. In the past, in general, when the channel length of a transistor decreased, the channel resistance was reduced to obtain a current gain. However, as the design rule of semiconductor devices has recently been reduced to less than the nanometer level, it is no longer possible to secure a current gain due to the channel length reduction of the transistor. This is because of the following reasons.

First, securing the current gain according to the decrease in the channel length of the transistor is possible because the current increases due to an increase in the inversion charge while the thickness of the gate oxide film decreases at a constant rate as the gate length decreases. However, as the size of the device has been further reduced in recent years, the gate leakage characteristic has sharply decreased, so that the thickness of the gate oxide film cannot be reduced as the gate length decreases. That is, as the thickness of the gate oxide film is limited, the current gain is reduced even if the transistor channel length is reduced.

In addition, as the short channel effect occurs due to the decrease in the channel length of the transistor, the mobility is lowered and the current gain is similarly reduced.

Therefore, there is a need for the development of a technique capable of securing a current gain even if the channel length of the transistor is reduced.

The present invention has been proposed to solve the above problems of the prior art, while maintaining the channel length of the transistor while forming the upper portion of the gate electrode having a larger width than the lower portion to increase the total area of the gate electrode, thereby reducing the gate resistance Accordingly, an object of the present invention is to provide a transistor of a semiconductor device and a method of manufacturing the same, which enable a high speed operation of the device by reducing RC delay and improving current drivability.

A transistor of the present invention for achieving the above object is a semiconductor substrate; A gate insulating film on the semiconductor substrate; And a first conductive layer pattern formed on the gate insulating layer and having a first width equal to a predetermined gate length, a second conductive layer pattern having a second width greater than the first width, and a third smaller than the second width. The third conductive film pattern having a width includes a gate electrode sequentially stacked.

In addition, the transistor manufacturing method of the present invention for achieving the above object comprises the steps of forming a gate insulating film on a semiconductor substrate; Forming a first conductive film pattern having a first width equal to a predetermined gate length and an oxide film on both sides of the first conductive film pattern on the gate insulating film; Forming a second conductive film on the first conductive film pattern and the oxide film; Forming a first mask pattern having a second width greater than the first width on the second conductive film; Etching the second conductive layer using the first mask pattern as an etching barrier to form a second conductive layer pattern having the second width; Etching the oxide layer using the first mask pattern as an etching barrier to form a buffer oxide layer aligned with the second conductive layer pattern on both sidewalls of the first conductive layer pattern; Removing the first mask pattern; And forming a third conductive film pattern having a third width smaller than the second width on the second conductive film pattern, wherein the first conductive film pattern, the second conductive film pattern, and the third conductive film pattern are formed. A gate electrode in which conductive film patterns are sequentially stacked is formed.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1 is a cross-sectional view for comparing a transistor structure according to an embodiment of the present invention with a transistor structure according to the prior art. 1A is a cross-sectional view of a transistor according to an embodiment of the present invention, and FIGS. 1B and 1C are cross-sectional views of a transistor according to the prior art.

As shown in FIG. 1A, a transistor according to an embodiment of the present invention includes a semiconductor substrate 10, a gate insulating film 11 on a semiconductor substrate, and a polysilicon gate electrode 100 on a gate insulating film. .

At this time, the polysilicon gate electrode 100 is formed in a different width of the upper, middle and lower portions thereof. That is, the second polysilicon layer pattern 13 forming the first width w1 of the first polysilicon layer pattern 12 forming the lower portion of the polysilicon gate electrode 100 and the middle portion of the polysilicon gate electrode 100. The second width w2 of the third polysilicon film pattern 14 forming the upper portion of the polysilicon gate electrode 100 is formed differently.

Here, the first polysilicon film pattern 12 is a film in contact with the surface of the semiconductor substrate 10 to determine the channel length of the transistor. Since the present invention aims to reduce the gate resistance while maintaining the conventional transistor channel length, the first width w1 of the first polysilicon film pattern 12 is determined according to the design rule of the semiconductor device. It is formed similarly to (Lg) (see FIG. 1C).

Since the second polysilicon film pattern 13 is for increasing the total area of the gate, the second width w2 of the second polysilicon film pattern 13 is defined by the first width of the first polysilicon film pattern 12. It is formed larger than w1).

The third width w3 of the third polysilicon film pattern 14 is smaller than the second width w2 of the second polysilicon film pattern 13 to secure a margin for a subsequent contact process. On the other hand, it is preferable to form larger than the first width w1 of the first polysilicon film pattern 12.

Here, in particular, buffer oxide films 15 aligned with the second polysilicon film patterns 13 are formed on both sidewalls of the first polysilicon film pattern 12. Therefore, when the width of the buffer oxide film 15 on one side wall of the first polysilicon film pattern 12 is w0, the following equation (1) is satisfied.

w2 ≒ w1 + w0 * 2... … (One)

In addition, it is preferable that the third width w3 of the third polysilicon film pattern 14 having a width larger than the first width w1 and smaller than the second width w2 satisfies the following equation (2). .

w3 ≒ w1 + w0. … (2)

On the other hand, since the present invention aims to reduce the gate resistance while maintaining the conventional gate height, the total height of the polysilicon gate electrode 100 is formed to be equal to the predetermined conventional gate total height Lh (Fig. 1). (b)).

 Here, the first height h1 of the first polysilicon film pattern 12 is preferably about 10% of the predetermined total gate height Lh, and the second height of the second polysilicon film pattern 13 is increased. (h2) is preferably about 75% of the total gate height (Lh). Therefore, the third height h3 of the third polysilicon film pattern 14 is about 15% of the total height Lh of the gate.

In summary, the gate electrode 100 according to an exemplary embodiment of the present invention may include a first polysilicon layer pattern 12, a second width w2, and a first width w1 and a first height h1. The second polysilicon film pattern 13 having the second height h2 and the third polysilicon film pattern 14 having the third width w3 and the third height h3 are sequentially stacked. At this time, the first width w1 is defined to be the same as the conventional gate length Lg, and the expression w2> w3> w1 is satisfied. In addition, while h1 + h2 + h3 is the same as the conventional gate height Lh, the formula of h2> h3> h1 is satisfied.

Gate spacers 16 are formed on both sidewalls of the polysilicon gate electrode 100 including the buffer oxide layer 15 formed on both sidewalls of the first polysilicon layer pattern 12.

That is, through the structure of the polysilicon gate electrode 100 according to the embodiment of the present invention, while maintaining the conventional gate length Lg and the gate height Lh, the total area of the gate is increased, and the RC delay according to the gate resistance decreases. It is possible to reduce and improve the current driving capability. In addition, it is possible to secure a subsequent contact process margin.

2A through 2K are cross-sectional views illustrating a method of manufacturing a transistor according to an embodiment of the present invention.

As shown in FIG. 2A, a gate insulating film 21 is formed on a semiconductor substrate 20 on which a predetermined process such as a device isolation process and a well formation is performed.

Subsequently, after the first polysilicon film 22 is formed on the gate insulating film 21 as the conductive film for the gate electrode, the first polysilicon film 22 is patterned by a mask and an etching process to form a first width w1. A first polysilicon film pattern 22a having a structure is formed. Here, the first polysilicon layer pattern 22a is a layer forming the bottom of the gate electrode and is in contact with the surface of the semiconductor substrate 20 to determine the channel length of the transistor. Therefore, the first width w1 of the first polysilicon film pattern 22a is formed in the same manner as in the prior art. That is, the first width w1 of the first polysilicon film pattern 22a is formed to be equal to the predetermined gate length Lg according to the design rule of the semiconductor device.

As shown in Fig. 2B, the LPTEOS film 23 for the buffer oxide film is formed on the resultant including the first polysilicon film pattern 22a. Here, the buffer oxide film is a film that acts to relieve stress between the gate spacer and the polysilicon gate electrode formed in a subsequent process.

Subsequently, a chemical mechanical polishing (CMP) process is performed until the first polysilicon film pattern 22a has a desired height (see dotted line), thereby forming a first having a first width w1 and a first height h1. 1 Polysilicon film pattern 22a is formed. As a result of the CMP process, the LPTEOS film pattern 23a having the same height as the first height h1 of the first polysilicon film pattern 22a is formed on the semiconductor substrate 20 on both sides of the first polysilicon film pattern 22a. Is formed. In this case, the first height h1 of the first polysilicon layer pattern 22a may be about 10% of the total height Lh of the predetermined gate.

As shown in Fig. 2C, a second polysilicon film 24 is formed as a conductive film for the gate electrode on the first polysilicon film pattern 22a and the LPTEOS film pattern 23a having the planarized surface. At this time, the second polysilicon film 24 is formed by performing a deposition process until the desired height, the height of the second polysilicon film 24 formed as described above is referred to as a second height (h2). The second height h2 of the second polysilicon film 24 is preferably about 75% of the total height Lh of the predetermined gate.

Subsequently, after forming a mask pattern 25 for patterning the second polysilicon film 24 on the second polysilicon film 24, the mask pattern 25 is used as an etching barrier to form the second polysilicon film 24. ) Is etched to form a second polysilicon film pattern 24a having a second height h2 and a second width w2. Here, since the second polysilicon film pattern 24a is to increase the total area of the gate, the second width w2 of the second polysilicon film pattern 24a is the first of the first polysilicon film pattern 22a. It is formed to be larger than the width w1.

Subsequently, the mask pattern 25 is etched to align the LPTEOS film pattern 23a with the second polysilicon film pattern 24a as an etching barrier, and the etched LPTEOS film pattern 23a is hereinafter referred to as a buffer oxide film. It is called (23b). As a result of the process of this figure, when the width of the buffer oxide film 23b of one side wall of the first polysilicon film pattern 22a is w0, the following equation (3) is satisfied.

w2 ≒ w1 + w0 * 2... … (3)

As shown in FIG. 2D, after removing the mask pattern 25, a substrate resultant is used to cure damage caused by the etching of the semiconductor substrate 20, the second polysilicon layer pattern 24a, and the like. Processing such as light oxidation is performed. As a result, a thin oxide film (not shown) is formed on the exposed surface of the semiconductor substrate 20 or on the second polysilicon film pattern 24a. This thin oxide film serves to relieve the stress between the subsequent gate capping film and the polysilicon gate electrode.

Subsequently, a gate capping film 26 made of a nitride film is formed along the profile of the substrate resultant. The gate capping layer serves to prevent impurities from diffusing into the second polysilicon layer pattern 24a or the like upon deposition of a subsequent BPSG (Boron Phospho Silicate Glass) layer.

As shown in Fig. 2E, the BPSG film 27 is formed as an insulating film for trench formation on the gate capping film 26 to form a trench defining a region where a subsequent third polysilicon film pattern is to be formed. Deposit. As described above, since the gate capping layer 26 is formed on the resultant material including the second polysilicon layer pattern 24a, it is possible to prevent diffusion of impurities in the BPSG layer 27 when the BPSG layer 27 is deposited. .

Subsequently, in order to eliminate the step difference of the BPSG film 27, a planarization process such as CMP is performed until the BPSG film 27 remains a predetermined thickness over the second polysilicon film pattern 24a (see the dotted line). The planarized BPSG film 27 is hereinafter referred to as BPSG film pattern 27a.

As shown in FIG. 2F, a mask pattern 28 is formed on the BPSG film pattern 27a to expose a region where a subsequent third polysilicon film pattern is to be formed. In this case, the width w3 of the region exposed by the mask pattern 28 is equal to the width of the subsequent third polysilicon film pattern, and is formed larger than the first width w1 and smaller than the second width w2. Preferably, the following formula (4) is satisfied.

w3 ≒ w1 + w0. … (4)

As shown in Fig. 2G, the BPSG film pattern 27a is etched using the mask pattern 28 as an etching barrier.

Subsequently, the second polysilicon layer pattern 24a is removed by over-etching the gate capping layer 26 using the mask pattern 28 as an etch barrier to remove the gate capping layer 26 and a thin oxide layer thereunder. A trench T is formed to be exposed. This trench T defines a region where a subsequent third polysilicon film pattern is to be formed.

As shown in FIG. 2H, after removing the mask pattern 28, a third polysilicon film 29 is formed on the resultant product including the trench T. Referring to FIG.

Subsequently, the CMP process is performed until the BPSG film pattern 27a is exposed to form the third polysilicon film pattern 29a embedded in the trench T. In this case, the CMP process is performed until the third polysilicon layer pattern 29a has a desired height (see dotted line), and accordingly, a third poly having a third width w3 and a third height h3 The silicon film pattern 29a is formed. Accordingly, it can be seen that the height at which the third polysilicon film 29 is initially deposited should be formed to be larger than the third height h3 for the CMP.

As described above, the third width w3 of the third polysilicon film pattern 29a is formed larger than the first width w1 and smaller than the second width w2, and preferably, Satisfies 4). In addition, as described above, the first height h1 is about 10% of the total height Lh of the predetermined gate, and the second height is about 75% of the total height Lh of the predetermined gate. The height h3 is about 15% of the total height Lh of the predetermined gate.

As such, reducing the third width w3 of the third polysilicon film pattern 29a compared to the second width w2 of the second polysilicon film pattern 24a is to secure a margin for a subsequent contact process. . That is, if the upper width of the gate is continuously increased to increase the area of the gate, it is advantageous to reduce the gate resistance, but it is difficult to secure a contact margin in a subsequent bitline contact process, and so on. Likewise, the top width of the gate is reduced again.

Hereinafter, a structure in which the first polysilicon film pattern 22a, the second polysilicon film pattern 24a, and the third polysilicon film pattern 29a are stacked is referred to as a polysilicon gate electrode 200.

As shown in FIG. 2I, after the mask pattern 30 is formed on the third polysilicon film pattern 29a to protect the third polysilicon film pattern 29a, the mask pattern 30 is formed as an etching barrier. The third polysilicon layer pattern 29a and the BPSG layer pattern 27a on both sides of the gate capping layer 26 are etched and removed. In this case, the gate capping layer 26 serves as an etching barrier to prevent etching of the second polysilicon layer pattern 24a, the first polysilicon layer pattern 22a, and the buffer oxide layer 23b.

As shown in FIG. 2J, the gate capping layer 26 is vertically etched to remove the mask pattern 30 as an etch barrier. In this case, the gate capping layer 26 on the plane may be removed, such as the upper portion of the semiconductor substrate 20 or the upper portion of the second polysilicon layer pattern 24a, whereas the second polysilicon layer pattern 24a may be removed. The gate capping film 26 on the sidewall of the buffer oxide film 23b is not removed and remains.

Subsequently, after the oxidation process is performed to cure damage caused to the gate insulating film 21 due to etching, the mask pattern 30 is removed.

 As shown in FIG. 2K, after the nitride film for the gate spacer is formed on the entire structure of the resultant structure, a spacer etch is performed to form the gate spacer 31.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The transistor of the semiconductor device and the method of manufacturing the same according to the present invention described above are formed such that the upper portion of the gate electrode has a larger width than the lower portion while maintaining the channel length of the transistor, thereby increasing the total area of the gate electrode, thereby reducing the gate resistance. Reducing RC delay and improving current drivability enable the device's high-speed operation.

Claims (27)

Semiconductor substrates; A gate insulating film on the semiconductor substrate; And A first conductive film pattern formed on the gate insulating film and having a first width equal to a predetermined gate length, a second conductive film pattern having a second width greater than the first width, and a third width smaller than the second width; A gate electrode in which a third conductive film pattern having a structure is sequentially stacked Transistor comprising a. The method of claim 1, The third width is greater than the first width transistor. The method according to claim 1 or 2, The first conductive layer pattern, the second conductive layer pattern, and the third conductive layer pattern may be formed of a polysilicon layer. transistor. The method according to claim 1 or 2, A buffer oxide film formed on the semiconductor substrate on both sidewalls of the first conductive film pattern More, Here, when the width of the buffer oxide film on one side wall of the first conductive film pattern is a fourth width, the buffer oxide film is aligned with the second conductive film pattern to satisfy the following <Relational Expression>. transistor. <Relationship> (The second width) ≒ (the first width) + (the fourth width) * 2 The method of claim 4, wherein The third width satisfies the following relational expression. transistor. <Relationship> (The third width) ≒ (the first width) + (the fourth width) The method of claim 1, The first conductive film pattern has a first height, the second conductive film pattern has a second height greater than the first height, and the third conductive film pattern is greater than the first height and greater than the second height. Has a small third height, Here, the sum of the first height, the second height and the third height is equal to a predetermined gate height. transistor. The method of claim 6, The first height has a value of 10% of the predetermined gate height, the second height has a value of 75% of the predetermined gate height, and the third height has a value of 15% of the predetermined gate height transistor. The method of claim 1, Gate spacers on both sidewalls of the gate electrode The transistor further comprising. The method of claim 4, wherein Gate spacers on both sidewalls of the buffer oxide layer, the second conductive layer pattern, and the third conductive layer pattern The transistor further comprising. The method of claim 4, wherein The buffer oxide film is made of an LPTEOS film transistor. Forming a gate insulating film on the semiconductor substrate; Forming a first conductive film pattern having a first width equal to a predetermined gate length and an oxide film on both sides of the first conductive film pattern on the gate insulating film; Forming a second conductive film on the first conductive film pattern and the oxide film; Forming a first mask pattern having a second width greater than the first width on the second conductive film; Etching the second conductive layer using the first mask pattern as an etching barrier to form a second conductive layer pattern having the second width; Etching the oxide layer using the first mask pattern as an etch barrier to form a buffer oxide layer aligned with the second conductive layer pattern on both sidewalls of the first conductive layer pattern; Removing the first mask pattern; And Forming a third conductive film pattern having a third width smaller than the second width on the second conductive film pattern Including a, the first conductive film pattern, the second conductive film pattern and the third conductive film pattern to form a gate electrode sequentially stacked Transistor manufacturing method. The method of claim 11, The third width is greater than the first width Transistor manufacturing method. The method of claim 11, When the width of the buffer oxide film on one side wall of the first conductive film pattern is referred to as a fourth width, the second width satisfies the following relational expression. Transistor manufacturing method. <Relationship> (The second width) ≒ (the first width) + (the fourth width) * 2 The method of claim 12, When the width of the buffer oxide film on one side wall of the first conductive film pattern is referred to as a fourth width, the third width satisfies the following relational expression. Method of manufacturing a transistor. <Relationship> (The third width) ≒ (the first width) + (the fourth width) The method of claim 11, The first conductive layer pattern, the second conductive layer pattern, and the third conductive layer pattern may be formed of a polysilicon layer. Transistor manufacturing method. The method of claim 11, The oxide film is an LPTEOS film Transistor manufacturing method. The method of claim 11, The first conductive film pattern has a first height, the second conductive film pattern has a second height greater than the first height, and the third conductive film pattern is greater than the first height and greater than the second height. Has a small third height, Here, the sum of the first height, the second height and the third height is equal to a predetermined gate height. Transistor manufacturing method. The method of claim 17, The first height has a value of 10% of the predetermined gate height, the second height has a value of 75% of the predetermined gate height, and the third height has a value of 15% of the predetermined gate height Transistor manufacturing method. The method of claim 17 or 18, The oxide film forming step of both the first conductive film pattern and the first conductive film pattern, Forming a first conductive film on the gate insulating film; Selectively etching the first conductive layer to cause the first conductive layer to have the first width; Forming the oxide film on the entire structure of the resultant product; And Performing a CMP process on the first conductive film and the oxide film until the first conductive film has the first height, Forming the oxide layer having the same height as the first conductive layer pattern on both sides of the first conductive layer pattern and the first conductive layer pattern having the first width and the first height; Transistor manufacturing method. The method of claim 17 or 18, The second conductive film forming step, The deposition process is performed until the second conductive film reaches the second height. Transistor manufacturing method. The method of claim 17 or 18, The third conductive film pattern forming step, Forming a gate capping layer along a profile of water as a result of the formation of the first conductive layer pattern, the buffer oxide layer, and the second conductive layer pattern; Forming an insulating film on the gate capping film; Forming a second mask pattern exposing a region where a trench is to be formed on the insulating layer; Sequentially etching the insulating layer and the gate capping layer using the second mask pattern as an etch barrier to form the trench having the third width; Forming a third conductive film on the resultant product including the trench; And Performing the CMP process until the third conductive film reaches the third height, thereby forming the third conductive film pattern having the third width and the third height. Transistor manufacturing method. The method of claim 21, The gate capping film is made of a nitride film Transistor manufacturing method. The method of claim 21, The insulating film is made of a BPSG film Transistor manufacturing method. The method of claim 21, The trench forming step, The gate capping layer is excessively etched to expose the second conductive layer pattern. Transistor manufacturing method. The method of claim 21, After performing the CMP process, And vertically etching the gate capping layer to remain on sidewalls of the buffer oxide layer and the second conductive layer pattern. Transistor manufacturing method. The method of claim 11, Forming gate spacers on both sidewalls of the buffer oxide layer, the second conductive layer pattern, and the third conductive layer pattern Transistor manufacturing method further comprising. The method of claim 25, After the gate capping layer is vertically etched, Forming gate spacers on both sidewalls of the remaining gate capping layer and the third conductive layer pattern; Transistor manufacturing method.
KR1020070045063A 2007-05-09 2007-05-09 Transistor in semiconductor device and method for manufacturing the same KR20080099484A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8916878B2 (en) 2012-09-19 2014-12-23 Samsung Display Co., Ltd. Thin film transistor and organic light-emitting display apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8916878B2 (en) 2012-09-19 2014-12-23 Samsung Display Co., Ltd. Thin film transistor and organic light-emitting display apparatus

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