KR101110545B1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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KR101110545B1
KR101110545B1 KR1020090108121A KR20090108121A KR101110545B1 KR 101110545 B1 KR101110545 B1 KR 101110545B1 KR 1020090108121 A KR1020090108121 A KR 1020090108121A KR 20090108121 A KR20090108121 A KR 20090108121A KR 101110545 B1 KR101110545 B1 KR 101110545B1
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method
pillar
semiconductor device
contact hole
formed
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KR1020090108121A
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Korean (ko)
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KR20110051506A (en
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김승환
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주식회사 하이닉스반도체
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10823Dynamic random access memory structures with one-transistor one-capacitor memory cells the transistor having a trench structure in the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10873Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the transistor
    • H01L27/10876Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the transistor the transistor having a trench structure in the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10882Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line
    • H01L27/10885Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line with at least one step of making a bit line
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10882Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line
    • H01L27/10888Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line with at least one step of making a bit line contact

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and to disclose a technique of forming a junction barrier in a contact hole when forming a buried bit line, and then forming a junction in a pillar bottom to improve device characteristics.
A method of manufacturing a semiconductor device according to the present invention may include forming a plurality of pillar patterns by etching a semiconductor substrate, depositing an insulating layer on a surface of the pillar pattern, and removing a portion of the insulating layer on one side of the pillar pattern. Forming a contact hole to which the pillar pattern is exposed, forming a barrier layer in the contact hole, and forming a junction in the pillar pattern in contact with the contact hole.
The semiconductor device may further include a plurality of pillar patterns, a contact hole formed at one side of the pillar pattern, a barrier layer embedded in the contact hole, a junction formed in the pillar pattern in contact with the contact hole, and the pillar. A buried bit line is formed at a bottom portion between the patterns in contact with the contact hole.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a method for manufacturing a semiconductor device having a vertical channel transistor.

As the degree of integration of semiconductor devices increases, the channel length of the transistors gradually decreases. However, the reduction in the channel length of such transistors has a problem of causing short channel effects such as a drain induced barrier lowering (DIBL) phenomenon, a hot carrier effect, and a punch through. To solve this problem, various methods have been proposed, such as a method of reducing the depth of the junction region or a method of increasing the channel length relatively by forming a recess in the channel region of the transistor.

However, as the integrated density of semiconductor memory devices, especially DRAM, approaches giga bits, smaller transistor sizes are required. That is, a transistor of a gigabit DRAM device requires an element area of 8F2 (F: minimum feature size) or less, and further requires an element area of about 4F2. Therefore, the current planar transistor structure in which the gate electrode is formed on the semiconductor substrate and the junction regions are formed on both sides of the gate electrode is difficult to satisfy the required device area even when the channel length is scaled.

In order to solve this problem, a vertical channel transistor structure has been proposed.

Although not shown, a brief description of a method of manufacturing a vertical channel transistor is as follows.

First, a top pillar is formed by etching a cell region of a semiconductor substrate to a predetermined depth through a photo process, and then forming spacers surrounding sidewalls of the top pillar. Next, the semiconductor substrate is further etched using the spacers as an etch mask to form a trench, and then an isotropic wet etching process is performed on the trench to integrally form the lower pillar and extend in a vertical direction. To form a neck pillar. At this time, the lower pillar is formed to have a narrower width than the upper pillar.

Next, a rounding gate including a gate insulating film and a gate conductive film is formed on the outer sidewall of the lower pillar, and ion implantation is performed on the semiconductor substrate adjacent to the rounding gate to form a bit line impurity region. Subsequently, the semiconductor substrate is etched to a depth where the impurity regions are separated to form buried bit lines in which the impurity regions are separated. In this case, in order to prevent a short circuit between the buried bit lines, the semiconductor substrate needs to be etched very deeply.

Subsequently, subsequent known processes are sequentially performed to complete a semiconductor device having a vertical transistor according to the prior art.

However, in the method of separating the buried bit lines by etching the semiconductor substrate, it is difficult to secure the dimensions necessary for the process as the integration degree of the semiconductor device increases and the line width of the buried bit lines decreases.

In addition, if a high concentration of ion implantation is performed directly on the silicon substrate when the buried bit line is formed, a body floating phenomenon is caused by the diffusion of impurities, thereby degrading the performance of the transistor. However, when the doping concentration is decreased during the ion implantation process, the resistance of the buried bit line is increased.

In order to solve such a problem, a method of making a bit line contact only on one side of a pillar has been proposed. However, in the process of forming the junction under the pillar, there is a problem in that the area of the junction is increased by a heat treatment process, which causes deterioration of drain induced barrier lowering (DIBL) and leakage current between cells.

The present invention is to improve the characteristics of the device by forming a diffusion barrier in the buried bit line contact hole.

A method of manufacturing a semiconductor device according to the present invention may include forming a plurality of pillar patterns by etching a semiconductor substrate, depositing an insulating layer on a surface of the pillar pattern, and removing a portion of the insulating layer on one side of the pillar pattern. Forming a contact hole to which the pillar pattern is exposed, forming a barrier layer on a surface of the insulating layer including the contact hole, and forming a junction in the pillar pattern in contact with the contact hole. It features.

In this case, the insulating layer is formed of a nitride film, the barrier film is a TiSi 2 film, and the TiSi 2 film is formed in a portion in contact with the pillar pattern in the process of depositing a Ti film. Here, the Ti film uses TiCl 4 , and is formed by a PECVD process. In this case, as the PECVD process is performed at 650 to 850 ° C, the Ti film embedded in the contact hole reacts with the silicon layer of the pillar pattern to be transformed into a TiSi 2 film. The Ti film is formed to a thickness of 20 to 30 mm 3.

A TiN film is further deposited on the barrier film surface. At this time, the TiN film is formed to a thickness of 30 ~ 40Å.

After the polysilicon layer is formed on the pillar pattern, an annealing process is performed to diffuse the dopant in the polysilicon layer into the pillar pattern to form a junction. In this case, the polysilicon layer is preferably doped polysilicon doped with phosphorous (Phosphorous). And, the annealing process that proceeds at the junction formation proceeds to a furnace or RTA process.

The method may further include forming a bit line material layer on the entire pillar pattern, and forming a buried bit line on the bottom of the pillar pattern by performing an etch-back process, wherein the bit line material layer is formed of tungsten or It is formed by TiN.

In addition, the semiconductor device may include a plurality of pillar patterns, a contact hole formed at one side of the pillar pattern, a barrier layer embedded in the contact hole, and a junction formed in the pillar pattern in contact with the contact hole. It is done.

Here, the barrier film is TiSi 2 , and further includes a Ti film and a TiN film on the pillar pattern surface. The buried bit line is formed of a tungsten or TiN film.

The present invention has the following effects.

First, resistance is reduced as TiSi 2 is formed in the contact hole, and TiSi 2 may act as a diffusion barrier to form a shallow junction.

Second, in the process of removing the doped polysilicon layer interposed between the pillar patterns, the TiN layer may protect the contact to form a stable contact.

Third, there is an advantage that the resistance is reduced by forming a buried bit line using tungsten or TiN.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

1A to 1F are perspective views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 1A, a hard mask layer (not shown) is formed on the semiconductor substrate 100. The hard mask layer (not shown) is formed using any one selected from an amorphous carbon layer (a-carbon), a silicon oxynitride layer (SiON), an amorphous silicon layer (a-Si), and a combination thereof.

Next, a hard mask layer (not shown) is patterned to form a hard mask pattern 110 defining a buried bit line region.

Next, the semiconductor substrate 100 is etched using the hard mask pattern 110 as a mask to form a plurality of pillars 100a. In this case, the pillar 100a is formed by etching part of the semiconductor substrate 100 in the vertical direction.

Next, an oxidation process is performed to form an oxide film 115 on the surfaces of the pillars 100a and the semiconductor substrate 100. In this case, since the oxidation process reacts with the silicon layer, the surface of the hard mask pattern 110 is not oxidized.

Next, the nitride film 120 is deposited on the surface of the semiconductor substrate 100 including the hard mask pattern 110 and the pillars 100a.

Referring to FIG. 1B, the first polysilicon layer 125 is formed on the entire surface including the hard mask pattern 110 and the pillar 100a on which the nitride film 120 is formed. In this case, the first polysilicon layer 125 uses undoped polysilicon and is preferably formed to a height where the hard mask pattern 110 is not opened.

Next, the CMP process is performed until the nitride film 120 on the upper side of the hard mask pattern 110 is exposed.

Next, the first polysilicon layer 125 is further etched by an etch-back process. In this case, a portion of the hard mask pattern 110 protrudes from the first polysilicon layer 125.

Next, a liner oxide film (not shown) and a liner nitride film (not shown) are deposited on the nitride film 120 and the first polysilicon layer 125 on the surface of the hard mask pattern 110, and then the etch-back process is performed. The first spacer 130 is formed on the surface of the nitride film 120 on the sidewall of the hard mask pattern 110.

Referring to FIG. 1C, a photoresist layer pattern 145 is formed on the nitride layer 120 and the first spacer 130 above the hard mask pattern 110 to open the bit line contact region. Here, the bit line contact is formed on one side of the pillar 100a. Accordingly, the photoresist pattern 145 opens the first spacer 130 on one side of the hard mask pattern 110 and prevents the first spacer 130 on the other side of the hard mask pattern 110 from being opened.

Next, the first spacer 130 and the first polysilicon layer 125 are etched using the photoresist pattern 145 as a mask. In this case, the first polysilicon layer 125 may be etched until the region to form the contact hole is exposed.

Referring to FIG. 1D, the photoresist pattern 145 and the first spacer 130 are removed. At this time, the pillar 100a and the nitride film 120 on one side of the hard mask pattern 110 are also simultaneously removed during the first spacer 130 removal process.

Next, the first polysilicon layer 125 left on the other side of the pillar 100a is removed. As a result, only the oxide film 115 remains on one side of the pillar 100a protruding upward of the first polysilicon layer 125, and the oxide film 115 and the nitride film 120 are formed on the other side of the pillar 100a. Lamination remains.

Then, the second polysilicon layer 150 is embedded in the bottom between the pillars 100a. In this case, the second polysilicon layer 150 may be formed to a height at which the region to form the contact hole is exposed.

Referring to FIG. 1E, a third polysilicon layer 153 is deposited on the second polysilicon layer 150.

Next, a liner nitride film (not shown) is formed on the entire top including the third polysilicon layer 153, the pillar 100a, and the hard mask pattern 110. In addition, the second spacer 155 is formed on the sidewalls of the pillar 100a and the hard mask pattern 110 by an etch-back process.

Referring to FIG. 1F, the third polysilicon layer 153 and the second polysilicon layer 150 are removed. In this case, the space where the third polysilicon layer 153 is removed is formed by the second spacer 155 and the nitride film 120. This space exists only on one side of the pillar 110a, and the oxide film 115 is exposed to this space.

Next, the exposed oxide film 115 is removed by a cleaning process to form a contact hole 160 exposed on the sidewall of the pillar 100a.

Referring to FIG. 1G, a Ti film 170 is deposited on the surface of the pillar 100a and the hard mask pattern 110 including the contact hole 160. At this time, the Ti film 170 proceeds by a PE-CVD method using TiCl 4 . In addition, the thickness of the Ti film 170 is 20-30 kPa. At this time, since the PE-CVD method proceeds at a high temperature of 650 to 850 ° C., the PE-CVD method reacts with the pillar 100a exposed by the contact hole 160 and is transformed into the TiSi 2 film 170a. That is, the TiSi 2 film 170a is buried in the contact hole 160. At this time, the Ti film 170 is formed in portions other than the contact hole 160 as it is.

Then, a TiN film 175 is deposited on the surface of the Ti film 170. Here, the thickness of the TiN film 175 is preferably 30 to 40 kPa.

Referring to FIG. 1H, the fourth polysilicon layer 185 is formed on the entire surface including the pillars 100a and the hard mask pattern 110. At this time, the fourth polysilicon layer 185 is preferably doped polysilicon doped with Phosphorous ions.

Next, a dopant in the fourth polysilicon layer 185 is diffused into the pillar 100a by an annealing process to form a junction 180. The annealing process is performed in a furnace or RTA method, the junction 180 is preferably formed inside the pillar (100a) in contact with the contact hole 160. As the TiSi 2 film 170a is buried in the contact hole 160, the resistance decreases, and the TiSi 2 film 170a is used as a diffusion barrier to form a shallow junction.

Referring to FIG. 1I, the fourth polysilicon layer 185 is removed. Here, the process of removing the fourth polysilicon layer 185 may be performed by dry etching or wet etching. More preferably, after the dry etching, the wet etching is further performed to completely remove the fourth polysilicon layer 185. At this time, since the TiN film 175 is deposited on the pillars 100a and the hard mask pattern 110, the TiSi 2 film 170a filling the contact hole 160 may be protected during dry etching or wet etching. Can be. Thus, a stable contact can be formed.

Next, a bit line material layer is formed on the whole including the pillars 100a and the hard mask pattern 110. Here, the bit line material layer is formed of tungsten or TiN film.

Next, the bit line material layer is etched to the upper side of the contact hole 160 to form a buried bit line 190 for connecting with the TiSi 2 film 170a. In this case, the buried bit line 190 may be formed of a tungsten or TiN film to reduce the resistance.

In addition, referring to FIG. 1I, a semiconductor device having a buried bit line is described as follows. This may be formed by methods other than those described with reference to FIGS. 1A to 1I.

First, a plurality of pillar patterns 100a are provided on the semiconductor substrate 100, and a hard mask pattern 110 is included above the pillar patterns 100a. In addition, the nitride film 120 is deposited on the pillar pattern 100a and the hard mask pattern 110, and the contact hole where the pillar pattern 100a is exposed by removing the nitride layer 120 on one side of the pillar pattern 100a is formed. Formed. In this case, the contact hole is filled with a TiSi 2 film 170a. In addition, a junction 180 is formed inside the pillar pattern 100a in contact with the contact hole.

The Ti film 170 and the TiN film 175 are deposited on the entire surface of the pillar pattern 100a and the hard mask pattern 110 including the contact holes, and the contact is formed at the bottom between the pillar patterns 100a. A buried bit line 190 is formed to connect with the hole. Here, the buried bit line 190 is formed of a tungsten or TiN film.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A to 1I are perspective views illustrating a method of manufacturing a semiconductor device according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

100 semiconductor substrate 100a pillar

110: hard mask pattern 115: oxide film

120: nitride film 125: first polysilicon layer

130: first spacer 145: photosensitive film pattern

150: second polysilicon layer 153: third polysilicon layer

155: second spacer 160: contact hole

170: Ti film 170a: TiSi 2 film

175 TiN film 180 junction

185: fourth polysilicon layer 190: buried bit line

Claims (19)

  1. Etching the semiconductor substrate to form a plurality of pillar patterns;
    Depositing an insulating layer on the pillar pattern surface;
    Removing a portion of the insulating layer on one side of the pillar pattern to form a contact hole exposing the pillar pattern;
    Forming a barrier layer in the contact hole; And
    And forming a junction in the pillar pattern in contact with the contact hole.
  2. The method of claim 1,
    The insulating layer is a method for manufacturing a semiconductor device, characterized in that the nitride film.
  3. The method of claim 1,
    The barrier film is a manufacturing method of a semiconductor device, characterized in that the TiSi 2 film.
  4. The method of claim 3, wherein
    The TiSi 2 film is a method of manufacturing a semiconductor device, characterized in that formed in the portion in contact with the pillar pattern in the process of depositing a Ti film.
  5. The method of claim 4, wherein
    The Ti film using TiCl 4 , characterized in that formed in the PECVD process.
  6. The method of claim 5,
    The PECVD process is a method of manufacturing a semiconductor device, characterized in that proceeding at 650 ~ 850 ℃.
  7. The method of claim 5,
    The Ti film is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 20 ~ 30 kHz.
  8. The method of claim 1,
    A TiN film is further deposited on the barrier film surface.
  9. The method of claim 8,
    The TiN film is a semiconductor device manufacturing method, characterized in that formed to a thickness of 30 ~ 40Å.
  10. The method of claim 1,
    The forming of the junction may include forming a polysilicon layer on the pillar pattern and then performing an annealing process to diffuse the dopant in the polysilicon layer into the pillar pattern.
  11. 11. The method of claim 10,
    The polysilicon layer is a semiconductor device manufacturing method, characterized in that the doped polysilicon.
  12. The method of claim 11,
    The dopant of the doped polysilicon is a manufacturing method of a semiconductor device, characterized in that the (Phosphorous).
  13. 11. The method of claim 10,
    The annealing process is a manufacturing method of a semiconductor device, characterized in that to proceed to the furnace or RTA process.
  14. The method of claim 1,
    After forming a junction in the pillar pattern,
    Forming a bit line material layer over the pillar pattern; And
    And forming a buried bit line at the bottom of the pillar pattern by performing an etch-back process.
  15. The method of claim 14,
    And the bit line material layer is formed of tungsten or TiN.
  16. Multiple pillar patterns;
    A contact hole formed at one side of the pillar pattern;
    A barrier film embedded in the contact hole;
    A junction formed in the pillar pattern in contact with the contact hole; And
    A buried bit line formed by connecting the contact hole to a bottom portion between the pillar patterns;
    A semiconductor device comprising a.
  17. The method of claim 16,
    And the barrier film is TiSi 2 .
  18. The method of claim 16,
    And a Ti film and a TiN film on the pillar pattern surface.
  19. The method of claim 16,
    The buried bit line is a semiconductor device, characterized in that formed by a tungsten or TiN film.
KR1020090108121A 2009-11-10 2009-11-10 Semiconductor device and method for manufacturing the same KR101110545B1 (en)

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US12/816,274 US20110108985A1 (en) 2009-11-10 2010-06-15 Semiconductor device and method for manufacturing the same
TW99120771A TW201117305A (en) 2009-11-10 2010-06-25 Semiconductor device and method for manufacturing the same
JP2010159277A JP2011103436A (en) 2009-11-10 2010-07-14 Semiconductor device and method for manufacturing the same
CN2010102307355A CN102054766A (en) 2009-11-10 2010-07-15 Semiconductor device and method for manufacturing the same

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US10269800B2 (en) * 2017-05-26 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical gate semiconductor device with steep subthreshold slope

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