KR20130023767A - Method for fabricating semiconductor device using single-side-contact - Google Patents

Method for fabricating semiconductor device using single-side-contact Download PDF

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KR20130023767A
KR20130023767A KR1020110086761A KR20110086761A KR20130023767A KR 20130023767 A KR20130023767 A KR 20130023767A KR 1020110086761 A KR1020110086761 A KR 1020110086761A KR 20110086761 A KR20110086761 A KR 20110086761A KR 20130023767 A KR20130023767 A KR 20130023767A
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South Korea
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side wall
trench
ion implantation
implantation region
film
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KR1020110086761A
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Korean (ko)
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표승석
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에스케이하이닉스 주식회사
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Publication of KR20130023767A publication Critical patent/KR20130023767A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can increase the etching selectivity of the doped polysilicon and undoped polysilicon, the semiconductor device manufacturing method of the present invention is a first side wall and the second insulating film Providing a trenched substrate having sidewalls; Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench; Forming a silicon film on the sacrificial layer adjacent to the upper region of the trench; Implanting nitrogen ions into the silicon film in the direction of the first side wall; And selectively removing the non-ion implantation region of the silicon film remaining on the second side wall using a hydroxyl chemical, wherein the present invention selects between an ion implantation region and a nonion implantation region through nitrogen ion implantation. By having a ratio, and by selectively removing the non-ion implantation region using a subsequent hydroxyl chemical it is possible to remove the non-ion implantation region without attack of the surrounding structure.

Description

Method of manufacturing semiconductor device using single side contact {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING SINGLE―SIDE―CONTACT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a single side contact.

As the design rule of the semiconductor device decreases, the cell size decreases, thereby increasing the process difficulty in the 8F 2 or 6F 2 (F is a minimun feature) cell structure. In addition, the short channel margin characteristic is degraded due to the reduction of the gate length.

In order to solve this problem, a method of three-dimensionally processing a semiconductor substrate and thereby three-dimensionally forming a transistor has been proposed. For example, a vertical transistor having a pillar extending in a direction perpendicular to the surface of a semiconductor substrate is used as a channel. Vertical transistors can reduce the footprint and contribute to a reduction in cell size. In addition, the vertical transistor can realize a 4F 2 cell structure by forming the gate and the channel in the vertical direction.

When a vertical transistor using a pillar is used as a cell transistor of a memory device, one side (eg, a source) of a junction that becomes a source or a drain is a bitline. ), And the other side of the junction (eg, drain) is connected to a capacitor. In general, since the capacitor is disposed above the cell transistor, the capacitor is connected to the upper part of the pillar and the bit line is connected to the lower part of the pillar.

A portion of the sidewall of either pillar must be exposed to connect the bitline and one side junction. This is called a SSC (Single-Side-Contact) process or an OSC (One-Side-Contact) OSC process. Hereinafter, it is abbreviated as "singleside contact process." The source formed inside the pillar is exposed by the single side contact process, and the buried bit line is electrically connected to the exposed source.

A memory device using a vertical transistor is disclosed in Patent Document 1 below.

Korean Laid-Open Patent Publication No. 2011-0035687 In the patent document, polysilicon liners and boron tilt implants are used in a single-side contact process. However, in the single-side contact process disclosed in the patent literature, the undoped polysilicon of boron-doped doped polysilicon and boron-doped undoped polysilicon is not large (selection ratio <1: 5), so that the undoped poly Loss of doped polysilicon is severe during the silicon removal process, which reduces process margins. In particular, if the spacing between polysilicon liners decreases as the design rule decreases, the thickness of the polysilicon liner decreases due to excessive loss of the doped polysilicon. In addition, lateral etching is caused by excessive loss of doped polysilicon. Due to such a thickness reduction and side etching, it is difficult to open one side of the polysilicon liner and a dual open phenomenon occurs. When dual open occurs, a short between neighboring bit lines occurs.

An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent the dual opening phenomenon in the single-side contact process.

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of providing a substrate having a trench having a first side wall and a second side wall is coated with an insulating film; Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench; Forming a liner film adjacent the upper region of the trench on the sacrificial film; Forming an ion implantation region in the liner layer in the direction of the first side wall; And selectively removing the non-ion implantation region of the liner layer remaining on the second side wall.

In addition, the semiconductor device manufacturing method of the present invention includes the steps of providing a substrate having a trench having a first side wall and a second side wall is coated with an insulating film; Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench; Forming a silicon film on the sacrificial layer adjacent to the upper region of the trench; Implanting nitrogen ions into the silicon film in the direction of the first side wall; And selectively removing the non-ion implantation region of the silicon film remaining on the second side wall by using a hydroxyl chemical.

In addition, the semiconductor device manufacturing method of the present invention includes the steps of providing a substrate having a trench having a first side wall and a second side wall is coated with an insulating film; Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench; Forming a silicon film on the sacrificial layer, the silicon film having an ion implantation region adjacent to an upper portion of the first side wall and a nonion implantation region adjacent to an upper portion of the second side wall; And selectively removing the non-ion implantation region using a hydroxyl chemical.

In addition, the semiconductor device manufacturing method of the present invention includes the steps of providing a substrate having a trench having a first side wall and a second side wall is coated with an insulating film; Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench; Forming a liner layer on the sacrificial layer, the liner layer having an ion implantation region adjacent to an upper portion of the first side wall and a nonion implantation region adjacent to an upper portion of the second side wall; Selectively removing the non-ion implantation region using a hydroxyl chemical; And selectively removing the sacrificial film and the insulating film adjacent to the first side wall to form an open portion exposing a portion of the first side wall.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of: providing a substrate having a plurality of active bodies having a first side wall and a second side wall coated with an insulating film; Forming a sacrificial layer gap-filling the active bodies while exposing an upper region of the active bodies; Forming a silicon film on the sacrificial layer, the silicon film having an ion implantation region adjacent to an upper portion of the first side wall and a nonion implantation region adjacent to an upper portion of the second side wall; Selectively removing the non-ion implantation region using a hydroxyl chemical; Selectively removing the sacrificial layer and the insulating layer adjacent to the first side wall to form an open portion exposing a portion of the first side wall; And forming a bit line connected to the first side wall through the open part and partially filling the active body.

The present invention described above has a selectivity ratio between the ion implantation region and the nonion implantation region through nitrogen ion implantation, and the non-ion implantation region is removed without attack of the surrounding structure by selectively removing the nonion implantation region using subsequent hydroxyl chemicals. It can be removed.

1A and 1B illustrate a semiconductor device according to an embodiment of the present invention.
2A to 2J are cross-sectional views illustrating a method of forming an open part by a single side contact process according to an exemplary embodiment of the present invention.
3A to 3C are diagrams illustrating a method of manufacturing a semiconductor device using an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

1A and 1B illustrate a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1A, a plurality of bodies 24 separated by a plurality of trenches 23 are formed on the substrate 21. The substrate 21 includes a silicon substrate. Since the substrate 21 includes a silicon substrate, the body 24 becomes a silicon body. The body 24 extends in the vertical direction from the surface of the substrate 21. The body 24 is used as an active region. As is well known, the active region is the region where the channel, source and drain of the transistor are formed. Body 24 has sidewalls. It is a line type body having at least two transverse sidewalls. The body 24 is also referred to as an 'active body'.

The hard mask film 22 is formed on the body 24. An insulating film is coated on both sidewalls of the body 24, the surface of the trench 23 between the body 24, and the sidewalls of the hard mask film 22. The insulating film includes a first liner film pattern 25A and a second liner film pattern 27A. The first liner film pattern 25A includes an oxide film, and the second liner film pattern 27A includes a nitride film. The first liner film pattern 25A is formed on both sidewalls of the body 24 and the surface of the substrate 21. The second liner film pattern 27A is formed on a part of the surface of the first liner film pattern 25A. The opening 34 which exposes a part of the side wall of the body 24 is provided by the above-described insulating film.

As shown in FIG. 1B, a junction 35 is formed in the sidewall of the body 24 exposed by the open portion 34. The bit line 37A is formed with the height of filling the open part 34 in contact with the junction 35. Bit line 37A partially fills trench 23. The bit line 37A is formed of a low resistance material having a low resistance. For example, the bit line 37A includes a metal film or a metal nitride film.

The semiconductor device of FIGS. 1A and 1B forms an open portion 34 for electrical connection between the bit line 37A and the junction 35. The open portion 34 is formed by a single side contact process.

2A to 2J are cross-sectional views illustrating a method of forming an open part by a single side contact process according to an exemplary embodiment of the present invention.

As shown in FIG. 2A, a hard mask film 22 is formed on the semiconductor substrate 21. The semiconductor substrate 21 includes a silicon-containing substrate, for example, a silicon substrate and a silicon germanium substrate. The hard mask film 22 includes a nitride film. In addition, the hard mask film 22 may have a multilayer structure including an oxide film and a nitride film. For example, the hard mask layer 22 may be stacked in the order of the hard mask nitride layer (HM Nitride) and the hard mask oxide layer (HM Oxide). In addition, the hard mask layer 22 may be laminated in the order of a hard mask nitride film, a hard mask oxide film, a hard mask silicon oxynitride film (HM SiON), and a hard mask carbon film (HM Carbon). In the case of including the hard mask nitride layer, a pad oxide layer may be further formed between the substrate 21 and the hard mask layer 22. The hard mask film 22 is formed using a photosensitive film pattern (not shown).

Next, a trench etch process is performed using the hard mask layer 22 as an etch barrier. For example, the body 24 is formed by etching the substrate 21 to a predetermined depth by using the hard mask layer 22 as an etch barrier. The bodies 24 are separated from each other by trenches 23. Body 24 includes an active region where a transistor is formed. The body 24 is in the form of a line with two side walls. Trench etching processes include anisotropic etch. When the substrate 21 is a silicon substrate, the anisotropic etching may include plasma dry etching using Cl 2 or HBr gas alone, or using a mixture of these gases. The plurality of bodies 24 are separated by the trench 23 described above, and the bodies 24 extend in the vertical direction on the substrate 21.

The first liner film 25 is formed as an insulating film. The first liner film 25 includes an oxide film such as a silicon oxide film.

A first sacrificial layer 26 is formed on the first liner layer 25 to gap-fill the trenches 23 between the bodies 24. The first sacrificial layer 26 may include undoped polysilicon or amorphous silicon.

As shown in FIG. 2B, the first sacrificial layer 26 is planarized until the surface of the hard mask layer 22 is exposed. The planarization of the first sacrificial film 26 includes a chemical mechanical polishing (CMP) process. The etch-back process is performed continuously. After the etch back process, the first sacrificial layer pattern 26A providing the first recess R1 is formed. In the chemical mechanical polishing process, the first liner layer 25 on the hard mask layer 24 may be polished. As a result, a first liner film pattern 25A covering both sidewalls of the hard mask film 22 and the trench 23 is formed. The first liner film pattern 25A also covers the bottom of the trench 23.

Subsequently, the first liner layer pattern 25A is slimmed by using wet etching. At this time, by adjusting the wet etching time, the first liner film pattern 25A remains on the sidewall of the body 22 with a predetermined thickness.

As shown in FIG. 2C, the second liner film 27 is formed as an insulating film on the entire surface including the first sacrificial film pattern 26A. The second liner film 27 includes a nitride film such as a silicon nitride film. The second liner film 27 is formed to have the same thickness as the slimmed thickness of the first liner film pattern 25A.

As shown in FIG. 2D, the second liner layer 27 is selectively etched. As a result, the second liner film pattern 27A is formed in the slimming area of the first liner film pattern 25A. An etch back process may be applied to form the second liner film pattern 27A, whereby the second liner film pattern 27A becomes a spacer.

Subsequently, the first sacrificial film pattern 26A is recessed to a predetermined depth using the second liner film pattern 27A as an etch barrier. As a result, a second recess R2 exposing a part of the surface of the first liner film pattern 25A is formed. The first sacrificial layer pattern 26A forming the second recess R2 is referred to as '26B'. When the first sacrificial film pattern 26B includes polysilicon, the first sacrificial film pattern 26B is recessed using an etch back process.

As shown in FIG. 2E, a metal nitride film is conformally formed on the entire surface including the second recess R2. Thereafter, the spacer etching is performed to form the sacrificial spacer 28. The sacrificial spacers 28 are formed on both sidewalls of the body 22. The sacrificial spacer 28 includes a titanium nitride film TiN.

Subsequently, the second recess R2 on which the sacrificial spacer 28 is formed is gap-filled to form a second sacrificial layer pattern 29 having a recessed surface. The second sacrificial film pattern 29 includes an oxide film. The second sacrificial layer pattern 29 includes a spin on dielectric (SOD). In order to form the second sacrificial layer pattern 29, an oxide layer is formed on the entire surface to gap-fill the second recess. Thereafter, the planarized second sacrificial layer pattern 29 is formed as the etch back is performed after the planarization. Both side walls of the hard mask layer 22 protrude from the recessed second sacrificial layer pattern 29. The laminated structure of the body 24 and the hard mask film 22 is called a body structure. Accordingly, the body structure is separated by the plurality of trenches 23, and the first liner layer pattern 25A, the first sacrificial layer pattern 26B, the second liner layer pattern 27A, the sacrificial spacer 28 and the first liner layer 25A are formed. 2 is insulated by the sacrificial film pattern 29.

As shown in FIG. 2F, the third liner layer 30 is formed on the entire surface including the second sacrificial layer pattern 29. The third liner layer 30 includes polysilicon. Therefore, the third liner film 30 is referred to as a polysilicon liner. The third liner film 30 is formed of undoped polysilicon.

As shown in FIG. 2G, the tilt ion implantation 31 is performed.

Tilt ion implantation 31 implants a dopant (Dopnat) by giving a tilt at a predetermined angle. Dopants are injected into a portion of the third liner layer 30.

The tilt ion implantation 31 is performed at a predetermined angle. The predetermined angle includes about 5-30 degrees. The ion beam is partially shadowed by the hard mask film 24. Thus, a part of the third liner film 30 is doped but the rest remains undoped.

Preferably, the tilt ion implantation 31 process uses a nitrogen containing source. When the tilt ion implantation 31 is applied using a nitrogen-containing source, nitrogen-doped polysilicon remains as it is in a subsequent process such as high temperature annealing and oxidation, and polysilicon not doped with nitrogen is converted into an oxide film. To form an asymmetric structure. Therefore, the etching selectivity of the doped polysilicon and the undoped polysilicon is greatly increased by the nitrogen ion implantation, so that the loss of the remaining polysilicon in the sidewall contact process does not occur.

Preferably, the tilt ion implantation 31 using the nitrogen-containing source uses an N 2 source, and the tilt ion implantation 31 is performed using nitrogen ions generated at this time. The portion of the third liner film formed on the upper surface of the hard mask film 22 and the part adjacent to the right side of the hard mask film 22 by the tilt ion implantation 31 using the nitrogen-containing source are doped with nitrogen. The ion implantation region 30A is obtained. The portion where the dopant is not injected becomes the nonion implantation region 30B. In particular, when the tilt ion implantation 31 is performed, ion implantation energy is reduced to minimize Rp (Projection of Range), and when the ion implantation amount (Dose) is sufficiently increased, a high concentration of nitrogen is doped on the surface of the third liner layer. As a result, the ion implantation region 30A is formed on one sidewall (eg, the first sidewall) of the trench 23 and the top of the hard mask film 22. The nonion implantation region 30B is formed on the other sidewall of the trench 23 (eg, the second sidewall).

Subsequently, an annealing process can be performed. The temperature of the annealing step is carried out at a high temperature of 600 ~ 1000 ℃. The ion implantation region 30A is recrystallized by the high temperature annealing process 32.

As shown in FIG. 2H, the nonion implantation region 30B is selectively removed. Here, wet etching is used to remove the nonion implantation region 30B. For example, the non-ion implantation region 30B is removed using the hydroxyl chemical 32. By using the hydroxyl chemical 32, selective etching is possible between the ion implantation region 30A and the nonion implantation region 30B.

Therefore, only the non-ion implantation region 30B can be selectively removed without removing the ion implantation region 30A.

When the non-ion implantation region 30B is removed as above, only the ion implantation region 30A remains. That is, only the ion implantation region 30A remains in the third liner layer, and the ion implantation region 30A of the third liner layer has a single-side structure 33 that opens an upper sidewall of one side of the body 24.

As shown in FIG. 2I, any one of the sacrificial spacers 28 is removed using the ion implantation region 30A as a barrier. As a result, a gap (not shown) is formed between the second sacrificial film pattern 29 and the second liner film pattern 27A. The sacrificial spacers 28 are removed using wet etching. Accordingly, one sacrificial spacer 28 remains.

Next, a cleaning process is performed to expose a portion of the sidewall.

The cleaning process includes wet cleaning. Wet cleaning uses hydrofluoric acid (HF) and BOE (Buffered Oxide Etchant). By using wet cleaning, the first liner film pattern 25A can be selectively removed without damaging the first sacrificial film pattern 6B, the sacrificial spacer 28 and the second liner film pattern 27A. At this time, the second sacrificial film pattern 29 formed of the oxide film is also removed at the same time.

The open part 34 exposing a part of one side wall of the body 24 is formed by the cleaning process as described above.

As shown in FIG. 2J, the ion implantation region 30A is removed. At this time, since the ion implantation region 30A and the first sacrificial film pattern 26B are the same polysilicon, they can be removed at the same time.

Next, the sacrificial spacers 28 are removed.

The open part 34 exposing a portion of one sidewall of the trench 23 coated with the insulating film including the first liner film pattern 25A and the second liner film pattern 27A is formed by the above-described process. Is formed. The open part 34 also has a structure that exposes a part of one side wall of the body 24 separated by the trench 23.

3A to 3C are diagrams illustrating a method of manufacturing a semiconductor device using an embodiment of the present invention.

As shown in FIG. 3A, a junction 35 is formed in a portion of the sidewall of the body 24 on which the open portion 34 is formed. Tilt implantation or plasma doping may be used as a method of forming the junction 35. It is assumed here that the plasma doping method 36 is applied. The doped impurities in the junction 35 have a doping concentration of 1 × 10 20 atoms / cm 3 or more. The junction 35 is doped with phosphorus (Ph) or arsenic (As). As a result, the junction 35 becomes an N type junction. When the plasma doping method 36 is applied, the depth (side diffusion depth) of the junction 35 can be controlled to be shallow, and the concentration of the dopant can be easily adjusted. Junction 35 becomes the source or drain of the vertical channel transistor.

As shown in FIG. 3B, the conductive film 37 is formed along the entire structure in which the junction 35 is formed. The conductive film 37 gap-fills between the bodies 24. The conductive film 37 is a material used as a buried bit line, and is formed of a low resistance material having a low resistance. For example, the conductive film 37 includes a metal film or a metal nitride film. The conductive film 37 includes a titanium nitride film TiN.

As shown in FIG. 3C, the planarization and etch back processes are sequentially performed on the conductive film 37. As a result, the conductive film pattern 37A remains only in the trench 23. The planarization proceeds until the surface of the hard mask film 22 is exposed, for example, by applying chemical mechanical polishing (CMP). The conductive film pattern 37A becomes a buried bit line by the etch back process. Hereinafter, reference numeral '37A' is referred to as a buried bit line. By forming the buried bit line 37A using a metal film or a metal nitride film, the resistance of the buried bit line can be lowered.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.

21: semiconductor substrate 22: hard mask film
23: trench 24: body
25: first liner film pattern 27: second liner film pattern
30: third liner film 30A: ion implantation region
30B: non-ion implantation area 34: open part

Claims (5)

Providing a substrate with a trench having a first side wall and a second side wall coated with an insulating film;
Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench;
Forming a liner film adjacent the upper region of the trench on the sacrificial film;
Forming an ion implantation region in the liner layer in the direction of the first side wall; And
Selectively removing the non-ion implantation region of the liner layer remaining on the second side wall
&Lt; / RTI &gt;
Providing a substrate with a trench having a first side wall and a second side wall coated with an insulating film;
Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench;
Forming a silicon film on the sacrificial layer adjacent to the upper region of the trench;
Implanting nitrogen ions into the silicon film in the direction of the first side wall; And
Selectively removing the non-ion implantation region of the silicon film remaining on the second side wall using a hydroxyl chemical
&Lt; / RTI &gt;
Providing a substrate with a trench having a first side wall and a second side wall coated with an insulating film;
Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench;
Forming a silicon film on the sacrificial layer, the silicon film having an ion implantation region adjacent to an upper portion of the first side wall and a nonion implantation region adjacent to an upper portion of the second side wall; And
Selectively removing the non-ion implantation region using a hydroxyl chemical
&Lt; / RTI &gt;
Providing a substrate with a trench having a first side wall and a second side wall coated with an insulating film;
Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench;
Forming a liner layer on the sacrificial layer, the liner layer having an ion implantation region adjacent to an upper portion of the first side wall and a nonion implantation region adjacent to an upper portion of the second side wall;
Selectively removing the non-ion implantation region using a hydroxyl chemical; And
Selectively removing the sacrificial layer and the insulating layer adjacent to the first side wall to form an open portion exposing a portion of the first side wall;
&Lt; / RTI &gt;
Providing a substrate having a plurality of active bodies having a first sidewall and a second sidewall coated with an insulating film;
Forming a sacrificial layer gap-filling the active bodies while exposing an upper region of the active bodies;
Forming a silicon film on the sacrificial layer, the silicon film having an ion implantation region adjacent to an upper portion of the first side wall and a nonion implantation region adjacent to an upper portion of the second side wall;
Selectively removing the non-ion implantation region using a hydroxyl chemical;
Selectively removing the sacrificial layer and the insulating layer adjacent to the first side wall to form an open portion exposing a portion of the first side wall; And
Forming a bit line connected to the first side wall through the open part and partially filling the active body
&Lt; / RTI &gt;
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US9269746B2 (en) 2013-11-12 2016-02-23 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same
US11107829B2 (en) 2018-12-17 2021-08-31 SK Hynix Inc. Method of manufacturing a three-dimensional non-volatile memory device
US11127862B2 (en) 2018-11-05 2021-09-21 SK Hynix Inc. Three-dimensional non-volatile memory device and method of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269746B2 (en) 2013-11-12 2016-02-23 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same
US9431458B2 (en) 2013-11-12 2016-08-30 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same
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