KR101087782B1 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and discloses a technique of improving the characteristics of devices by forming different thicknesses of upper and lower oxide layers when forming oxide films on sidewalls of pillar patterns when forming buried bitlines.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a method for manufacturing a semiconductor device having a vertical channel transistor.

As the degree of integration of semiconductor devices increases, the channel length of the transistors gradually decreases. However, the reduction in the channel length of such transistors has a problem of causing short channel effects such as a drain induced barrier lowering (DIBL) phenomenon, a hot carrier effect, and a punch through. To solve this problem, various methods have been proposed, such as a method of reducing the depth of the junction region or a method of increasing the channel length relatively by forming a recess in the channel region of the transistor.

However, as the integrated density of semiconductor memory devices, especially DRAM, approaches giga bits, smaller transistor sizes are required. That is, a transistor of a gigabit DRAM device requires an element area of 8F2 (F: minimum feature size) or less, and further requires an element area of about 4F2. Therefore, the current planar transistor structure in which the gate electrode is formed on the semiconductor substrate and the junction regions are formed on both sides of the gate electrode is difficult to satisfy the required device area even when the channel length is scaled.

In order to solve this problem, a vertical channel transistor structure has been proposed.

Although not shown, a brief description of a method of manufacturing a vertical channel transistor is as follows.

First, a top pillar is formed by etching a cell region of a semiconductor substrate to a predetermined depth through a photo process, and then forming spacers surrounding sidewalls of the top pillar. Next, the semiconductor substrate is further etched using the spacers as an etch mask to form a trench, and then an isotropic wet etching process is performed on the trench to integrally form the lower pillar and extend in a vertical direction. To form a neck pillar. At this time, the lower pillar is formed to have a narrower width than the upper pillar.

Next, a rounding gate including a gate insulating film and a gate conductive film is formed on the outer sidewall of the lower pillar, and ion implantation is performed on the semiconductor substrate adjacent to the rounding gate to form a bit line impurity region. Subsequently, the semiconductor substrate is etched to a depth where the impurity regions are separated to form buried bit lines in which the impurity regions are separated. In this case, in order to prevent a short circuit between the buried bit lines, the semiconductor substrate needs to be etched very deeply.

Subsequently, subsequent known processes are sequentially performed to complete a semiconductor device having a vertical transistor according to the prior art.

However, when the buried bit line is formed, a problem occurs in that a resistance value between the bit line and the substrate increases. Accordingly, a method of increasing the thickness of the sidewall oxide film has been proposed to reduce the resistance between the bit line and the substrate. However, as the thickness of the sidewall oxide film is increased, the space margin is reduced, which causes difficulties in subsequent embedding or etching processes. In addition, there is a problem that the separation between the bit line and the bit line is weak, in order to overcome this, a method of deepening the buried bit line depth has been proposed. However, if the depth of the buried bit line is deeply formed, there is a problem in that it is difficult to apply because it burdens subsequent processes.

The present invention is to improve the characteristics of the device by forming different thickness of the sidewall oxide film on the upper and lower pillar pattern.

A method of manufacturing a semiconductor device according to the present invention includes etching a semiconductor substrate to form a plurality of pillar patterns and trenches defining a buried bit line region, forming a first oxide film in the trench, and forming a trench bottom portion. Exposing the semiconductor substrate by removing the first oxide film, forming a second oxide film thicker than the first oxide film on the exposed semiconductor substrate, and partially removing the first oxide film on one side of the pillar pattern. Removing and forming a contact hole.

Here, the pillar pattern is formed to a height of 2500 ~ 2700Å, the first oxide film is formed to a thickness of 70 ~ 80ÅÅ.

A TiN film is further formed on the surface of the first oxide film, and the TiN film is formed by a CVD method using TiCl 4 as a source gas. The second oxide film is formed to a thickness of 250 ~ 270Å, and the second oxide film is subjected to a nitriding process to deform the surface of the second oxide film to a first nitride film.

The forming of the contact hole may include filling a polysilicon layer in the bottom of the trench, wherein the polysilicon layer is formed to partially overlap with the first oxide layer, and is exposed to the upper portion of the polysilicon layer. A second nitride film is formed on the oxide sidewall. Next, the method may further include removing the polysilicon layer and removing the second oxide layer between the first nitride layer and the second nitride layer.

Further, a field stop ion implantation region is formed in the semiconductor substrate at the bottom of the trench, wherein the ion implantation region is formed by performing an ion implantation process using any one selected from BF2, B, and a combination thereof.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail. First, forming a plurality of pillar patterns and trenches by etching the semiconductor substrate, forming a laminated film of a first oxide film and a conductive film in the trench, and removing the laminated film at the bottom of the trench to expose the semiconductor substrate. Forming a second oxide film thicker than the first oxide film on the exposed semiconductor substrate surface, nitriding the surface of the second oxide film to form a first nitride film, and conducting the conductive pattern on one side of the pillar pattern Removing the film to expose the first oxide film, embedding a polysilicon layer in the bottom of the trench, wherein the polysilicon layer is formed at a height partially overlapping with the first oxide film, and exposed above the polysilicon layer Forming a second nitride film on the surface of the first oxide film, and removing the polysilicon layer Exposing the first oxide film overlapping the polysilicon layer on one side of the pattern, and removing the first oxide film exposed between the first nitride film and the second nitride film to form a contact hole. It features.

In addition, the semiconductor device according to the present invention may include a plurality of pillar patterns and trenches defining a buried bit line region, a first oxide film formed on sidewalls of the pillar pattern, a lower portion of the trench, and a thickness greater than that of the first oxide film. And a contact hole formed by exposing the pillar pattern between the formed second oxide film and the first oxide film and the second oxide film.

Here, the first oxide film is formed to a thickness of 70 ~ 80Å, the second oxide film is formed to a thickness of 250 ~ 270Å. The nitride oxide film may further include a nitride film on the first oxide film and the second oxide film.

The present invention has the following effects.

First, by forming a thin sidewall oxide film thickness on the pillar pattern, it is possible to secure a process margin.

Second, the thickness of the sidewall oxide film under the pillar pattern is formed thicker than the thickness of the sidewall oxide film on the upper side, thereby improving the sensing margin by reducing the bit line resistance.

Third, by forming different thicknesses of the sidewall oxide layers on the upper and lower pillar patterns, the upper part secures a process margin and the lower part improves a sensing margin, thereby improving the refresh characteristics of the device.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

1A to 1I are perspective views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 1A, a hard mask pattern 110 for forming a vertical channel transistor is formed on the semiconductor substrate 100. Here, the hard mask pattern 110 is to form a buried bit line, it is preferable to form a line type (Line Type).

Next, the semiconductor substrate 100 is etched using the hard mask pattern 110 as a barrier to form a plurality of pillar patterns 100a. At this time, the pillar pattern 100a is formed by etching the depth of 2500-2700 으로부터 from the upper side of the semiconductor substrate 100. In this case, the portions etched between the pillar patterns 100a are defined as trenches 113.

Next, a first oxidation process is performed to form a first oxide film 115 in the trench 113. Here, the first oxide film 115 is formed by oxidizing the silicon layer of the semiconductor substrate 100, and is formed to a thickness of 70 ~ 80Å.

Next, the conductive film 120 is deposited on the entire surface including the first oxide film 115. Here, the conductive film 120 is formed of a TiN film having a thickness of 50 to 60 Å. At this time. The TiN film is formed by a CVD method using TiCl 4 as a source gas.

Referring to FIG. 1B, the conductive layer 120 at the bottom of the trench 113 is removed to expose the first oxide layer 115. Thereafter, a cleaning process using a BOE solution is performed to remove the exposed first oxide film 115. As a result, the semiconductor substrate 100 at the bottom of the trench 113 is exposed.

Referring to FIG. 1C, a second oxide film 130 is formed on the exposed surface of the semiconductor substrate 100 at the bottom of the trench 113 by performing a secondary oxidation process. Here, the second oxide film 130 is preferably formed thicker than the first oxide film 115. For example, the second oxide film 130 is formed to a thickness of 250 ~ 270Å. As such, the reason why the oxide film is thickly formed only on the bottom of the trench 113 is that when the oxide film formed on both the top and the bottom of the pillar pattern is formed thick, the subsequent filling or etching process cannot be easily performed.

Referring to FIG. 1D, a nitride process using an NH 3 source gas is performed to deform the surface of the second oxide film 130 to the first nitride film 135. At this time, the thickness of the first nitride film 135 to be deformed is preferably 50 ~ 60 50.

Next, an ion implantation process is performed to form a field stop ion implantation region (not shown) under the trench 113. In this case, the ion implantation process is performed using any one selected from BF2, B, and combinations thereof, and the field stop ion implantation region (not shown) is formed to prevent leakage current between bit lines.

Referring to FIG. 1E, the first polysilicon layer 140 is formed on the entire surface including the pillar pattern 100a and the trench 113, and then planarized etching is performed until the hard mask pattern 110 is exposed. Next, a mask pattern (not shown) in which one side of the pillar pattern 100a is opened is formed on the first polysilicon layer 140 and the hard mask pattern 110.

Next, the first polysilicon layer 140 is etched using the mask pattern (not shown) as a barrier to expose the conductive layer 120 on one side of the pillar pattern 100a. In this case, a portion of the first nitride layer 135 of the bottom of the trench 113 may be exposed. In addition, the exposed conductive layer 120 is removed to expose the hard mask pattern 110 and the first oxide layer 115, and then the mask pattern (not shown) is removed. Here, the conductive film 120 is preferably removed by going through a cleaning process.

Referring to FIG. 1F, after removing the first polysilicon layer 140, the second polysilicon layer 145 is formed on the entire upper portion including the pillar pattern 100a and the trench 113. Next, the second polysilicon layer 145 is planarized until the hard mask pattern 110 is exposed. Next, the second polysilicon layer 145 is further etched so that the second polysilicon layer 145 remains only at the bottom of the trench 113. In this case, the second polysilicon layer 145 is formed to have a height partially overlapping with the first oxide film 115. That is, the second oxide layer 130 is formed to be higher than the upper side of the second oxide layer 130.

Next, the second nitride film 150 is deposited on the entire surface including the trench 113 in which the second polysilicon layer 145 is embedded. At this time, the second nitride film 150 is deposited using a furnace (Funace) equipment, so that the thickness is 50 ~ 60Å.

Next, the etch-back process is performed to leave the second nitride layer 150 only on the sidewalls of the pillar pattern 110a and the hard mask pattern 110.

Referring to FIG. 1G, the second polysilicon layer 145 is removed. At this time, only the first oxide film 115 is formed in a region between the first nitride film 135 formed on the bottom of the trench 113 and the second nitride film 150 formed above the second polysilicon layer 145. Accordingly, when the second polysilicon layer 145 is removed, the first oxide film 115 is exposed in a portion of one side of the pillar pattern 110a.

Next, the exposed first oxide film 115 is removed to form a contact hole 155 exposing one side of the pillar pattern 110a. In this case, the contact hole 155 is used as a buried bit line contact hole.

As described above, by forming different thicknesses of the oxide layer on the upper and lower portions of the trench in which the buried bitline is to be formed, process margins may be secured and the sensing margin of the bitline may be improved.

In addition, the semiconductor device according to the present invention will be described with reference to FIG. 1G as follows.

First, a pillar pattern 100a defining a buried bit line is provided, and the oxide films 115 and 130 and the nitride films 135 and 150 exposing a part of one side of the pillar pattern 100a on the surface of the pillar pattern 100a are provided. The laminated structure is formed. Here, the exposed portion is defined as a contact hole 155.

In this case, the thicknesses of the oxide film 115 formed above the contact hole 155 and the oxide film 130 formed below the contact hole are different from each other. In detail, the oxide film 130 formed below the contact hole 155 is formed thicker than the oxide film 115 formed above the contact hole 155.

As described above, by forming different thicknesses of the oxide layer on the upper and lower portions of the trench in which the buried bitline is to be formed, process margins may be secured and the sensing margin of the bitline may be improved.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

100 semiconductor substrate 100a pillar pattern

110: hard mask pattern 113: trench

115: first oxide film 120: conductive film

130: second oxide film 135: first nitride film

140: first polysilicon layer 145: second polysilicon layer

150: second nitride film 155: contact hole

Claims (15)

Etching the semiconductor substrate to form a plurality of pillar patterns and trenches defining a buried bit line region; Forming a first oxide film in the trench; Removing the first oxide film at the bottom of the trench to expose the semiconductor substrate; Forming a second oxide film thicker than the first oxide film on the exposed semiconductor substrate; And Removing a portion of the first oxide layer on one side of the pillar pattern to form a contact hole Method of manufacturing a semiconductor device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The pillar pattern is a manufacturing method of a semiconductor device, characterized in that formed in a height of 2500 ~ 2700Å. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, The first oxide film is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 70 ~ 80Å. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, A TiN film is further formed on the surface of the first oxide film. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein And the TiN film is formed by a CVD method using TiCl 4 as a source gas. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, The second oxide film is a semiconductor device manufacturing method, characterized in that formed in a thickness of 250 ~ 270. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, And a first nitride film is formed on the surface of the second oxide film to form a first nitride film. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein Forming the contact hole Embedding a polysilicon layer in the bottom of the trench, wherein the polysilicon layer is formed to a height overlapping a portion of the first oxide layer; Forming a second nitride film on sidewalls of the first oxide film exposed to the polysilicon layer; And Removing the polysilicon layer and removing the second oxide film between the first nitride film and the second nitride film Method of manufacturing a semiconductor device further comprising. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, And forming a field stop ion implantation region in the semiconductor substrate at the bottom of the trench. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 9, The ion implantation region is formed by performing an ion implantation process using any one selected from BF2, B and combinations thereof. Etching the semiconductor substrate to form a plurality of pillar patterns and trenches; Forming a laminated film of a first oxide film and a conductive film in the trench; Removing the laminated film of the trench bottom to expose the semiconductor substrate; Forming a second oxide film thicker than the first oxide film on the exposed semiconductor substrate surface; Nitriding the surface of the second oxide film to form a first nitride film; Exposing the first oxide layer by removing the conductive layer on one side of the pillar pattern; Embedding a polysilicon layer in the bottom of the trench, wherein the polysilicon layer is formed to a height overlapping a portion of the first oxide layer; Forming a second nitride film on a surface of the first oxide film exposed above the polysilicon layer; Removing the polysilicon layer to expose the first oxide layer overlapping the polysilicon layer on one side of the pillar pattern; And Forming a contact hole by removing the first oxide film exposed between the first nitride film and the second nitride film Method of manufacturing a semiconductor device comprising a. A plurality of pillar patterns and trenches defining buried bitline regions; A first oxide film formed on sidewalls of the pillar pattern; A second oxide film formed on the bottom of the trench and formed to a thickness thicker than the first oxide film; A contact hole formed by exposing the pillar pattern between the first oxide film and the second oxide film; And And a nitride film formed on the surfaces of the first oxide film and the second oxide film. Claim 13 was abandoned upon payment of a registration fee. 13. The method of claim 12, The first oxide film is a semiconductor device, characterized in that formed in a thickness of 70 ~ 80Å. Claim 14 was abandoned when the registration fee was paid. 13. The method of claim 12, The second oxide film is a semiconductor device, characterized in that formed in a thickness of 250 ~ 270Å. delete

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