KR20080084572A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
KR20080084572A
KR20080084572A KR1020080009042A KR20080009042A KR20080084572A KR 20080084572 A KR20080084572 A KR 20080084572A KR 1020080009042 A KR1020080009042 A KR 1020080009042A KR 20080009042 A KR20080009042 A KR 20080009042A KR 20080084572 A KR20080084572 A KR 20080084572A
Authority
KR
South Korea
Prior art keywords
opening
semiconductor substrate
pad electrode
insulating layer
diameter
Prior art date
Application number
KR1020080009042A
Other languages
Korean (ko)
Other versions
KR101463895B1 (en
Inventor
요시히로 나베
히로시 아사미
유지 다카오카
요시미치 하라다
Original Assignee
소니 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 소니 가부시끼 가이샤 filed Critical 소니 가부시끼 가이샤
Publication of KR20080084572A publication Critical patent/KR20080084572A/en
Application granted granted Critical
Publication of KR101463895B1 publication Critical patent/KR101463895B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A semiconductor device and a method of manufacturing the same are provided to shorten TAT(Turn Around Time) of the formation of a through-hole by forming a first large opening except for a portion which contacts a pad electrode. A semiconductor device comprises a semiconductor substrate(10), a pad electrode(12), a first opening(H1), a second opening(H2), an insulating layer(20), and a conductive layer(21). The semiconductor substrate has first and second surfaces opposite each other. The first surface is an active surface provided with an electronic element. The pad electrode is formed to be connected to the electronic element in a peripheral portion of the electronic element on the active surface. The first opening extends from the second surface of the semiconductor substrate toward the pad electrode so as not to reach the first surface of the semiconductor substrate. The second opening, which is formed to reach the pad electrode from a bottom surface of the first opening, has a diameter smaller than that of the first opening. The insulating layer is formed to cover sidewall surfaces of the first opening and the second opening. The conductive layer is formed inside of the insulating layer to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.

Description

반도체장치 및 그 제조방법{Semiconductor device and method of manufacturing the same}Semiconductor device and method of manufacturing the same

본 발명은 반도체장치 및 그 제조방법에 관한 것이다. 보다 상세하게는, 본 발명은 고체 촬상 장치 등이 공기가 통하지 않게 밀봉된 패키지 형태의 반도체장치와 같은 기판을 관통하는 배선을 가지는 반도체장치에 관한 것이다. 또한 본 발명은 그 제조방법에 관한 것이다.The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device having a wiring through a substrate such as a semiconductor device in a package form in which a solid-state imaging device or the like is sealed without passing through air. The present invention also relates to a method for producing the same.

고체 촬상 센서의 소형화의 일례로서, 촬상 센서 영역을 밀봉된 상태로 유지하는 방법이 일본 미심사 특허출원공보 번호 2006-128713(이후로는 "특허문헌 1"로 칭함) 등에 개시되어 있다. 그 방법은 촬상 센서 영역의 주변부 외측에 접착층을 형성하고, 밀봉을 위한 접착층에 의해 투명판을 접착시키도록 고체 촬상 센서의 상부에 유리와 같은 투명판을 배치하는 것을 포함한다.As an example of miniaturization of a solid-state imaging sensor, a method of maintaining the imaging sensor region in a sealed state is disclosed in Japanese Unexamined Patent Application Publication No. 2006-128713 (hereinafter referred to as "Patent Document 1"). The method includes forming an adhesive layer outside the periphery of the imaging sensor region and disposing a transparent plate such as glass on top of the solid-state imaging sensor to adhere the transparent plate by the adhesive layer for sealing.

이와 같은 구성의 고체 촬상 센서의 외부 전극을 전기적으로 접속하기 위한 방법은 다음과 같다. 고체 촬상 센서의 액티브 표면과는 반대쪽의 표면으로부터 액티브 표면에 배치된 알루미늄 등으로 된 패드 전극에 이르는 하나의 스루홀(through hole)을 형성하기 위해 드라이 에칭법(dry etching method) 등이 이용 되고 있으며, 그 스루홀의 내벽은 고체 촬상 센서를 구성하는 실리콘 기판으로부터 절연을 확실하게 하기 위한 절연층과, 스루홀 내에 채워진 또는 스루홀의 측벽을 피복하도록 피복된 패드전극과 전기적으로 접속하기 위한 구리 등으로 된 도전층으로 형성된다.The method for electrically connecting the external electrode of the solid-state imaging sensor of such a structure is as follows. A dry etching method is used to form a through hole from the surface opposite to the active surface of the solid-state imaging sensor to a pad electrode made of aluminum or the like disposed on the active surface. The inner wall of the through hole is made of an insulating layer for assuring insulation from the silicon substrate constituting the solid-state imaging sensor, and copper for electrically connecting with a pad electrode filled in the through hole or coated to cover the sidewall of the through hole. It is formed of a conductive layer.

외부 전극이 액티브 표면의 후면으로부터 전기적으로 접속될 때, 고체 촬상 센서와 같은 사이즈로 고체 촬상 장치의 패키지화를 실현할 수 있어, 그것에 의해 고체 촬상 장치의 소형화가 가능할 수 있게 된다.When the external electrodes are electrically connected from the rear surface of the active surface, the solid-state imaging device can be packaged in the same size as the solid-state imaging sensor, thereby making it possible to downsize the solid-state imaging device.

그렇지만, 상기 특허문헌 1의 반도체장치에 있어서, 스루홀 내에 채워진 또는 스루홀의 측벽을 피복하도록 피복된 실리콘 기판과 도전층은 열팽창계수에서 차이가 있다. 따라서 땜납의 되흐름(reflow) 등 도전층의 형성 후에 적용된 수지의 고체화와 같은 열처리로 인하여 스루홀의 패드 전극에 이르는 바닥과 측벽의 코너 근방으로부터 실리콘 기판 상에서 크랙(crack)이 발생하는 문제가 일어난다.However, in the semiconductor device of Patent Document 1, the silicon substrate filled in the through hole or coated to cover the sidewall of the through hole and the conductive layer differ in coefficient of thermal expansion. Therefore, a problem occurs that cracks occur on the silicon substrate from near the corners of the bottom and sidewalls to the pad electrodes of the through holes due to heat treatment such as solidification of the resin applied after the formation of the conductive layer such as solder reflow.

또, 도전층의 열처리에 의한 열팽창으로 인하여, 패드 전극의 알루미늄 등이 밀려 올려지며, 그것에 의해 도전층과 패드 전극 사이의 인터페이스상에서 필링(peeling)이나 또는 패드 전극과 접착제층의 필링을 일으킨다는 또 다른 문제가 있다.In addition, due to thermal expansion by heat treatment of the conductive layer, aluminum of the pad electrode is pushed up, thereby causing peeling on the interface between the conductive layer and the pad electrode or peeling of the pad electrode and the adhesive layer. There is another problem.

해결되어야 할 과제는, 스루홀 내에 채워진 도전층과, 기판이나 패드 전극 사이에서 열팽창계수에 있어서의 차이로 인하여 일으키게 되는 크랙이나 필링을 억 제하는 것이 곤란한 것이다.The problem to be solved is that it is difficult to suppress cracking or peeling caused by a difference in thermal expansion coefficient between the conductive layer filled in the through hole and the substrate or the pad electrode.

본 발명의 한 관점에 따라, 서로 반대편의 제 1 및 제 2 표면을 가지는 반도체 기판과, 전자소자가 제공됨으로써 액티브 표면이 되는 제 1 표면, 즉, 전자소자로 형성된 액티브 표면과, 액티브 표면상의 전자소자의 주변부에서 상기 전자소자에 접속되도록 형성된 패드 전극과, 반도체 기판의 제 1 표면에 도달하지 않도록 반도체 기판의 제 2 표면으로부터 패드 전극을 향하여 연장하는 제 1 개구부와, 제 1 개구부의 직경보다 작은 직경을 가지는, 제 1 개구부의 바닥 표면으로부터 패드 전극에 도달하도록 형성된 제 2 개구부와, 제 1 개구부 및 제 2 개구부의 측벽 표면을 피복하도록 형성된 절연층과, 절연층의 내부, 적어도 절연층의 내벽 표면과 제 2 개구부의 바닥 표면을 피복하도록 형성된 도전층을 포함하는 반도체장치가 제공되어 있다.According to one aspect of the invention, a semiconductor substrate having first and second surfaces opposite to each other, a first surface which becomes an active surface by providing an electronic element, that is, an active surface formed of an electronic element, and an electron on the active surface A pad electrode formed to be connected to the electronic device at the periphery of the device, a first opening extending from the second surface of the semiconductor substrate toward the pad electrode so as not to reach the first surface of the semiconductor substrate, and smaller than the diameter of the first opening; A second opening having a diameter, the second opening being formed to reach the pad electrode from the bottom surface of the first opening, an insulating layer formed to cover the sidewall surfaces of the first opening and the second opening, an inner wall of the insulating layer, and at least an inner wall of the insulating layer. There is provided a semiconductor device comprising a conductive layer formed to cover a surface and a bottom surface of a second opening.

상기의 본 발명의 반도체장치에 있어서, 전자소자가 반도체 기판의 액티브 표면인 제 1 표면에 형성되고, 패드 전극이 액티브 표면상에서 전자소자의 주변부에서 전자소자에 접속되도록 형성되어 있다. 여기서, 제 1 개구부는 반도체 기판의 제 1 표면에 도달하지 않도록 반도체 기판의 제 2 표면으로부터 패드 전극을 향하여 연장되며, 제 1 개구부의 직경보다 작은 직경을 가지는 제 2 개구부는 제 1 개구부의 바닥 표면으로부터 패드 전극에 도달하도록 형성된다. 절연층은 제 1 개구부 및 제 2 개구부의 측벽 표면을 피복하도록 형성된다. 도전층은 절연층의 내부, 적어도 절연층의 내벽 표면과 제 2 개구부의 바닥 표면을 피복하도록 형성된 다.In the semiconductor device of the present invention described above, an electronic element is formed on a first surface which is an active surface of a semiconductor substrate, and a pad electrode is formed so as to be connected to the electronic element at the periphery of the electronic element on the active surface. Here, the first opening extends from the second surface of the semiconductor substrate toward the pad electrode so as not to reach the first surface of the semiconductor substrate, and the second opening having a diameter smaller than the diameter of the first opening is the bottom surface of the first opening. It is formed to reach the pad electrode from. The insulating layer is formed to cover the sidewall surfaces of the first opening and the second opening. The conductive layer is formed to cover the inside of the insulating layer, at least the inner wall surface of the insulating layer and the bottom surface of the second opening.

본 발명의 또 다른 관점에 따라, 서로 반대편의 제 1 및 제 2 표면을 가지는 반도체 기판을 제공하는 스텝과, 반도체 기판의 액티브 표면인 제 1 표면상에서 전자소자를 형성하고 액티브 표면상에서 전자소자의 주변부에서 전자소자에 접속되도록 패드 전극을 형성하는 스텝과, 반도체 기판의 제 1 표면에 도달하지 않도록 반도체 기판의 제 2 표면으로부터 패드 전극을 향하여 연장하는 제 1 개구부를 형성하는 스텝과, 제 1 개구부의 바닥 표면으로부터 패드 전극에 도달하도록 제 1 개구부의 직경보다 작은 직경을 가지는 제 2 개구부를 형성하는 스텝과, 절연층을 형성하기 위하여 제 1 개구부 및 제 2 개구부의 측벽 표면을 피복하는 스텝과, 도전층을 형성하기 위하여 절연층의 내부, 적어도 절연층의 내벽 표면과 제 2 개구부의 바닥 표면을 피복하는 스텝을 포함하는 반도체장치의 제조방법이 제공되어 있다.According to another aspect of the invention, there is provided a step of providing a semiconductor substrate having first and second surfaces opposite each other, and forming an electronic device on a first surface that is an active surface of the semiconductor substrate and forming a peripheral portion of the electronic device on an active surface. Forming a pad electrode so as to be connected to the electronic device at step 2, forming a first opening extending from the second surface of the semiconductor substrate toward the pad electrode so as not to reach the first surface of the semiconductor substrate, and Forming a second opening having a diameter smaller than the diameter of the first opening to reach the pad electrode from the bottom surface, covering the sidewall surfaces of the first opening and the second opening to form an insulating layer, and conducting Covering the inside of the insulating layer, at least the inner wall surface of the insulating layer and the bottom surface of the second opening to form a layer There is provided a method of manufacturing a semiconductor device comprising a.

상기한 반도체장치의 제조방법에 있어서, 전자소자는 반도체 기판의 제 1 표면상에서 형성되고, 패드 전극은 액티브 표면상에서 전자소자의 주변부에서 전자소자로 접속되도록 형성된다.In the above method of manufacturing a semiconductor device, an electronic element is formed on the first surface of the semiconductor substrate, and the pad electrode is formed to be connected to the electronic element at the periphery of the electronic element on the active surface.

다음에, 제 1 개구부는 반도체 기판의 제 1 표면에 도달하지 않도록 반도체 기판의 제 2 표면으로부터 패드 전극을 향하여 연장하도록 형성되고, 제 1 개구부의 직경보다 작은 직경을 가지는 제 2 개구부는 제 1 개구부의 바닥 표면으로부터 패드 전극에 도달하도록 형성된다.Next, the first opening is formed to extend toward the pad electrode from the second surface of the semiconductor substrate so as not to reach the first surface of the semiconductor substrate, and the second opening having a diameter smaller than the diameter of the first opening is the first opening. It is formed to reach the pad electrode from the bottom surface of the.

그 다음에, 제 1 개구부 및 제 2 개구부의 측벽 표면은 절연층을 형성하도록 피복되고, 절연층의 내부, 적어도 절연층의 내벽 표면과 제 2 개구부의 바닥 표면 은 도전층을 형성하도록 피복된다.Then, the sidewall surfaces of the first opening and the second opening are covered to form an insulating layer, and the inside of the insulating layer, at least the inner wall surface of the insulating layer and the bottom surface of the second opening are coated to form a conductive layer.

본 발명의 각 실시형태에 따른 반도체장치에 의하면, 이하의 유리한 효과가 얻어질 수 있다.According to the semiconductor device according to each embodiment of the present invention, the following advantageous effects can be obtained.

본 실시형태들의 반도체장치에서는, 패드 전극을 접촉하는 개구부(제 2 개구부)의 직경이 작게 될 경우, 개구부에 형성되는 도전층의 열팽창의 영향이 감소될 수 있다. 결과적으로 고신뢰성이 달성될 수 있다.In the semiconductor devices of the present embodiments, when the diameter of the opening (second opening) in contact with the pad electrode becomes small, the influence of thermal expansion of the conductive layer formed on the opening can be reduced. As a result, high reliability can be achieved.

보다 직경이 큰 제 1 개구부가 패드 전극을 접촉하는 부분을 제외하고 형성되며, 결과적으로 스루홀 형성의 TAT(Turn Around Time)가 짧아질 수 있고, 두꺼운 웨이퍼에서도 적용될 수 있다. 따라서 핸들링성(handling ability)의 향상도 또한 달성될 수 있다.The first opening having a larger diameter is formed except for the portion in contact with the pad electrode. As a result, the TAT (Turn Around Time) of the through hole formation can be shortened, and it can be applied to a thick wafer. Thus, an improvement in handling ability can also be achieved.

또, 패드 전극은 직경이 보다 작은 제 2 개구부에 의해 접촉되므로, 스루홀과 패드 전극의 위치 맞춤(얼라인먼트)의 자유도가 개선된다. 결과적으로, 스루홀은 반도체 웨이퍼의 검사 시에 프로브(probe)에 의한 자국을 피하도록 형성될 수 있으며, 그것에 의해 스루홀의 수율이 향상될 수 있다.In addition, since the pad electrode is contacted by the second opening having a smaller diameter, the degree of freedom of alignment (alignment) of the through hole and the pad electrode is improved. As a result, the through hole can be formed so as to avoid the marks by the probe during the inspection of the semiconductor wafer, whereby the through hole yield can be improved.

게다가, 보다 직경이 작은 제 2 개구부가 형성될 경우, 패드 전극의 소형화도 또한 달성될 수 있다.In addition, miniaturization of the pad electrode can also be achieved when a second opening having a smaller diameter is formed.

절연층이 제 2 개구부와 비교해서 제 1 개구부의 벽 표면상에서 보다 두껍게 형성되기 때문에, 개구부의 도전층 내부와 반도체 기판의 사이에서 기생 용량(parasitic capacitance)이 감소될 수 있다.Since the insulating layer is formed thicker on the wall surface of the first opening as compared with the second opening, parasitic capacitance can be reduced between the conductive layer of the opening and the semiconductor substrate.

이하에, 도면을 참조하여 본 발명의 반도체장치 및 그 제조방법의 실시형태를 설명한다.EMBODIMENT OF THE INVENTION Below, embodiment of the semiconductor device of this invention and its manufacturing method is described with reference to drawings.

제 1 실시형태1st Embodiment

도 1a는 본 실시형태에 따른 반도체장치의 약식 단면도이며, 도 1b는 도 1a의 주요부 확대도이다.FIG. 1A is a schematic cross-sectional view of a semiconductor device according to the present embodiment, and FIG. 1B is an enlarged view of an essential part of FIG. 1A.

본 실시형태에 따른 반도체장치는, CMOS 이미지 센서와 같은 고체 촬상 센서를 가지는 반도체 칩 상에서 구성된 것이며, 고체 촬상 센서는 공기가 통하지 않게 밀봉되어, 그것에 의해 패키지 형태가 실현된다.The semiconductor device according to the present embodiment is configured on a semiconductor chip having a solid-state imaging sensor such as a CMOS image sensor, and the solid-state imaging sensor is sealed to prevent air from passing through, thereby realizing a package form.

반도체 기판(10)은 서로 반대편의 제 1 표면과 제 2 표면을 가지고 있다. 예를 들면, 실리콘으로 형성된 반도체 기판(10)의 액티브 표면인 제 1 표면상에서, CMOS 이미지 센서와 같은 고체 촬상 센서가 형성된다.The semiconductor substrate 10 has a first surface and a second surface opposite to each other. For example, on a first surface which is the active surface of the semiconductor substrate 10 formed of silicon, a solid state imaging sensor such as a CMOS image sensor is formed.

또, 예를 들면, 반도체 기판(10)의 액티브 표면상에서, 고체 촬상 센서(11)의 주변부에서, 패드 전극(12)은 고체 촬상 센서(11)와 접속되도록 형성된다.In addition, for example, on the active surface of the semiconductor substrate 10, at the periphery of the solid state imaging sensor 11, the pad electrode 12 is formed to be connected to the solid state imaging sensor 11.

예를 들면, 반도체 기판(10)의 액티브 표면의 반대쪽인 제 2 표면은, 유리와 같은 투명 기판으로 형성된 패키지 기판(14)이 배치된다. 반도체 기판(10)상의 고체 촬상 센서(11)의 주변부와 패키지 기판(14) 사이의 간극에 밀봉 수지층(13)이 형성되어, 이것에 의해 고체 촬상 센서(11)가 공기가 통하지 않게 밀봉된다.For example, a package substrate 14 formed of a transparent substrate such as glass is disposed on the second surface opposite to the active surface of the semiconductor substrate 10. The sealing resin layer 13 is formed in the gap between the periphery of the solid-state imaging sensor 11 on the semiconductor substrate 10 and the package substrate 14, whereby the solid-state imaging sensor 11 is sealed without passing air. .

예를 들면, 제 1 개구부(H1)는 반도체 기판(10)의 제 1 표면에 도달하지 않도록 반도체 기판(10)의 제 2 표면으로부터 패드 전극(12)을 향하여 연장하도록 형 성되며, 제 1 개구부(H1)의 직경보다 작은 직경을 가지는 제 2 개구부(H2)는 제 1 개구부의 바닥 표면으로부터 패드 전극에 도달하도록 형성된다.For example, the first opening H1 is formed to extend toward the pad electrode 12 from the second surface of the semiconductor substrate 10 so as not to reach the first surface of the semiconductor substrate 10, and the first opening H1. The second opening H2 having a diameter smaller than the diameter of H1 is formed to reach the pad electrode from the bottom surface of the first opening.

예를 들면, 산화실리콘 등으로 형성된 절연층(20)이 제 1 개구부(H1) 및 제 2 개구부(H2)의 측벽 표면을 피복하도록 형성된다. 구리 등으로 형성된 절연층(20)의 내부인 도전층(21)은 적어도 절연층(20)의 내벽 표면과 제 2 개구부의 바닥 표면을 피복하도록 형성된다.For example, an insulating layer 20 made of silicon oxide or the like is formed to cover the sidewall surfaces of the first opening H1 and the second opening H2. The conductive layer 21 inside the insulating layer 20 formed of copper or the like is formed to cover at least the inner wall surface of the insulating layer 20 and the bottom surface of the second opening.

절연층(20)은 반도체 기판(10)과 도전층(21) 사이에서 단락을 피하기 위한 층이다. 절연층(20)과 도전층(21)이 반도체 기판(10)의 액티브 표면의 반대측의 표면상에서 개구부의 외부로까지 인출되며, 납 전극으로서의 기능을 한다.The insulating layer 20 is a layer for avoiding a short circuit between the semiconductor substrate 10 and the conductive layer 21. The insulating layer 20 and the conductive layer 21 are led out to the outside of the opening on the surface on the opposite side of the active surface of the semiconductor substrate 10, and function as lead electrodes.

솔더레지스트 등인 보호막(22)이 반도체 기판(10)의 액티브 표면의 반대측의 표면을 피복하도록 형성된다. 도전층(21)의 일부를 노출하는 개구부는 보호막(22)상에서 제공되며, 솔더링 볼 범프(soldering ball bump)나 골드 스터드 범프(gold stud bump)와 같은 범프(23)가 거기에서 형성된다.A protective film 22, such as a solder resist, is formed so as to cover the surface opposite to the active surface of the semiconductor substrate 10. An opening that exposes a portion of the conductive layer 21 is provided on the protective film 22, and bumps 23, such as soldering ball bumps or gold stud bumps, are formed therein.

상기에서 기술된 바와 같이, 본 발명의 한 실시형태에 따른 반도체장치가 구성되어 있다.As described above, a semiconductor device according to one embodiment of the present invention is constructed.

본 발명의 한 실시형태에 따른 반도체장치가, 예를 들면, 실장기판 등 상에서 범프(23)를 경유하여 실장되거나 또는 모듈에서 사용될 메모리 소자 등으로 형성된 또 다른 기판에 실장됨으로써 이용된다.The semiconductor device according to one embodiment of the present invention is used by being mounted on, for example, a bump 23 on a mounting substrate or the like on another substrate formed of a memory element or the like to be used in a module.

도 2는 본 발명의 제 1 실시형태에 따른 반도체장치의 각 부분의 사이즈를 설명하기 위한 약식도이다.2 is a schematic view for explaining the size of each part of the semiconductor device according to the first embodiment of the present invention.

상기의 반도체장치에 있어서, 바람직하게는, 제 2 개구부(H2)의 직경(a2)이, 제 1 개구부(H1)의 직경(a1의) 0.7배 이하이며, 더 바람직하게는 0.5배 이하이다.In the above semiconductor device, preferably, the diameter a2 of the second opening H2 is 0.7 times or less, more preferably 0.5 times or less of the diameter a1 of the first opening H1.

후술될 제조방법에서 설명되는 바와 같이, 패드 전극(12)에 대한 제 2 개구부(H2)의 얼라인먼트(alignment)의 자유도를 증가시키는 것이 가능할 수 있다.As described in the manufacturing method described below, it may be possible to increase the degree of freedom of alignment of the second opening H2 with respect to the pad electrode 12.

또, 바람직하게는, 제 1 개구부(H1)의 깊이(b1)가, 반도체 기판(10)의 두께(B)의 0.5배 이상이고 0.9배 이하이다.Moreover, preferably, the depth b1 of the 1st opening part H1 is 0.5 times or more and 0.9 times or less of the thickness B of the semiconductor substrate 10.

만약 제 1 개구부(H1)의 깊이(b1)가 반도체 기판(10)의 두께(B)의 0.5배 미만일 경우, 제 2 개구부(H2)의 애스펙트 비(aspect ratio)가 너무 커지게 된다. 그래서, 제 2 개구부(H2)의 개구나 도전층에서의 임베딩(embedding) 스텝 등이 곤란해질 수 있다. 결과로서, TAT(Turn Around Time)가 길게 될 가능성이 있다. 또 만약, 깊이(b1)가 0.9배를 넘을 경우, 제 2 개구부(H2)가 형성되는 부분에서 반도체 기판(10)의 두께가 너무 얇아진다. 따라서, 제 2 개구부(H2)의 형성시에나 또는 그 후의 신뢰성 사이클에 있어서 불편이 생길 가능성이 더 있을 수 있다.If the depth b1 of the first opening H1 is less than 0.5 times the thickness B of the semiconductor substrate 10, the aspect ratio of the second opening H2 becomes too large. Therefore, the opening of the second opening H2, the embedding step in the conductive layer, or the like can be difficult. As a result, there is a possibility that the TAT (Turn Around Time) becomes long. If the depth b1 exceeds 0.9 times, the thickness of the semiconductor substrate 10 becomes too thin in the portion where the second opening H2 is formed. Therefore, there may be a possibility that inconvenience may occur in the formation of the second opening H2 or in a subsequent reliability cycle.

예를 들면, 반도체 기판(10)의 두께(B)가 200μm, 제 1 개구부(H1)의 직경(a1)이 80μm, 깊이(b1)가 160μm, 제 2 개구부(H2)의 직경(a2)이 30μm, 깊이(b2)가 40μm일 경우, 양호한 스루홀의 형상이 실현될 수 있다.For example, the thickness B of the semiconductor substrate 10 is 200 μm, the diameter a1 of the first opening H1 is 80 μm, the depth b1 is 160 μm, and the diameter a2 of the second opening H2 is When 30 μm and the depth b2 is 40 μm, a good through hole shape can be realized.

또, 절연층(20)에 있어서, 제 1 개구부(H1)의 측벽 표면을 피복하는 부분의 두께(c1)가, 제 2 개구부(H2)의 측벽 표면을 피복하는 부분의 두께(c2)보다 더 두꺼워야 바람직하다.In addition, in the insulating layer 20, the thickness c1 of the portion covering the sidewall surface of the first opening H1 is greater than the thickness c2 of the portion covering the sidewall surface of the second opening H2. It is desirable to be thick.

큰 직경을 갖는 제 1 개구부(H1)의 부분에서의 절연층의 두께(c1)가 두껍게 되고, 제 2 개구부(H2)의 부분에서의 절연층(20)의 두께가 얇게 될 경우, 도전층과 반도체 기판(10) 간의 기생 용량(parasitic capacitance)은 감소된다. 결과적으로, 반도체장치의 저소비 전력화를 달성하고, 작은 직경을 갖는 제 2 개구부(H2)의 부분에서 도전재료 내에서 양호한 임베딩을 수행하는 것이 가능할 수 있다.When the thickness c1 of the insulating layer in the portion of the first opening H1 having a large diameter becomes thick and the thickness of the insulating layer 20 in the portion of the second opening H2 becomes thin, the conductive layer and Parasitic capacitance between the semiconductor substrates 10 is reduced. As a result, it may be possible to achieve low power consumption of the semiconductor device and to perform good embedding in the conductive material in the portion of the second opening H2 having a small diameter.

절연층(20)은 산화 실리콘과 같은 1개의 절연성 재료로 형성되는 것이 바람직하지만, 복수의 재료로 형성될 수도 있다.The insulating layer 20 is preferably formed of one insulating material such as silicon oxide, but may be formed of a plurality of materials.

예를 들면, 절연층(20) 전부가 산화 실리콘으로 형성될 경우, 제조방법에서 후술되는 바와 같이, 제 1 개구부(H1)의 측벽 표면과 제 2 개구부(H2)의 측벽 표면이 산화 실리콘막을 형성하도록 피복되고, 제 2 개구부(H2)의 측벽 표면의 부분에서 산화 실리콘막을 재차 형성하면서, 제 2 개구부(H2)의 측벽 표면의 부분이 제 1 개구부(H1)의 부분의 절연층을 두껍게 하도록 제거되며, 그것에 의해 원하는 형태의 절연층이 형성될 수 있다.For example, when all of the insulating layer 20 is formed of silicon oxide, as described later in the manufacturing method, the sidewall surface of the first opening H1 and the sidewall surface of the second opening H2 form a silicon oxide film. So that a portion of the sidewall surface of the second opening H2 thickens the insulating layer of the portion of the first opening H1 while again forming a silicon oxide film at the portion of the sidewall surface of the second opening H2. By this, an insulating layer of a desired shape can be formed.

기술 개발에 있어 문제인, 기판을 관통하는 개구부의 내벽에 도전층이 형성되는 구성에 있어서, 도전층의 직경을 크랙이나 필링을 방지할 수 있을 만큼 작게 하는 것이 효과적이다. 예를 들면, 단순하게 스루홀의 직경 크기를 줄이는 것을 생각할 수 있지만, 이 경우, 스루홀의 가공성이 떨어져, 패드 전극에 도달하는 개구부를 형성하는 것이 매우 어려워질 수 있다. 또, 스루홀의 직경 크기가 축소될 경우, 도전층의 형성시에 도전체의 임베딩 성능이 떨어져, 도전층을 형성하는 것이 매우 어려워질 수 있다.In a configuration in which a conductive layer is formed on an inner wall of an opening that penetrates a substrate, which is a problem in technology development, it is effective to make the diameter of the conductive layer small enough to prevent cracking or peeling. For example, it is conceivable to simply reduce the diameter size of the through hole, but in this case, the workability of the through hole is poor, and it may be very difficult to form an opening reaching the pad electrode. In addition, when the diameter of the through hole is reduced, the embedding performance of the conductor is degraded at the time of forming the conductive layer, which makes it very difficult to form the conductive layer.

또, 스루홀의 직경은 종래와 같이 유지되고, 벽 표면상에 형성된 산화 실리 콘막의 두께는 두껍게 되고, 도전층의 직경 크기는 축소되는 것이 고려될 수도 있다. 하지만, 이 경우에서도, 도전층이 형성되는 공간의 직경이 작아지므로, 도전체의 임베딩 성능이 떨어지게 된다. 결과적으로, 도전층을 형성하는 것이 매우 어려워질 수 있다.In addition, it may be considered that the diameter of the through hole is maintained as in the prior art, the thickness of the silicon oxide film formed on the wall surface becomes thick, and the diameter size of the conductive layer is reduced. However, also in this case, since the diameter of the space in which the conductive layer is formed becomes small, the embedding performance of the conductor is degraded. As a result, forming the conductive layer can be very difficult.

본 발명의 한 실시형태의 반도체장치에 의해서, 스루홀은 제 1 개구부와 제 1 개구부보다 직경이 작은 제 2 개구부로 형성된다. 따라서 스루홀내에 채워진 도전층과 기판이나 패드 전극과 사이에서 열팽창 계수의 차이로 인해 발생되는 크랙이나 필링을 막을 수 있다.According to the semiconductor device of one embodiment of the present invention, the through hole is formed by the first opening portion and the second opening portion smaller in diameter than the first opening portion. Therefore, cracks or peeling caused by the difference in thermal expansion coefficient between the conductive layer filled in the through hole and the substrate or the pad electrode can be prevented.

게다가 직경이 작은 부분은 제 2 개구부뿐이어서, 스루홀의 형성도 용이해 진다. 또, 스루홀내에서의 도전체의 임베딩 성능은 악화를 일으키지 않고 실현된다.In addition, since the portion having the small diameter is only the second opening portion, the formation of the through hole also becomes easy. In addition, the embedding performance of the conductor in the through hole is realized without causing deterioration.

도 3 내지 도 8을 참조하여, 상술된 본 발명의 실시형태들의 반도체장치의 제조방법이 기술된다.3 to 8, a method of manufacturing a semiconductor device of the above-described embodiments of the present invention is described.

우선, 도 3a에 나타내는 바와 같이, 실리콘 등으로 형성된 반도체 기판(10)의 액티브 표면상에, CMOS 이미지 센서와 같은 고체 촬상 센서(11)가 형성되고, 예를 들면 또, 반도체 기판(10)의 액티브 표면상에서, 고체 촬상 센서(11)의 주변부에서 고체 촬상 센서(11)에 접속되도록 패드 전극(12)이 형성된다.First, as shown in FIG. 3A, a solid-state imaging sensor 11, such as a CMOS image sensor, is formed on the active surface of the semiconductor substrate 10 formed of silicon or the like. On the active surface, the pad electrode 12 is formed to be connected to the solid state imaging sensor 11 at the periphery of the solid state imaging sensor 11.

다음에, 도 3b에 나타내는 바와 같이, 예를 들면, 스핀 코트법 등에 의해 감광성 수지층이 도포되고, 반도체 기판(10)상에서 패드 전극(12)을 피복하는 영역의 수지가 고체 촬상 센서(11)의 주변부에 남겨 지고, 고체 촬상 센서(11)의 영역에서 수지가 제거되도록 노광 및 현상이 수행되며, 그것에 의해 반도체 기판(10)상에서 고체 촬상 센서(11)의 주변부에 밀봉 수지층(13)이 형성된다.Next, as shown in FIG. 3B, the photosensitive resin layer is apply | coated by the spin coat method etc., for example, and the resin of the area | region which covers the pad electrode 12 on the semiconductor substrate 10 is a solid-state imaging sensor 11. Exposure and development are performed so that the resin is removed in the region of the solid-state imaging sensor 11, thereby leaving the sealing resin layer 13 on the periphery of the solid-state imaging sensor 11 on the semiconductor substrate 10. Is formed.

밀봉 수지층(13)으로 피복된 영역은, 다음 스텝에서 접착된 패키지 기판과의 밀착 강도에 관련하기 때문에, 적절하게 최적치를 선택할 필요가 있다, 바람직하게는, 그 영역은 패드 전극(12)의 폭보다 크고, 밀봉 수지층(13)이 제거되어야 할 영역으로부터 안쪽으로 10μm 이상 간격을 두는 것이 바람직하다. 그 영역이 밀봉 수지층이 제거되어야 할 영역에 정확히 형성될 때, 패키지 기판을 접착하기 위한 그 다음의 스텝에서 밀봉 수지가 삐져나오는 경우에 있어서 결함조건이 발생해 버릴 수도 있다.Since the area | region covered with the sealing resin layer 13 relates to the adhesive strength with the package substrate adhere | attached in the next step, it is necessary to select an optimal value suitably, Preferably, the area | region of the pad electrode 12 is carried out. It is preferable to space larger than the width and to space inwardly 10 m or more from the region where the sealing resin layer 13 is to be removed. When the area is exactly formed in the area where the sealing resin layer is to be removed, a defect condition may occur in the case where the sealing resin sticks out in the next step for adhering the package substrate.

다음에, 도 4a에 나타내는 바와 같이, 예를 들면, 반도체 기판(10)의 액티브 표면에 면하는 방식으로 밀봉 수지층(13) 상에서 유리와 같은 투명 기판으로 형성된 패키지 기판(14)이 배치되고, 패키지 기판(14) 및 밀봉 수지층(13)에 의해 고체 촬상 센서(11)가 공기가 통하지 않게 밀봉된다.Next, as shown in FIG. 4A, a package substrate 14 formed of a transparent substrate such as glass is disposed on the sealing resin layer 13 in a manner facing the active surface of the semiconductor substrate 10, for example. The solid-state imaging sensor 11 is sealed by the package substrate 14 and the sealing resin layer 13 to prevent air from passing through.

밀봉 수지층(13)은, 패드 전극(12)을 피복하는 부분과 유리와 같은 투명 기판으로 형성된 패키지 기판(14)을 공기가 통하지 않게 밀봉하는 부분이 단일의 밀봉 수지층으로 형성되도록 구성된다. 그렇지만 밀봉 수지층은 복수의 밀봉 수지로 형성되어도 좋다.The sealing resin layer 13 is comprised so that the part which coats the pad electrode 12 and the part which seals the package board | substrate 14 formed from the transparent substrate, such as glass, through air | atmosphere may be formed by a single sealing resin layer. However, the sealing resin layer may be formed of a plurality of sealing resins.

도 4b는 도 4a의 주요부 확대도이며, 이후의 스텝은 확대도에 의해 설명된다.FIG. 4B is an enlarged view of a main part of FIG. 4A, and subsequent steps are explained by an enlarged view.

다음에, 도 5a에 나타내는 바와 같이, 예를 들면, 반도체 기판(10)의 액티브 표면의 반대측의 표면에서, 제 1 개구부를 개구하는 패턴의 레지스트막(도시하지 아니함)이 포토리소그라피(photolithography) 스텝에 의해 형성되고, 반응성 이온 에칭(RIE(reactive ion etching))과 같은 이방성(異方性) 드라이 에칭 처리가, 패드 전극(12)을 향하여 반도체 기판(10)의 2차 표면에서 연장하는 제 1 개구부(H1)를 형성하도록 가해진다.Next, as shown in FIG. 5A, for example, a resist film (not shown) having a pattern that opens the first opening on the surface on the opposite side of the active surface of the semiconductor substrate 10 is subjected to a photolithography step. Is formed by the film, and an anisotropic dry etching process such as reactive ion etching (RIE) extends from the secondary surface of the semiconductor substrate 10 toward the pad electrode 12. It is applied to form the opening H1.

여기서, 제 1 개구부(H1)의 깊이는 반도체 기판(10)의 두께의 0.5배 이상이고 0.9배 이하로 하는 것이 바람직하다.Here, the depth of the first opening H1 is preferably 0.5 times or more and 0.9 times or less of the thickness of the semiconductor substrate 10.

다음에, 도 5b에 나타내는 바와 같이, 예를 들면, 화학기상반응(CVD(Chemical Vapor Deposition))법에 의해, 제 1 개구부(H1)의 측벽 표면과 그 바닥 표면은 수 100 nm 내지 수μm의 막 두께로 산화 실리콘을 퇴적하여 피복되어, 그것에 의해 절연층(20)이 형성된다.Next, as shown in FIG. 5B, for example, by the chemical vapor deposition (CVD) method, the sidewall surface and the bottom surface of the first opening H1 are several hundred nm to several μm. Silicon oxide is deposited and coated at a film thickness, whereby an insulating layer 20 is formed.

다음에, 도 6a에 나타내는 바와 같이, 예를 들면, 제 1 개구부의 바닥 표면 부분을 개구하는 패턴의 레지스트막(도시하지 아니함)이 포토리소그라피 스텝에 의해 형성되고, RIE와 같은 이방성 드라이 에칭 처리가 제 1 개구부(H1)의 바닥 표면 부분의 절연층을 제거하도록 가해진다.Next, as shown in Fig. 6A, for example, a resist film (not shown) having a pattern opening the bottom surface portion of the first opening is formed by a photolithography step, and anisotropic dry etching treatment such as RIE is performed. It is applied to remove the insulating layer of the bottom surface portion of the first opening H1.

다음에, 도 6b에 나타내는 바와 같이, 예를 들면, YAG 레이저의 4 차 고조파(266 nm) 혹은 ArF 엑시머 레이저와 같은 레이저빔이, 제 1 개구부(H1)의 바닥 표면으로부터 패드 전극(12)에 이르도록, 직경이 제 1 개구부(H1)보다 작은 제 2 개구부(H2)를 형성하도록 조사된다.Next, as shown in FIG. 6B, for example, a fourth harmonic (266 nm) of a YAG laser or a laser beam such as an ArF excimer laser is applied from the bottom surface of the first opening H1 to the pad electrode 12. As far as it can go, it is irradiated to form a second opening H2 whose diameter is smaller than the first opening H1.

예를 들면, YAG 레이저의 4 차 고조파(266 nm)의 이용은, 직경이 10μm이하 인 개구부의 형성을 허용할 수 있다.For example, the use of the fourth harmonic (266 nm) of the YAG laser can allow the formation of openings with a diameter of 10 μm or less.

여기서, 바람직하게는, 제 2 개구부(H2)의 직경이 제 1 개구부(H1)의 직경의 0.7배 이하이며, 더 바람직하게는 0.5배 이하이다.Here, preferably, the diameter of the 2nd opening part H2 is 0.7 times or less of the diameter of the 1st opening part H1, More preferably, it is 0.5 times or less.

제 1 개구부(H1)의 깊이의 바람직한 범위로부터 판단하면, 제 2 개구부의 깊이의 바람직한 범위는 반도체 기판(10)의 두께의 0.1배 이상이고 0.5배 이하이다. 특히, 제 1 개구부(H1)의 개구 스텝에 있어서 웨이퍼 표면내에서 3% ~ 5％의 가공 격차가 있기 때문에, 예를 들면, 반도체 기판의 두께가 200μm일 경우에 있어서는 10μm 정도의 마진이 필요하고, 따라서 제 2 개구부(H2)의 깊이는 10μm 이상이 바람직하다.Judging from the preferred range of the depth of the first opening H1, the preferred range of the depth of the second opening is 0.1 times or more and 0.5 times or less of the thickness of the semiconductor substrate 10. In particular, since there is a processing gap of 3% to 5% in the wafer surface in the opening step of the first opening H1, for example, when the thickness of the semiconductor substrate is 200 μm, a margin of about 10 μm is required. Therefore, the depth of the second opening portion H2 is preferably 10 μm or more.

다음에, 도 7a에 나타내는 바와 같이, 예를 들면, CVD법에 따라, 산화 실리콘막이 절연층(20)을 형성하도록 제 2 개구부(H2)의 측벽 표면의 부분에 형성되고, 절연층(20)은 제 1 개구부(H1)의 부분의 막에서 두껍게 된다.Next, as shown in FIG. 7A, for example, a silicon oxide film is formed in the portion of the sidewall surface of the second opening H2 so as to form the insulating layer 20 by the CVD method, and the insulating layer 20 is formed. Becomes thick in the film of the part of the first opening H1.

상기의 스텝들의 결과, 절연층(20)으로서, 제 1 개구부(H1)의 측벽 표면을 피복하는 부분이, 제 2 개구부(H2)의 측벽 표면을 피복하는 부분보다 두꺼워지도록 형성하는 것이 가능해질 수 있다.As a result of the above steps, as the insulating layer 20, it is possible to form the portion covering the side wall surface of the first opening H1 to be thicker than the portion covering the side wall surface of the second opening H2. have.

그 후에, 도 7b에 나타내는 바와 같이, 예를 들면, 적어도 절연층(20)의 내벽 표면과 제 2 개구부(H2)의 바닥 표면은 스퍼터링(sputtering)에 의한 구리로 형성된 시드(seed)층의 형성과 구리 전해 도금 처리 등에 의해 절연층(20)의 내부가 피복되고, 그것에 의해 구리로 형성된 도전층(21)이 형성된다.After that, as shown in FIG. 7B, for example, at least the inner wall surface of the insulating layer 20 and the bottom surface of the second opening H2 are formed of a seed layer formed of copper by sputtering. And the inside of the insulating layer 20 are coated by a copper electroplating process or the like, whereby a conductive layer 21 made of copper is formed.

다음에, 도 8a에 나타내는 바와 같이, 예를 들면, 소정의 패턴의 레지스트 막(도시하지 아니함)이 포토리소그라피 스텝에 의해 형성되고, RIE와 같은 이방성 드라이 에칭 처리를 통하여, 도전층(21)과 절연층(20)은 반도체 기판(10)의 액티브 표면의 반대측의 표면상에서 개구로 인출된 인출 전극을 형성하도록 패턴된다.Next, as shown in FIG. 8A, for example, a resist film (not shown) having a predetermined pattern is formed by a photolithography step, and the conductive layer 21 is subjected to an anisotropic dry etching process such as RIE. The insulating layer 20 is patterned to form an extraction electrode drawn out into the opening on the surface on the opposite side of the active surface of the semiconductor substrate 10.

다음에, 반도체 기판(10)의 액티브 표면의 반대측의 표면은 제 1 개구부(H1) 및 제 2 개구부(H2)의 안쪽에서 임베딩하도록 피복되고, 그것에 의해 솔더레지스트와 같은 보호막(22)이 형성된다. 보호막(22)은 범프(bump) 형성 영역에 있어서 도전층(21)을 노출시키는 개구부를 형성한다.Next, the surface on the opposite side of the active surface of the semiconductor substrate 10 is covered to be embedded inside the first opening H1 and the second opening H2, whereby a protective film 22 such as a solder resist is formed. . The protective film 22 forms an opening that exposes the conductive layer 21 in the bump formation region.

보호막에 관하여, 제 1 개구부(H1) 및 제 2 개구부(H2)의 안쪽에서의 임베딩 부분과 반도체 기판(10)의 액티브 표면의 반대측의 표면을 피복하는 부분은 동일한 절연층 재료로 형성되어 있지만, 서로 다른 절연성 재료로 형성되어도 좋다.As for the protective film, the embedding portion inside the first opening H1 and the second opening H2 and the portion covering the surface on the opposite side of the active surface of the semiconductor substrate 10 are formed of the same insulating layer material, It may be formed of different insulating materials.

다음에, 도 8b에 나타내는 바와 같이, 예를 들면, 솔더 볼 범프(solder ball bump)나 골드 스터드 범프(gold stud bump)와 같은 범프(23)가 보호막(22)의 개구부에서 형성된다.Next, as shown in FIG. 8B, bumps 23, for example, solder ball bumps and gold stud bumps, are formed in the openings of the protective film 22.

상기된 바와 같이, 본 발명의 실시형태에 따른 반도체장치가 형성된다.As described above, the semiconductor device according to the embodiment of the present invention is formed.

상기된 스텝들을 따르는 스텝으로서는, 상기된 스텝들이 웨이퍼 레벨상에서수행되는 경우에 있어서, 예를 들면 상기의 스텝을 웨이퍼 레벨로 갔을 경우, 다이싱 처리(dicing process)가 수행되어 개편화된다.As the steps following the above-described steps, in the case where the above-described steps are performed on the wafer level, for example, when the above steps go to the wafer level, a dicing process is performed and separated.

본 발명의 한 실시형태에 따른 반도체장치의 제조방법에 의하면, 제 1 개구부와 제 1 개구부보다 직경이 작은 제 2 개구부가 스루홀로서 형성될 경우, 스루홀 안에 채워진 도전층과 기판이나 패드 전극 사이에서 열팽창 계수의 차이로 인해 발 생되는 크랙이나 필링을 막을 수 있다.According to the method of manufacturing a semiconductor device according to one embodiment of the present invention, when a first opening and a second opening having a diameter smaller than the first opening are formed as through holes, between the conductive layer filled in the through holes and the substrate or pad electrode. This prevents cracking and peeling caused by differences in the coefficient of thermal expansion at.

최근에, 반도체장치의 저소비 전력화나 고속화가 더욱 요구되고 있고, 스루홀 안에 채워진 도전층의 기생 용량의 감소도 또한 요구되고 있다. 스루홀 내부의 도전층의 저용량화에 대해서는, 스루홀의 측벽에 형성된 도전재료층과 실리콘 기판간에 형성된 절연층이 두껍게 형성될 경우, 보다 저용량을 가진 도전재료층을 실현할 수 있다. 실리콘과의 절연을 확보하기 위한 절연재(예를 들면, 산화 실리콘)를 형성함에 있어서, 커버리지(coverage)의 균일성을 유지하기 위하여 CVD법 등이 일반적으로 채용되고 있다. 그렇지만, 직경이 가늘어지는 형상의 종래의 스루홀 형상에서의 경우, 절연층이 두껍게 되면 개구부 바닥 부분 근방에서 도전층의 임베딩성이 악화되고, 또 한편, 저용량화를 달성하기 위하여 절연층이 두껍게 되면 시간이 걸리게 되어, 그것에 의해 TAT가 길어진다고 하는 문제가 발생한다.In recent years, lower power consumption and higher speed of semiconductor devices have been further demanded, and a reduction in parasitic capacitance of conductive layers filled in through holes is also required. Regarding the reduction of the capacitance of the conductive layer inside the through hole, when the insulating layer formed between the conductive material layer formed on the sidewall of the through hole and the silicon substrate is formed thick, a conductive material layer having a lower capacity can be realized. In forming an insulating material (for example, silicon oxide) for securing insulation from silicon, a CVD method or the like is generally employed to maintain uniformity of coverage. However, in the conventional through-hole shape having a thinner diameter, when the insulating layer becomes thick, the embedding property of the conductive layer becomes worse near the bottom portion of the opening, and when the insulating layer becomes thick in order to achieve lower capacity It takes time, and the problem that TAT becomes long by this arises.

본 발명의 실시형태에 따른 반도체장치에서, 절연막이 두번 형성되므로, 절연막의 두께가 용이하게 두껍게 될 수 있다. 또, 직경이 큰 제 1 개구부만이 두껍게 되기 때문에, 제 2 개구부에서는 절연막이 얇게 형성되어, 그것에 의해 도전층의 임베딩성의 악화가 예방될 수 있다.In the semiconductor device according to the embodiment of the present invention, since the insulating film is formed twice, the thickness of the insulating film can be easily thickened. In addition, since only the first opening having a large diameter becomes thick, the insulating film is thinly formed in the second opening, whereby the deterioration of the embedding property of the conductive layer can be prevented.

또, 검사시에 패드 전극에 남겨진 프로브(probe)에 의한 자국이 스루홀의 형성 영역과 겹쳐질 경우, 패드 부식과 같은 결함 조건이 발생될 수도 있다.In addition, a defect condition such as pad corrosion may occur when a mark by a probe left on the pad electrode at the time of inspection overlaps with the formation area of the through hole.

도 9a는, 패드 전극에 있어서 프로브에 의한 자국과 제 2 개구부의 개구 영역을 나타내는 레이아웃차트이다. 패드 전극(P)상에서, 프로브에 의한 자국(T)과 제 2 개구부(H2)의 개구 영역이 서로 겹쳐지지 않도록 레이아웃 되어 있다.FIG. 9A is a layout chart showing the marks by the probe and the opening region of the second opening in the pad electrode. FIG. On the pad electrode P, it is laid out so that the trace T by a probe and the opening area | region of the 2nd opening part H2 may not overlap with each other.

본 발명의 실시형태에 따른 반도체장치의 제조방법에서는, 실제로 패드 전극에 도달하는 제 2 개구부는 레이저 조사로 형성되기 때문에, 제 2 개구부가 고정밀도의 위치 맞춤으로 형성될 수 있다. 결과적으로, 오조정(misalignment)이 감소될 수 있고, 그것에 의해, 도 9a에 나타내는 바와 같이, 프로브에 의한 자국을 피해서 스루홀이 형성될 수 있다.In the manufacturing method of the semiconductor device according to the embodiment of the present invention, since the second opening portion actually reaching the pad electrode is formed by laser irradiation, the second opening portion can be formed with high precision alignment. As a result, misalignment can be reduced, whereby a through hole can be formed avoiding a mark by the probe, as shown in Fig. 9A.

또, 스루홀의 크기를 줄임에 관하여, 본딩 패드(bonding pad)는 스루홀을 형성하여 장치의 바닥 표면으로부터 접촉되므로, 조정 정밀 측면에서, 스루홀 등의 오조정이 일어나고, 그래서 웨이퍼의 전체 수율(yield)이 감소될 수 있다. 따라서 본딩 패드의 크기를 줄이기 곤란해져서 결국 장치 크기의 소형화는 불리로 끝나 버린다.In addition, in terms of reducing the size of the through hole, since the bonding pad forms a through hole and contacts from the bottom surface of the device, in terms of adjustment precision, misadjustment such as through hole occurs, so that the overall yield of the wafer ( yield may be reduced. Therefore, it is difficult to reduce the size of the bonding pads, and eventually the miniaturization of the device size is disadvantageous.

도 9b는, 패드 전극에 대한 제 1 개구부와 제 2 개구부를 나타내는 레이아웃차트이다.9B is a layout chart showing a first opening and a second opening with respect to the pad electrode.

본 발명의 실시형태에 따른 반도체장치의 제조방법에서는, 실제로 패드 전극에 도달하는 제 2 개구부는 레이저 조사로 형성되기 때문에, 오조정이 감소될 수 있다. 제 1 개구부(H1)가 패드 전극(P)에 대해서 오조정된다 하더라도, 도 9b에 나타내는 바와 같이, 제 2 개구부(H2)가 제 1 개구부(H1)와 패드 전극(P) 사이에서 어느 정도의 겹침이 있을 경우에는, 고정밀도로 형성될 수 있으며, 이것에 의해 패드 전극의 크기를 줄일 수 있다, 따라서 장치의 소형화가 실현될 수 있다.In the manufacturing method of the semiconductor device according to the embodiment of the present invention, since the second opening portion actually reaching the pad electrode is formed by laser irradiation, misalignment can be reduced. Even if the first opening portion H1 is misaligned with respect to the pad electrode P, as shown in FIG. 9B, the second opening portion H2 has a certain degree between the first opening portion H1 and the pad electrode P. FIG. In the case of overlapping, it can be formed with high precision, whereby the size of the pad electrode can be reduced, thus miniaturization of the device can be realized.

제 2 실시형태2nd Embodiment

도 10은 본 발명의 한 실시형태에 따른 반도체장치의 단면도이다.10 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.

제 1 실시형태에 따른 반도체장치가, 메모리 소자 등으로 형성된 또 다른 기판(30)상에서 배선(31)상에 범프(23)를 거쳐서 실장되고, 그것에 의해 모듈이 실현된다. 예를 들면, 이것은 이용을 위해 실장 기판에 실장된다.The semiconductor device according to the first embodiment is mounted on the wiring 31 via the bumps 23 on another substrate 30 formed of a memory element or the like, thereby realizing a module. For example, it is mounted on a mounting substrate for use.

또한, 제 1 실시형태에 따른 반도체장치가 여러 가지 실장기판과 반도체 기판 등 상에서 실장되어 이용될 수도 있다.Further, the semiconductor device according to the first embodiment may be mounted and used on various mounting substrates, semiconductor substrates, and the like.

본 발명의 한 실시형태에 따른 반도체장치는 제 1 개구부와 스루홀 처럼 제 1 개구부보다 직경이 작은 제 2 개구부로 구성되어 있다. 따라서 스루홀 안으로 채워진 도전층과 기판이나 패드 전극 사이에서 열팽창계수의 차이로 인하여 발생되는 크랙이나 필링을 막을 수 있게 된다.The semiconductor device according to one embodiment of the present invention is composed of a first opening portion and a second opening portion having a diameter smaller than the first opening portion, such as through holes. Therefore, it is possible to prevent cracks or peeling caused by the difference in thermal expansion coefficient between the conductive layer filled into the through hole and the substrate or pad electrode.

본 발명의 한 실시형태에 따른 반도체장치의 제조방법은 제 1 개구부와 제 1 개구부보다 직경이 작은 제 2 개구부가 스루홀로서 형성되어 있으므로, 스루홀 안으로 채워진 도전층과 기판이나 패드 전극 사이에서 열팽창계수의 차이로 인하여 발생되는 크랙이나 필링을 막을 수 있게 된다.In the method of manufacturing a semiconductor device according to one embodiment of the present invention, since the first opening and the second opening having a smaller diameter than the first opening are formed as through holes, thermal expansion between the conductive layer filled into the through holes and the substrate or pad electrode is performed. It is possible to prevent cracks or peeling caused by the difference in coefficients.

본 발명의 각 실시형태에 따른 반도체장치에 의하면, 이하의 유리한 효과가 얻어질 수 있다.According to the semiconductor device according to each embodiment of the present invention, the following advantageous effects can be obtained.

상술된 바와 같이, 본 실시형태들의 반도체장치에서는, 패드 전극을 접촉하는 개구부(제 2 개구부)의 직경이 작게 될 경우, 개구부에 형성되는 도전층의 열팽창의 영향이 감소될 수 있다. 결과적으로 고신뢰성이 달성될 수 있다.As described above, in the semiconductor device of the present embodiments, when the diameter of the opening (second opening) in contact with the pad electrode becomes small, the influence of thermal expansion of the conductive layer formed in the opening can be reduced. As a result, high reliability can be achieved.

보다 직경이 큰 제 1 개구부가 패드 전극을 접촉하는 부분을 제외하고 형성되며, 결과적으로 스루홀 형성의 TAT가 짧아질 수 있고, 두꺼운 웨이퍼에서도 적용 될 수 있다. 따라서 핸들링성(handling ability)의 향상도 또한 달성될 수 있다.A larger diameter first opening is formed except for the part in contact with the pad electrode, and as a result, the TAT of the through hole formation can be shortened and can be applied to a thick wafer. Thus, an improvement in handling ability can also be achieved.

또, 패드 전극은 직경이 보다 작은 제 2 개구부에 의해 접촉되므로, 스루홀과 패드 전극의 위치 맞춤(얼라인먼트)의 자유도가 개선된다. 결과적으로, 스루홀은 반도체 웨이퍼의 검사 시에 프로브에 의한 자국을 피하도록 형성될 수 있으며, 그것에 의해 스루홀의 수율이 향상될 수 있다.In addition, since the pad electrode is contacted by the second opening having a smaller diameter, the degree of freedom of alignment (alignment) of the through hole and the pad electrode is improved. As a result, the through holes can be formed to avoid marks by the probes during the inspection of the semiconductor wafer, whereby the through hole yield can be improved.

게다가, 보다 직경이 작은 제 2 개구부가 형성될 경우, 패드 전극의 소형화도 또한 달성될 수 있다.In addition, miniaturization of the pad electrode can also be achieved when a second opening having a smaller diameter is formed.

절연층이 제 2 개구부와 비교해서 제 1 개구부의 벽 표면상에서 보다 두껍게 형성되기 때문에, 개구부의 도전층 내부와 반도체 기판의 사이에서 기생 용량이 감소될 수 있다.Since the insulating layer is formed thicker on the wall surface of the first opening as compared with the second opening, the parasitic capacitance can be reduced between the conductive layer of the opening and the semiconductor substrate.

본 발명은 상기의 설명으로 한정되지 않는다.The present invention is not limited to the above description.

예를 들면, 본 발명은 CMOS 이미지 센서와 같은 고체 촬상 장치를 공기가 통하지 않게 밀봉하여 패키지화된 반도체장치뿐만 아니라, 또 다른 전자소자가 공기가 통하지 않게 밀봉되는 반도체장치에도 적용될 수 있다.For example, the present invention can be applied not only to a semiconductor device packaged by sealing a solid-state imaging device such as a CMOS image sensor in a non-airflow manner, but also to a semiconductor device in which another electronic device is sealed in a non-airflow way.

본 발명은 전자소자가 공기가 통하지 않게 밀봉되는 방식의 반도체장치로 한정되지 않고, 기판을 관통하는 배선이 제공되는 한, 본 발명이 적용될 수 있다.The present invention is not limited to a semiconductor device in which the electronic device is sealed to prevent air from passing through, and the present invention can be applied as long as wiring is provided through the substrate.

또한, 본 발명은 본 발명의 요지를 일탈하지 않는 한, 여러 가지 방법으로 변경될 수 있다.In addition, the present invention can be modified in various ways without departing from the gist of the present invention.

본 발명의 반도체장치는, 고체 촬상 장치 등이 공기가 통하지 않게 밀봉되는 패키지 형태의 반도체장치와 같이 기판을 관통하는 배선을 가지는 반도체장치에 적용될 수 있다.The semiconductor device of the present invention can be applied to a semiconductor device having wiring through a substrate, such as a semiconductor device in a package form in which a solid-state imaging device or the like is sealed without passing through air.

본 발명의 반도체장치의 제조방법은, 고체 촬상 장치 등이 공기가 통하지 않게 밀봉되는 패키지 형태의 반도체장치와 같이 기판을 관통하는 배선을 가지는 반도체장치의 제조방법에 적용될 수 있다.The method for manufacturing a semiconductor device of the present invention can be applied to a method for manufacturing a semiconductor device having wirings through a substrate, such as a semiconductor device in a package form in which a solid-state imaging device or the like is sealed without passing through air.

본 출원은 2007년 3월 15일 일본 특허청에 출원된 일본특허공보 번호 2007-66173의 우선권과, 참조하여 여기에 반영된 전체 내용을 주장한다.This application claims the priority of Japanese Patent Publication No. 2007-66173 filed with the Japan Patent Office on March 15, 2007, and the entire contents reflected therein.

도 1a는 본 발명의 제 1 실시형태에 따른 반도체장치의 약식 단면도이며, 도 1b는 도 1a의 주요부 확대도이다.FIG. 1A is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention, and FIG. 1B is an enlarged view of an essential part of FIG. 1A.

도 2는 본 발명의 제 1 실시형태에 따른 반도체장치의 각 부분의 사이즈를 설명하기 위한 약식도이다.2 is a schematic view for explaining the size of each part of the semiconductor device according to the first embodiment of the present invention.

도 3a 및 도 3b는 본 발명의 제 1 실시형태에 따른 반도체장치의 제조방법의 제조 스텝을 각각 나타내는 단면도이다.3A and 3B are cross-sectional views each showing manufacturing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

도 4a 및 도 4b는 본 발명의 제 1 실시형태에 따른 반도체장치의 제조방법의 제조 스텝을 각각 나타내는 단면도이다.4A and 4B are cross-sectional views each showing manufacturing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

도 5a 및 도 5b는 본 발명의 제 1 실시형태에 따른 반도체장치의 제조방법의 제조 스텝을 각각 나타내는 단면도이다.5A and 5B are cross-sectional views each showing manufacturing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

도 6a 및 도 6b는 본 발명의 제 1 실시형태에 따른 반도체장치의 제조방법의 제조 스텝을 각각 나타내는 단면도이다.6A and 6B are cross-sectional views each showing manufacturing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

도 7a 및 도 7b는 본 발명의 제 1 실시형태에 따른 반도체장치의 제조방법의 제조 스텝을 각각 나타내는 단면도이다.7A and 7B are cross-sectional views each showing manufacturing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

도 8a 및 도 8b는 본 발명의 제 1 실시형태에 따른 반도체장치의 제조방법의 제조 스텝을 각각 나타내는 단면도이다.8A and 8B are cross-sectional views each showing manufacturing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

도 9a는 본 발명의 제 1 실시형태의 반도체장치의 패드 전극에 있어서 프로브에 의한 자국과 제 2 개구부의 개구 영역을 나타내는 레이아웃차트이며, 도 9b는 패드 전극에 대한 제 1 개구부와 제 2 개구부의 레이아웃차트이다.Fig. 9A is a layout chart showing the openings of the marks and the openings of the second openings in the pad electrode of the semiconductor device according to the first embodiment of the present invention. Layout chart.

도 10은 본 발명의 제 2 실시형태에 따른 반도체장치의 약식 단면도이다.10 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10 : 반도체 기판, 11 : 고체 촬상 센서10 semiconductor substrate, 11 solid-state imaging sensor

12 : 패드 전극, 13 : 밀봉 수지층12 pad electrode, 13 sealing resin layer

14 : 패키지 기판, 20 : 절연층14: package substrate, 20: insulating layer

21 : 도전층, 22 : 솔더레지스트막21: conductive layer, 22: solder resist film

23 : 범프, 30 : 메모리 기판23 bump, 30 memory board

31 : 배선, H1 : 제 1 개구부31: wiring, H1: first opening

H2 : 제 2 개구부, P : 패드 전극H2: second opening, P: pad electrode

T : 프로브에 의한 자국T: mark by probe

Claims (12)

반도체장치에 있어서,In a semiconductor device, 전자소자가 제공된 액티브 표면인 제 1 표면과 서로 반대편의 제 2 표면을 가지는 반도체 기판과,A semiconductor substrate having a first surface which is an active surface provided with an electronic element and a second surface opposite to each other; 상기 액티브 표면상의 상기 전자소자의 주변부에서 상기 전자소자에 접속되도록 형성된 패드 전극과,A pad electrode formed to be connected to the electronic device at a periphery of the electronic device on the active surface; 상기 반도체 기판의 상기 제 1 표면에 도달하지 않도록 상기 반도체 기판의 상기 제 2 표면으로부터 상기 패드 전극을 향하여 연장하는 제 1 개구부와,A first opening extending toward the pad electrode from the second surface of the semiconductor substrate so as not to reach the first surface of the semiconductor substrate; 상기 제 1 개구부의 직경보다 작은 직경을 가지는, 상기 제 1 개구부의 바닥 표면으로부터 상기 패드 전극에 도달하도록 형성된 제 2 개구부와,A second opening formed to reach the pad electrode from a bottom surface of the first opening, the second opening having a diameter smaller than the diameter of the first opening; 상기 제 1 개구부 및 상기 제 2 개구부의 측벽 표면을 피복하도록 형성된 절연층과,An insulating layer formed to cover the sidewall surfaces of the first and second openings; 상기 절연층의 내부, 적어도 상기 절연층의 내벽 표면과 상기 제 2 개구부의 바닥 표면을 피복하도록 형성된 도전층으로 이루어져 있는 것을 특징으로 하는 반도체장치.And a conductive layer formed to cover the inside of the insulating layer, at least the inner wall surface of the insulating layer and the bottom surface of the second opening. 제 1항에 있어서,The method of claim 1, 상기 제 2 개구부는 상기 제 1 개구부의 직경의 0.7배 이하의 직경을 가지는 것을 특징으로 하는 반도체장치.And the second opening portion has a diameter no greater than 0.7 times the diameter of the first opening portion. 제 1항에 있어서,The method of claim 1, 상기 제 1 개구부는 상기 반도체 기판의 0.5배 이상의 깊이와 0.9배 이하의 두께를 가지는 것을 특징으로 하는 반도체장치.And the first opening has a depth of 0.5 times or more and a thickness of 0.9 times or less of the semiconductor substrate. 제 1항에 있어서,The method of claim 1, 상기 절연층은, 상기 제 1 개구부의 측벽 표면을 피복하는 부분이 상기 제 2 개구부의 측벽 표면을 피복하는 부분보다 두껍게 되도록 형성되어 있는 것을 특징으로 하는 반도체장치.And the insulating layer is formed such that a portion covering the sidewall surface of the first opening portion is thicker than a portion covering the sidewall surface of the second opening portion. 제 1항에 있어서,The method of claim 1, 상기 반도체 기판의 상기 액티브 표면에 대향된 패키지 기판과,A package substrate facing the active surface of the semiconductor substrate; 상기 전자소자를 공기가 통하지 않게 밀봉하도록 상기 반도체 기판상의 전자소자의 주변부와 상기 패키지 기판 사이의 간극에 형성된 밀봉 수지층으로 더 이루어져 있는 것을 특징으로 하는 반도체장치.And a sealing resin layer formed in the gap between the periphery of the electronic device on the semiconductor substrate and the package substrate so as to seal the electronic device through the air. 제 1항에 있어서,The method of claim 1, 상기 전자소자는 고체 촬상 센서인 것을 특징으로 하는 반도체장치.And said electronic device is a solid-state imaging sensor. 반도체장치의 제조방법에 있어서,In the method of manufacturing a semiconductor device, 서로 반대편의 제 1 및 제 2 표면을 가지는 반도체 기판을 제공하는 스텝과,Providing a semiconductor substrate having first and second surfaces opposite each other, 상기 반도체 기판의 액티브 표면인 상기 제 1 표면상에서 전자소자를 형성하고 상기 액티브 표면상에서 상기 전자소자의 주변부에서 상기 전자소자에 접속되도록 패드 전극을 형성하는 스텝과,Forming an electronic device on the first surface which is an active surface of the semiconductor substrate and forming a pad electrode to be connected to the electronic device at the periphery of the electronic device on the active surface; 상기 반도체 기판의 상기 제 1 표면에 도달하지 않도록 상기 반도체 기판의 상기 제 2 표면으로부터 상기 패드 전극을 향하여 연장하는 제 1 개구부를 형성하는 스텝과,Forming a first opening extending from the second surface of the semiconductor substrate toward the pad electrode so as not to reach the first surface of the semiconductor substrate; 상기 제 1 개구부의 바닥 표면으로부터 상기 패드 전극에 도달하도록 상기 제 1 개구부의 직경보다 작은 직경을 가지는 제 2 개구부를 형성하는 스텝과,Forming a second opening having a diameter smaller than the diameter of the first opening so as to reach the pad electrode from the bottom surface of the first opening; 절연층을 형성하기 위하여 상기 제 1 개구부 및 상기 제 2 개구부의 측벽 표면을 피복하는 스텝과,Covering the sidewall surfaces of the first and second openings to form an insulating layer, 도전층을 형성하기 위하여 상기 절연층의 내부, 적어도 상기 절연층의 내벽 표면과 상기 제 2 개구부의 바닥 표면을 피복하는 스텝으로 이루어져 있는 것을 특징으로 하는 반도체장치의 제조방법.A method of manufacturing a semiconductor device, comprising the steps of covering an inner surface of the insulating layer, at least an inner wall surface of the insulating layer, and a bottom surface of the second opening to form a conductive layer. 제 7항에 있어서,The method of claim 7, wherein 상기 제 2 개구부는 상기 제 1 개구부의 직경의 0.7배 이하의 직경을 갖도록 형성되어 있는 것을 특징으로 하는 반도체장치의 제조방법.And the second opening portion is formed to have a diameter no greater than 0.7 times the diameter of the first opening portion. 제 7항에 있어서,The method of claim 7, wherein 상기 제 1 개구부는 상기 반도체 기판의 0.5배 이상의 깊이와 0.9배 이하의 두께를 갖도록 형성되어 있는 것을 특징으로 하는 반도체장치의 제조방법.And the first opening is formed to have a depth of 0.5 times or more and a thickness of 0.9 times or less of the semiconductor substrate. 제 7항에 있어서,The method of claim 7, wherein 상기 절연층은, 상기 제 1 개구부의 측벽 표면을 피복하는 부분이 상기 제 2 개구부의 측벽 표면을 피복하는 부분보다 두껍게 되도록 형성되어 있는 것을 특징으로 하는 반도체장치의 제조방법.And the insulating layer is formed such that a portion covering the sidewall surface of the first opening portion is thicker than a portion covering the sidewall surface of the second opening portion. 제 7항에 있어서,The method of claim 7, wherein 상기 반도체 기판상의 상기 전자소자의 주변부에 밀봉 수지층을 형성하는 스텝과,Forming a sealing resin layer on a periphery of said electronic element on said semiconductor substrate; 상기 반도체 기판의 상기 액티브 표면에 대향된 상기 밀봉 수지층상에서 패키지 기판을 배치하고, 상기 패키지 기판 및 상기 밀봉 수지층에 의해 상기 전자소자를 공기가 통하지 않게 밀봉하는 스텝으로 더 이루어지는 것을 특징으로 하는 반도체장치의 제조방법.And arranging a package substrate on the sealing resin layer opposite to the active surface of the semiconductor substrate, and sealing the electronic device through the air by the package substrate and the sealing resin layer. Method of manufacturing the device. 제 7항에 있어서,The method of claim 7, wherein 상기 전자소자는 고체 촬상 센서인 것을 특징으로 하는 반도체장치의 제조방법.And the electronic device is a solid-state image sensor.
KR1020080009042A 2007-03-15 2008-01-29 Semiconductor device and method of manufacturing the same KR101463895B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007066173A JP4380718B2 (en) 2007-03-15 2007-03-15 Manufacturing method of semiconductor device
JPJP-P-2007-00066173 2007-03-15

Publications (2)

Publication Number Publication Date
KR20080084572A true KR20080084572A (en) 2008-09-19
KR101463895B1 KR101463895B1 (en) 2014-11-20

Family

ID=39761794

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080009042A KR101463895B1 (en) 2007-03-15 2008-01-29 Semiconductor device and method of manufacturing the same

Country Status (5)

Country Link
US (7) US8252628B2 (en)
JP (1) JP4380718B2 (en)
KR (1) KR101463895B1 (en)
CN (1) CN101266991B (en)
TW (1) TWI360850B (en)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6995462B2 (en) * 2003-09-17 2006-02-07 Micron Technology, Inc. Image sensor packages
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US8405196B2 (en) 2007-03-05 2013-03-26 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
JP4380718B2 (en) * 2007-03-15 2009-12-09 ソニー株式会社 Manufacturing method of semiconductor device
JP4937842B2 (en) * 2007-06-06 2012-05-23 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
KR101538648B1 (en) * 2007-07-31 2015-07-22 인벤사스 코포레이션 Semiconductor packaging process using through silicon vias
JP4713602B2 (en) * 2008-02-21 2011-06-29 パナソニック株式会社 Substrate module, method for manufacturing the same, and electronic device
JP5175620B2 (en) * 2008-05-29 2013-04-03 シャープ株式会社 Electronic element wafer module and manufacturing method thereof, electronic element module, and electronic information device
JP5455538B2 (en) * 2008-10-21 2014-03-26 キヤノン株式会社 Semiconductor device and manufacturing method thereof
JP2010177569A (en) * 2009-01-30 2010-08-12 Panasonic Corp Optical device and method of manufacturing the same
JP2010206158A (en) 2009-02-04 2010-09-16 Panasonic Corp Device
JP2010210590A (en) * 2009-03-12 2010-09-24 Fujifilm Corp Radiation detector
US8471289B2 (en) * 2009-12-28 2013-06-25 Sanyo Electric Co., Ltd. Semiconductor laser device, optical pickup device and semiconductor device
TWI515930B (en) * 2010-05-31 2016-01-01 精材科技股份有限公司 Light-emitting diode submount, light-emitting diode package and fabrication method thereof
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
JP5619542B2 (en) * 2010-09-08 2014-11-05 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Semiconductor substrate processing method and semiconductor device manufacturing method
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
JP5568451B2 (en) * 2010-11-26 2014-08-06 株式会社フジクラ Semiconductor package
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8872293B2 (en) * 2011-02-15 2014-10-28 Sony Corporation Solid-state imaging device and method of manufacturing the same and electronic apparatus
CN103050450B (en) * 2012-11-14 2015-10-28 日月光半导体制造股份有限公司 Chip encapsulation construction and manufacture method thereof
US9379041B2 (en) 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
US9524917B2 (en) * 2014-04-23 2016-12-20 Optiz, Inc. Chip level heat dissipation using silicon
JP6260871B2 (en) * 2014-06-27 2018-01-17 パナソニックＩｐマネジメント株式会社 PREPARATE PARTS SET, PREPARATE, PREPARATE MANUFACTURING METHOD, IMAGE CAPTURE DEVICE, AND IMAGE CAPTURE METHOD
TWI621229B (en) * 2015-04-27 2018-04-11 精材科技股份有限公司 Chip package and manufacturing method thereof
TWI692859B (en) 2015-05-15 2020-05-01 日商新力股份有限公司 Solid-state imaging device, manufacturing method thereof, and electronic device
WO2018067136A1 (en) * 2016-10-05 2018-04-12 Hewlett-Packard Development Company, L.P. Insulated sensors
JP6808460B2 (en) 2016-11-29 2021-01-06 キヤノン株式会社 Semiconductor devices and their manufacturing methods
JP6791584B2 (en) * 2017-02-01 2020-11-25 株式会社ディスコ Processing method
CN109087897A (en) * 2017-06-13 2018-12-25 精材科技股份有限公司 Wafer encapsulation body and preparation method thereof
CN107230684B (en) * 2017-06-28 2019-07-30 华进半导体封装先导技术研发中心有限公司 The encapsulating structure and its manufacturing method of wafer scale image sensing chip
CN110112109A (en) * 2019-05-30 2019-08-09 苏州多感科技有限公司 A kind of encapsulation chip, chip module and terminal
US11605576B2 (en) * 2019-06-25 2023-03-14 Semiconductor Components Industries, Llc Via for semiconductor devices and related methods
US11824126B2 (en) * 2019-12-10 2023-11-21 Maxeon Solar Pte. Ltd. Aligned metallization for solar cells
CN113539946B (en) * 2020-04-16 2023-07-07 长鑫存储技术有限公司 Semiconductor structure and forming method thereof

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
JP3724110B2 (en) 1997-04-24 2005-12-07 三菱電機株式会社 Manufacturing method of semiconductor device
JP3879816B2 (en) * 2000-06-02 2007-02-14 セイコーエプソン株式会社 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD, LAMINATED SEMICONDUCTOR DEVICE, CIRCUIT BOARD AND ELECTRONIC DEVICE
JP2002217197A (en) 2001-01-18 2002-08-02 Sony Corp Semiconductor device
JP2002270718A (en) * 2001-03-07 2002-09-20 Seiko Epson Corp Wiring board and its manufacturing method, semiconductor device and its manufacturing method, and circuit board and electronic apparatus
JP2004014657A (en) 2002-06-05 2004-01-15 Toshiba Corp Semiconductor chip and its manufacturing method, and three-dimensional laminated semiconductor device
EP1527480A2 (en) * 2002-08-09 2005-05-04 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
US7180149B2 (en) * 2003-08-28 2007-02-20 Fujikura Ltd. Semiconductor package with through-hole
JP4850392B2 (en) 2004-02-17 2012-01-11 三洋電機株式会社 Manufacturing method of semiconductor device
JP4327644B2 (en) 2004-03-31 2009-09-09 Ｎｅｃエレクトロニクス株式会社 Manufacturing method of semiconductor device
US7417293B2 (en) * 2004-04-27 2008-08-26 Industrial Technology Research Institute Image sensor packaging structure
JP4376715B2 (en) * 2004-07-16 2009-12-02 三洋電機株式会社 Manufacturing method of semiconductor device
US8217396B2 (en) * 2004-07-30 2012-07-10 Semiconductor Energy Laboratory Co., Ltd. Display device comprising electrode layer contacting wiring in the connection region and extending to pixel region
US7598167B2 (en) * 2004-08-24 2009-10-06 Micron Technology, Inc. Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures
US7109068B2 (en) * 2004-08-31 2006-09-19 Micron Technology, Inc. Through-substrate interconnect fabrication methods
US7459406B2 (en) * 2004-09-01 2008-12-02 Semiconductor Energy Laboratory Co., Ltd. Laser processing unit, laser processing method, and method for manufacturing semiconductor device
US8350466B2 (en) * 2004-09-17 2013-01-08 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
TWI313914B (en) * 2005-01-31 2009-08-21 Sanyo Electric Co Semiconductor device and a method for manufacturing thereof
US7566971B2 (en) * 2005-05-27 2009-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7485511B2 (en) * 2005-06-01 2009-02-03 Semiconductor Energy Laboratory Co., Ltd. Integrated circuit device and method for manufacturing integrated circuit device
US8101868B2 (en) * 2005-10-14 2012-01-24 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
JP4463194B2 (en) 2005-12-27 2010-05-12 ソニー株式会社 Solid-state imaging device and method for manufacturing solid-state imaging device
EP2038684B1 (en) * 2006-05-31 2016-03-16 Semiconductor Energy Laboratory Co., Ltd. Display device
US7781768B2 (en) * 2006-06-29 2010-08-24 Semiconductor Energy Laboratory Co., Ltd. Display device, method for manufacturing the same, and electronic device having the same
WO2008069162A1 (en) * 2006-12-05 2008-06-12 Semiconductor Energy Laboratory Co., Ltd. Anti-reflection film and display device
WO2008069164A1 (en) * 2006-12-05 2008-06-12 Semiconductor Energy Laboratory Co., Ltd. Antireflection film and display device
WO2008069223A1 (en) * 2006-12-05 2008-06-12 Semiconductor Energy Laboratory Co., Ltd. Anti-reflection film and display device
US8405196B2 (en) * 2007-03-05 2013-03-26 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
JP4380718B2 (en) 2007-03-15 2009-12-09 ソニー株式会社 Manufacturing method of semiconductor device
US8105458B2 (en) * 2007-03-23 2012-01-31 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing liquid crystal display device
US8591694B2 (en) * 2007-03-23 2013-11-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing liquid crystal display device
US20080284041A1 (en) * 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
JP6215577B2 (en) 2013-05-31 2017-10-18 株式会社ヨコオ Semiconductor package container, semiconductor device, electronic equipment

Also Published As

Publication number Publication date
US20160276385A1 (en) 2016-09-22
US9379155B2 (en) 2016-06-28
CN101266991B (en) 2011-08-31
US20140183680A1 (en) 2014-07-03
US9041179B2 (en) 2015-05-26
US11676977B2 (en) 2023-06-13
US8252628B2 (en) 2012-08-28
JP2008227335A (en) 2008-09-25
US20120286387A1 (en) 2012-11-15
US20080224249A1 (en) 2008-09-18
US10050074B2 (en) 2018-08-14
JP4380718B2 (en) 2009-12-09
US20220231061A1 (en) 2022-07-21
CN101266991A (en) 2008-09-17
US20190043905A1 (en) 2019-02-07
KR101463895B1 (en) 2014-11-20
TWI360850B (en) 2012-03-21
US11315970B2 (en) 2022-04-26
TW200837845A (en) 2008-09-16
US20150221690A1 (en) 2015-08-06

Similar Documents

Publication Publication Date Title
KR101463895B1 (en) Semiconductor device and method of manufacturing the same
KR101478524B1 (en) Semiconductor device and method for manufacturing the same
TWI525758B (en) Chip package and fabrication method thereof
KR101531097B1 (en) Interposer substrate and method of manufacturing the same
KR100659625B1 (en) Semiconductor device and method for manufacturing the same
US20120108055A1 (en) Manufacturing process of semiconductor device and semiconductor device
US7830017B2 (en) Wafer level chip scale package, method of manufacturing the same, and semiconductor chip module including the wafer level chip scale package
KR20080074773A (en) Image sensor package with die receiving opening and method of the same
JP2007157844A (en) Semiconductor device, and method of manufacturing same
US8178977B2 (en) Semiconductor device and method of manufacturing the same
US20100207271A1 (en) Semiconductor device
JP2003338518A (en) Bump of semiconductor chip and method of manufacturing the same
JP3618212B2 (en) Semiconductor device and manufacturing method thereof
JP4264823B2 (en) Manufacturing method of semiconductor device
CN215869349U (en) Wafer level chip scale package device with sensor
JP2008153696A (en) Semiconductor package and manufacturing method therefor
US11444014B2 (en) Semiconductor packages including an insulating layer including a recessed surface and methods of manufacturing the same
JP4188752B2 (en) Semiconductor package and manufacturing method thereof
US11682648B2 (en) Semiconductor device and method of fabricating the same
US8372691B2 (en) Method of manufacturing semiconductor device
KR20090022783A (en) Printed circuit board used semiconductor package and method for fabricating of the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20171103

Year of fee payment: 4