KR20080079738A - Semiconductor device and method for forming the same - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device, the method comprising: forming a first insulating film on a semiconductor substrate, etching the first insulating film to expose the semiconductor substrate, and forming the first insulating film pattern; Forming a first silicon layer between the first insulating film patterns, forming a second insulating film pattern on the first insulating film pattern, reducing an upper width of the second insulating film pattern, and forming the second insulating film Since the second silicon film is formed between the patterns, the leakage current may be reduced by increasing the length of the channel formed between the memory cells.

Description

Semiconductor device and method for forming the same

1A to 1H are cross-sectional views of a device illustrated to explain a method of manufacturing a semiconductor device according to the present invention.

<Description of the symbols for the main parts of the drawings>

102 semiconductor substrate 104 first insulating film

106: first antireflection film 108: first mask pattern

110: first silicon layer 112: second insulating film

114: second antireflection film 116: second mask pattern

118 device isolation layer 120 second silicon layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of reducing leakage current while securing a sufficient channel length.

Recently, due to the high integration of semiconductor devices, as the design rules of the devices become smaller, the manufacturing process of the semiconductor devices has been gradually refined and refined. As a result, the size of the semiconductor device to be formed is also miniaturized, and it is emerging as an important issue to form a fine device isolation region and an active region in the semiconductor substrate.

In general, a trench is formed in a semiconductor substrate in a device isolation region, and a trench is filled with an insulating material to form a device isolation film. However, as the size of the semiconductor device becomes smaller, problems such as voids may occur when the width of the trench is reduced to fill the trench with an insulating material. In addition, as the active region is gradually reduced and the distance between the active regions is closer, the amount of leakage current generated between the active regions increases, which may adversely affect the performance of the semiconductor device.

According to the present invention, a plurality of damascene processes are performed to form an insulating film recessed in a semiconductor substrate, so that an isolation layer can be formed more easily than a buried insulating material formed in a trench. The leakage current can be reduced by increasing the length of the channel.

A method of manufacturing a semiconductor device according to the present invention may include forming a first insulating film on a semiconductor substrate, etching the first insulating film to expose the semiconductor substrate, and forming the first insulating film pattern. Forming a first silicon layer between the first insulating film pattern, forming a second insulating film pattern on the first insulating film pattern, reducing an upper width of the second insulating film pattern, and forming the second insulating film Forming a second silicon film between the patterns.

In order to reduce the width of the second insulating layer pattern, a thermal process may be performed. The second insulating layer may be formed of a BPSG (Boro Phospho Silicate Glass) film or a SOG (Spin On Glass) film. The first silicon film and the second silicon film may be formed using a selective epitaxial growth method. After forming the first silicon layer, the method may further include performing a planarization process on the first silicon layer. After forming the second silicon layer, the method may further include performing a planarization process on the second silicon layer.

On the other hand, the semiconductor device according to the present invention may include a semiconductor substrate, an element isolation film formed inside the semiconductor substrate and a narrow upper width, and an active region defined by the device isolation film.

The semiconductor substrate and the device isolation layer may be formed by a damascene process.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1A to 1H are cross-sectional views of a device illustrated to explain a method of manufacturing a semiconductor device according to the present invention. In particular, FIGS. 1A-1H are cross-sectional views of devices around the active region of a semiconductor substrate.

Referring to FIG. 1A, a first insulating layer 104 is formed on a semiconductor substrate 102 formed of silicon having a single crystal structure. The first insulating film 104 is preferably formed of an oxide film. The first antireflection film 106 is formed over the entire structure of the semiconductor substrate 102 including the first insulating film 104. Afterwards, in order to perform the damascene process, the first mask pattern 108 is first formed on the first anti-reflection film 106.

Referring to FIG. 1B, an etching process using the first mask pattern 108 (see FIG. 1A) as an etching mask may be performed to form the first anti-reflection film 106 (see FIG. 1A) and the first insulating layer 104 in the isolation region. Pattern. On the other hand, the first insulating film 104 is preferably patterned in a wider width than the device isolation region is formed over the device isolation region and the active region around it. Next, the first mask pattern 108 and the first antireflection film 106 are removed.

Referring to FIG. 1C, the first silicon layer 110 is formed on the entire structure of the semiconductor substrate 102 including the first insulating layer 104. The first silicon layer 110 may be formed on the semiconductor substrate 102 by a selective epitaxial growth (SEG) method. When the first silicon layer 110 is formed by a selective epitaxial growth method, the first silicon layer 110 is formed to have the same lattice as the semiconductor substrate 102, and thus the first silicon layer 110 is formed of a semiconductor substrate. Since it has the same characteristics as the 102, it can be formed integrally with the semiconductor substrate 102. Meanwhile, the first silicon layer 110 is formed by sufficiently growing the semiconductor substrate 102 so as to be formed thicker than the height of the first insulating layer 104.

Referring to FIG. 1D, the first silicon layer 110 formed on the first insulating layer 104 may be formed by performing a planarization process such as chemical mechanical polishing (CMP) on the first silicon layer 110. Remove and flatten.

Referring to FIG. 1E, a second insulating layer 112 is formed on the first insulating layer 104 and the first silicon layer 110. The second insulating layer 112 is formed of an oxide film, and in particular, it is preferable to form a shrinkable material, for example, a BOSG (Boro Phospho Silicate Glass) film or a SOG (Spin On Glass) film. Thereafter, in order to perform the damascene process, first, a second anti-reflection film 114 and a second mask pattern 116 are formed on the second insulating film 112. The second mask pattern 116 is preferably formed at a position corresponding to the first insulating film 104 formed in the above-described process.

Referring to FIG. 1F, an etching process using the second mask pattern 116 (see FIG. 1E) as an etching mask is performed to form the second anti-reflection film 114 (see FIG. 1E) and the second insulating layer 112 in the isolation region. Pattern. On the other hand, the second insulating film 112 is preferably patterned in a wider width than the device isolation region, and is formed over the device isolation region and the active region around it. As a result, the second insulating film 112 and the first insulating film 104 integrally form the device isolation film 118. Thereafter, the second mask pattern 116 and the second anti-reflection film 114 are removed.

Referring to FIG. 1G, a heat treatment process is performed on the device isolation layer 118 to shrink the upper part 112 of the exposed device isolation layer 118. As a result, the width between the upper portions 112 of the device isolation layer 118 becomes wider, and the device isolation layer 118 is formed in the form of iron with a protruding upper portion.

Referring to FIG. 1H, the second silicon layer 120 is formed on the entire structure including the device isolation layer 118. The second silicon layer 120 is preferably formed by a selective epitaxial growth method. When the second silicon layer 120 is formed by the selective epitaxial growth method, the second silicon layer 120 is formed to have the same lattice as the first silicon layer 110 and the semiconductor substrate 102. Accordingly, the second silicon layer 120 may have the same characteristics as the first silicon layer 110 and the semiconductor substrate 102, and thus may be integrally formed with the semiconductor substrate 102. Meanwhile, the second silicon layer 102 is formed by sufficiently growing the first silicon layer 110 and the semiconductor substrate 102 so as to be formed thicker than the height of the second insulating layer 112.

Thereafter, a planarization process such as a chemical mechanical polishing method is performed on the second silicon layer 120 to remove and planarize the second silicon layer 120 formed on the insulating layer 118. As a result, an element isolation layer 118 having a recessed shape having an upper width narrower than the lower width is formed in the active region of the semiconductor substrate 102 to form a separate field stop ion implant. There is no need to increase the length of the channel formed along the device isolation layer 118 between the memory cells. In addition, even if the distance between the second silicon layer 120 is narrow, the device isolation layer 118 is formed before the second silicon layer 120, the second silicon layer 120 is formed between the protrusions 112 of the device isolation layer. As a result, voids that may be generated when the device isolation layer 118 is buried are not formed.

Thereafter, although not shown in the figure, a gate is formed on the second silicon film 120 to form a semiconductor device.

According to the method of manufacturing a semiconductor device of the present invention, since the device isolation film is formed in the active region of the semiconductor substrate by performing a plurality of damascene processes, voids can be prevented as compared with forming the device isolation film by embedding an insulating material in the trench. Can be. In addition, since the device isolation layer is formed in a recessed shape, the length of the channel formed between the memory cells may be increased to reduce leakage current and to improve refresh characteristics in the DRAM.

Claims (9)

Forming a first insulating film on the semiconductor substrate; Etching the first insulating film to expose the semiconductor substrate to form the first insulating film pattern; Forming a first silicon layer between the first insulating layer patterns; Forming a second insulating film pattern on the first insulating film pattern; Reducing an upper width of the second insulating layer pattern; And Forming a second silicon film between the second insulating film patterns. The method of claim 1, And a thermal process to reduce the width of the second insulating film pattern. The method of claim 1, The second insulating film is a semiconductor device manufacturing method of forming a BPSG (Boro Phospho Silicate Glass) film or a spin on glass (SOG) film. The method of claim 1, And the first silicon film and the second silicon film are formed using a selective epitaxial growth method. The method of claim 1, And forming a planarization process on the first silicon layer after forming the first silicon layer. The method of claim 1, And forming a planarization process on the second silicon layer after forming the second silicon layer. Semiconductor substrates; An isolation layer formed over the semiconductor substrate and having a narrow upper width; And an active region formed between the device isolation films on the semiconductor substrate. The method of claim 7, wherein The device isolation layer is a semiconductor device formed of a BPSG (Boro Phospho Silicate Glass) film or a spin on glass (SOG) film. The method of claim 7, wherein The active region is formed using a selective epitaxial growth method.

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