CN104517889B - The forming method of isolation structure - Google Patents
The forming method of isolation structure Download PDFInfo
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- CN104517889B CN104517889B CN201310462446.1A CN201310462446A CN104517889B CN 104517889 B CN104517889 B CN 104517889B CN 201310462446 A CN201310462446 A CN 201310462446A CN 104517889 B CN104517889 B CN 104517889B
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000002955 isolation Methods 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 84
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 18
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 239000007789 gas Substances 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 229910052786 argon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 239000011261 inert gas Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 4
- 238000007669 thermal treatment Methods 0.000 claims description 4
- 239000008246 gaseous mixture Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 239000012212 insulator Substances 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 238000010276 construction Methods 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- -1 oxonium ion Chemical class 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910003978 SiClx Inorganic materials 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Element Separation (AREA)
Abstract
A kind of forming method of isolation structure, including：Substrate is provided；O +ion implanted is carried out, to form doped region in the position of substrate distance substrate surface certain depth；After carrying out O +ion implanted, groove is formed in substrate；It is formed after groove, is heat-treated to form buries oxide layer in doping zone position, groove exposes buries oxide layer；Form the insulating layer of covering groove bottom and side wall.Buries oxide layer is formed in the position of substrate distance surface certain depth by O +ion implanted method, compared with the forming method of existing isolation structure, this method is more simple.In addition, since the buries oxide layer in isolation structure is to be formed using O +ion implanted method rather than served as using the insulating layer in silicon-on-insulator substrate, it is thus possible to reduce the manufacture cost of isolation structure.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of forming method of isolation structure.
Background technology
Isolation structure is used to the two neighboring active area on substrate being electrically isolated.Analog circuit is formed in the active area of substrate
（Analog Circuit）When, in order to which analog circuit is made to obtain preferable interference free performance, the isolation structure is in addition to including ditch
Except recess isolating structure, further include：Buries oxide layer with a certain distance from substrate surface（Buried Oxide）, the buries oxide layer with
Groove isolation construction forms the isolation structure of closing.
A kind of forming method of existing isolation structure includes：As shown in Figure 1, providing substrate 1, substrate 1 is using on insulator
Silicon substrate（Silicon On Insulation）, including bottom silicon layer 11, top silicon layer 13 and positioned at bottom silicon layer 11 and top
Insulating layer 12 between portion's silicon layer 13, insulating layer 12 are used as buries oxide layer；Bottom is formed in top silicon layer 13 and extends to insulation
The groove isolation construction 2 of layer 12.
In above-mentioned isolation structure forming method, buries oxide layer is served as by the insulating layer in silicon-on-insulator substrate, by
It is higher in the cost of silicon-on-insulator substrate, cause to increase the manufacture cost of isolation structure.
The forming method of existing another kind isolation structure includes：Buries oxide layer, then the shape in substrate are first formed in substrate
Into groove isolation construction.Wherein, the forming method of the buries oxide layer includes：
As shown in Fig. 2, providing monocrystalline substrate 3, silica is formed on 3 surface of monocrystalline substrate using thermal oxidation technology
Layer and the polycrystalline silicon seed layer on silicon oxide layer, are patterned the polycrystalline silicon seed layer and silicon oxide layer, in list
3 surface of crystalline silicon substrate forms island stacked structure 4, and island stacked structure 4 includes silicon oxide layer 41 and polycrystalline silicon seed layer 42,
Silicon oxide layer 41 is used as the buries oxide layer.
As shown in figure 3, epitaxial growth is carried out, to form epitaxial layer in monocrystalline substrate 3 and island stacked structure 4,
In, the epitaxial layer for being covered in 3 surface of monocrystalline substrate is single-crystal Si epitaxial layers 5, is covered in the extension on 4 surface of island stacked structure
Layer is polysilicon epitaxial layer 6.Then, cap 7 is formed in single-crystal Si epitaxial layers 5 and polysilicon epitaxial layer 6.
As shown in figure 4, carry out rapid thermal treatment（Rapid Thermal Process, abbreviation RTP）, make polycrystalline silicon seed
Layer 42 and polysilicon epitaxial layer 6（As shown in Figure 3）Fusing（Monocrystalline substrate 3 and single-crystal Si epitaxial layers 5 are still in solid at this time
State）, rapid thermal treatment is later as temperature is gradually reduced, polycrystalline silicon seed layer 42 and polysilicon epitaxial layer 6（Such as Fig. 3 institutes
Show）It recrystallizes, its material is made to become monocrystalline silicon from polysilicon, to form monocrystalline silicon layer 8.Therefore, single-crystal Si epitaxial layers 5,
The material identical of monocrystalline silicon layer 8 and monocrystalline substrate 3, three collectively form substrate, as buries oxide layer silicon oxide layer 41 from
The substrate surface has certain distance.
As shown in figure 5, chemical mechanical grinding is carried out, to remove cap 7（As shown in Figure 4）.
In above-mentioned isolation structure forming method, the forming method of buries oxide layer is complex.
Invention content
The problem to be solved in the present invention is：Buries oxide layer is formed in the existing method that closing isolation structure is formed in substrate
Method is complex, cost is higher.
To solve the above problems, the present invention provides a kind of forming method of isolation structure, including：
Substrate is provided；
O +ion implanted is carried out, to form doped region in the position of the substrate distance substrate surface certain depth；
After carrying out the O +ion implanted, groove is formed in the substrate；
It is formed after the groove, is heat-treated to form buries oxide layer, the groove dew in the doping zone position
Go out the buries oxide layer.
Optionally, the technological parameter of the O +ion implanted includes：O +ion implanted dosage is 1 × 1017atom/cm3To 5
×1018atom/cm3, O +ion implanted energy is 100Kev to 2.5Mev.
Optionally, the heat treatment is carried out in oxygenous atmosphere, to form the same of the buries oxide layer
When, it is formed and covers the channel bottom and side wall, the insulating layer that material is silica.
Optionally, the oxygenous atmosphere further includes hydrogen.
Optionally, the oxygenous gas further includes inert gas.
Optionally, mixed gas of the inert gas for nitrogen and argon gas.
Optionally, the process of thermal treatment parameter includes：Temperature be 900 DEG C to 1300 DEG C, the time for 30min extremely
800min, the flow of oxygen are 1slm to 20slm, and the flow of hydrogen is 0.1slm to 10slm, the flow of nitrogen for 0.1slm extremely
20slm, the flow of argon gas is 0.1slm to 20slm.
Optionally, it further includes：The filled layer being located on the insulating layer is formed, the filled layer is by the trench fill
It is full.
Optionally, the material of the filled layer is silica, silicon nitride or polysilicon.
Optionally, it further includes：It is formed the full insulating layer of the trench fill.
Optionally, the forming method of the doped region includes：
Mask layer is formed over the substrate, and the mask layer has the opening for exposing substrate；
O +ion implanted is carried out by mask of the mask layer, to form the doping in the substrate below the opening
Area；
It is formed after the doped region, removes the mask layer.
Compared with prior art, technical scheme of the present invention has the following advantages：
Buries oxide layer is formed in the position of substrate distance surface certain depth by O +ion implanted method, is isolated with existing
The forming method of structure is compared, and this method is more simple.In addition, since the buries oxide layer in isolation structure is noted using oxonium ion
Enter method to be formed rather than served as using the insulating layer in silicon-on-insulator substrate, it is thus possible to reduce the system of isolation structure
Cause this.
Further, in the step of heat treatment is to form buries oxide layer is carried out, the groove in substrate can discharge
The stress generated in heat treatment step.
Description of the drawings
Fig. 1 is a kind of cross-sectional view of existing isolation structure；
Fig. 2 to Fig. 5 be in a kind of existing isolation structure forming method isolation structure in the cross-section structure of different production phases
Schematic diagram；
Fig. 6 to Figure 11 be in the first embodiment of the present invention substrate in the cross-sectional view of different production phases；
Figure 12 to Figure 13 be in the third embodiment of the present invention substrate in the cross-sectional view of different production phases；
Figure 14 is the cross-sectional view of substrate production phase wherein in the fourth embodiment of the present invention.
Specific embodiment
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
As shown in fig. 6, provide substrate 100.
In the present embodiment, substrate 100 is silicon substrate.In other embodiments, substrate 100 may be that other contain silicon
Substrate.
With continued reference to shown in Fig. 6, O +ion implanted is carried out, to be formed in substrate 100 apart from the position of surface certain depth
Doped region 110.
In the present embodiment, the forming method of doped region 110 includes：Mask layer 120, mask layer are formed on the substrate 100
120 have the opening 121 for exposing substrate 100；O +ion implanted is carried out for mask with mask layer 120, with below opening 121
Doped region 110 is formed in substrate 100；As shown in fig. 7, remove mask layer 120 after forming doped region 110（As shown in Figure 6）.
In a particular embodiment, mask layer 120 is photoresist layer.In other embodiments, mask layer 120 or oxygen
The laminated construction of SiClx layer and photoresist layer, photoresist layer are located above silicon oxide layer；Alternatively, mask layer 120 or nitrogen
The laminated construction of SiClx layer and photoresist layer, photoresist layer are located above silicon nitride layer；Alternatively, mask layer 120 or nitrogen
The laminated construction of SiClx layer, silicon oxide layer and photoresist layer, silicon oxide layer are located above silicon nitride layer, and photoresist layer is located at oxidation
Silicon layer.Certainly, mask layer 120 can not be confined to given embodiment, or other are suitable for use as the material of mask.
In a particular embodiment, the technological parameter of the O +ion implanted includes：O +ion implanted dosage for 1 ×
1017atom/cm3To 5 × 1018atom/cm3, O +ion implanted energy is 100Kev to 2.5Mev.
In the O +ion implanted step is carried out, substrate 100 can also be heated, to increase the work of oxonium ion
Property.In a particular embodiment, when carrying out the O +ion implanted, the temperature of substrate 100 is 400 DEG C to 600 DEG C.
As shown in figure 8, groove 130 is formed in substrate 100.
In the present embodiment, the forming method of groove 130 includes：Mask layer 140, mask layer 140 are formed on the substrate 100
With the opening for exposing substrate 100（It does not identify）；It is performed etching with mask layer 140 for mask, to form groove in substrate 100
130, the lithographic method can be dry etching.In a particular embodiment, mask layer 140 is oxide-nitride-oxide
Laminated construction.
In the present embodiment, groove 130 is located at around doped region 110, and in other words, groove 130 is on the surface of a substrate
Projection, the projection of doped region 110 on the surface of a substrate is surrounded；The bottom of groove 130 is located at 110 lower section of doped region, and
The side wall of groove 130 exposes buries oxide layer 110.
In a particular embodiment, the depth of groove 130 is 1000A to 4um.
As shown in figure 9, it is heat-treated in doped region 110（As shown in Figure 8）Position forms buries oxide layer 150.At this
In embodiment, the side wall of groove 130 exposes buries oxide layer 150.
The heat treatment has the effect that：1）The oxonium ion and substrate 100 for promoting doped region 110 chemically react,
And generate uniform buries oxide layer 150；2）To being repaiied during forming groove 130 in etching to damage caused by substrate 100
It is multiple.
In the heat treatment process is carried out, larger stress can be formed in substrate 100, due in substrate 100
It is formed with groove 130 so that generated stress can be released in the heat treatment process.
In the present embodiment, the heat treatment is carried out in the atmosphere containing inert gas, in order to more uniformly
Substrate 100 is heated.The inert gas is containing one or both of nitrogen, argon gas.
In the present embodiment, the atmosphere further includes oxygen.So, while heat treatment step, oxygen
Can be chemically reacted with substrate 100, using formed be covered in 130 bottom and side wall of groove, material as silica insulation
Layer 160, insulating layer 160 are simultaneously not filled by full groove 130.Expose buries oxide layer 150 since the side wall of groove 130 has, therefore be covered in
Insulating layer 160 on 130 side wall of groove can realize " seamless connection " with buries oxide layer 150, i.e. insulating layer 160 and buries oxide layer
150 are linked to be an entirety.
In a particular embodiment, the heat treatment is carried out in the atmosphere of oxygenous, nitrogen and argon gas, the heat
The technological parameter of processing includes：Temperature is 900 DEG C to 1300 DEG C, and the time is 30min to 800min, the flow of oxygen for 1slm extremely
20slm, the flow of nitrogen is 0.1slm to 20slm, and the flow of argon gas is 0.1slm to 20slm.
In other embodiments, the atmosphere can also include hydrogen other than including oxygen, nitrogen and argon gas
Gas, to improve the formation speed of insulating layer 160.In this case, the flow of hydrogen is 0.1slm to 10slm.
The filled layer being located on insulating layer is formed, filled layer fills up groove.
In the present embodiment, the forming method of the filled layer includes：As shown in Figure 10, it is formed and is covered in mask layer 140
Encapsulant layer 171 that is upper, being filled in groove 130；As shown in figure 11, carry out planarization process, with remove mask layer 140 and
Extra encapsulant layer 171 outside groove 130（As shown in Figure 10）, form the filled layer 170 being located on insulating layer 160, filling
Layer 170 fills groove 130 completely, and in a particular embodiment, the planarization process can be chemical mechanical grinding.
Groove 130 is filled into full insulating layer 160 and filled layer 170 forms groove isolation construction.Due to insulating layer 160 with
Buries oxide layer 150 is linked to be an entirety so that the groove isolation construction and buries oxide layer 150 form a U-shaped closing every
From structure.The U-shaped closing isolation structure can define the active area for being used to form semiconductor devices in substrate 100.
Under the action of the U-shaped closing isolation structure, the semiconductor devices positioned at the active area can be with the semiconductor device of adjacent active regions
Part is effectively electrically isolated.
In the present embodiment, the material of filled layer 170 is silica, silicon nitride or polysilicon.In other embodiments, it fills out
It fills layer 170 or other is suitable for the material of filling in the trench（The material can be conductive material or insulation material
Material）, it is not limited to the present embodiment.
Insulating layer 160 has the effect that：As transition of stress layer, the stress for preventing filled layer 170 from applying to substrate 100
It is excessive to cause substrate 100 that dislocation occurs, so that the device being formed in substrate 100 can generate leakage current under non-working condition.
Oxidation is buried it can be seen from the above, being formed by O +ion implanted method in the position of substrate distance surface certain depth
Layer, then the groove isolation construction for being linked to be an entirety with buried oxide layer is formed in substrate, you can form the isolation junction of closing
Structure.Compared with the forming method of existing isolation structure, this method is more simple.In addition, due to the buries oxide layer in isolation structure
It is to be formed using O +ion implanted method rather than served as using the insulating layer in silicon-on-insulator substrate, it is thus possible to drop
The manufacture cost of low isolation structure.
Second embodiment
Between second embodiment and first embodiment difference lies in：In a second embodiment, the heat treatment step is not
It is carried out in oxygenous atmosphere so that while buries oxide layer is formed in substrate, not in the side wall of groove and bottom
Form insulating layer.In this case, it is formed after buries oxide layer, first can form insulating layer in the side wall of groove and bottom,
Form filled layer on the insulating layer again, the insulating layer and filled layer expire trench fill, and the material of filled layer can be conduction material
Material or insulating materials；Alternatively, being formed after buries oxide layer, the insulating layer of the full groove of filling can be directly formed.
3rd embodiment
Between 3rd embodiment and first embodiment difference lies in：In the third embodiment, as shown in figure 12, in substrate
It is formed after doped region 110 in 100, the groove 130 being located above doped region 110, the bottom of groove 130 is formed in substrate 100
Expose buries oxide layer 110 in portion；Then, as shown in figure 13, the heat treatment is carried out, in doped region 110（As shown in figure 12）Institute
Buries oxide layer 150 is formed in position, and insulating layer 160 is formed in the side wall of groove 130 and bottom, the bottom of groove 130 is exposed
Buries oxide layer 150, insulating layer 160 are linked to be an entirety with buries oxide layer 150.
Fourth embodiment
Between fourth embodiment and first embodiment difference lies in：In the fourth embodiment, as shown in figure 14, doped region
The projection of groove 130 on the surface of a substrate is surrounded by 110 projection on the surface of a substrate so that 130 position of respective grooves
Doped region 110 be removed, the bottom of groove 130 is located at 110 lower section of doped region, and the side wall of groove 130 exposes doped region 110.
It should be noted that the forming method of insulating layer is not limited to above-described embodiment, it in other embodiments, can also
The insulating layer is formed using chemical vapor deposition method.
It needs it is emphasized that in above-described embodiment and attached drawing, before carrying out the heat treatment, groove has exposing to mix
Miscellaneous area so that after being heat-treated to form buries oxide layer, groove can expose buries oxide layer.In other embodiments, institute is carried out
Before stating heat treatment, groove can not also expose doped region, but should ensure that the substrate material between groove and doped region（It is not oxygen-containing
Ion）Less, so, in heat treatment process, the oxonium ion in doped region can be diffused between groove and doped region
In substrate material so that after heat treatment, the substrate material between groove and doped region can also form buries oxide layer, and then make
Buries oxide layer can be exposed by obtaining groove.
In the present invention, each embodiment uses progressive literary style, emphasis description and the difference of previous embodiment, each to implement
Same section in example is referred to previous embodiment.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (9)
1. a kind of forming method of isolation structure, which is characterized in that including：
Substrate is provided；
O +ion implanted is carried out, to form doped region in the position of the substrate distance substrate surface certain depth；
After carrying out the O +ion implanted, groove is formed in the substrate, the groove is located at around the doped region；
Wherein, the groove is located above the doped region, and, the doped region is exposed in the bottom of the groove；
It is formed after the groove, is heat-treated to form buries oxide layer in the doping zone position, the groove exposes institute
State buries oxide layer；
The heat treatment is carried out in oxygenous atmosphere, while the buries oxide layer is formed, to form covering
The channel bottom and side wall, the insulating layer that material is silica；
The oxygenous atmosphere includes hydrogen.
2. forming method according to claim 1, which is characterized in that the technological parameter of the O +ion implanted includes：Oxygen
Ion implantation dosage is 1 × 1017atom/cm3To 5 × 1018atom/cm3, O +ion implanted energy is 100Kev to 2.5Mev.
3. forming method according to claim 1, which is characterized in that the oxygenous atmosphere further includes indifferent gas
Body.
4. forming method according to claim 3, which is characterized in that the inert gas is nitrogen and the gaseous mixture of argon gas
Body.
5. forming method according to claim 4, which is characterized in that the process of thermal treatment parameter includes：Temperature is
900 DEG C to 1300 DEG C, the time is 30min to 800min, and the flow of oxygen is 1slm to 20slm, and the flow of hydrogen is 0.1slm
To 10slm, the flow of nitrogen is 0.1slm to 20slm, and the flow of argon gas is 0.1slm to 20slm.
6. forming method according to claim 1, which is characterized in that further include：It is formed and is located at filling out on the insulating layer
Layer is filled, the filled layer expires the trench fill.
7. forming method according to claim 6, which is characterized in that the material of the filled layer is silica, silicon nitride
Or polysilicon.
8. forming method according to claim 1, which is characterized in that further include：It is formed full exhausted of the trench fill
Edge layer.
9. forming method according to claim 1, which is characterized in that the forming method of the doped region includes：
Mask layer is formed over the substrate, and the mask layer has the opening for exposing substrate；
O +ion implanted is carried out by mask of the mask layer, to form the doped region in the substrate below the opening；
It is formed after the doped region, removes the mask layer.
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| CN101258590A (en) * | 2005-09-06 | 2008-09-03 | Nxp股份有限公司 | Method of manufacturing a semiconductor device with an isolation region and a device manufactured by the method |
| CN101692435A (en) * | 2009-10-15 | 2010-04-07 | 苏州博创集成电路设计有限公司 | Etching and filling method of deep groove isolation structure of silicon-on-insulator |
-
2013
- 2013-09-30 CN CN201310462446.1A patent/CN104517889B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6521947B1 (en) * | 1999-01-28 | 2003-02-18 | International Business Machines Corporation | Method of integrating substrate contact on SOI wafers with STI process |
| CN1431701A (en) * | 2003-02-14 | 2003-07-23 | 中国科学院上海微系统与信息技术研究所 | Method for forming graphical oxygen injection and separator with shallow grooves at same time |
| CN101258590A (en) * | 2005-09-06 | 2008-09-03 | Nxp股份有限公司 | Method of manufacturing a semiconductor device with an isolation region and a device manufactured by the method |
| CN101692435A (en) * | 2009-10-15 | 2010-04-07 | 苏州博创集成电路设计有限公司 | Etching and filling method of deep groove isolation structure of silicon-on-insulator |
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| Publication number | Publication date |
|---|---|
| CN104517889A (en) | 2015-04-15 |
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