KR20080079040A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device is provided to prevent bridge of a bit line and a power line from being occurred in a formation region of a sense amplifier in order to prevent generation of a leakage current. A method of manufacturing a semiconductor device includes the steps of: forming a landing plug(120) connected to an active region of a substrate in a first region and a second region; forming a first interlayer insulation layer(110) to cover the landing plug; forming bit lines(140) on the landing plug not to overlap with the landing plug; forming a first storage node contact plug(170) to penetrate between the bit lines to be connected to the land plug; forming a second storage node contact plug(190) on the first storage node contact plug; forming a power line(200) on the second storage node contact plug in the second region; and forming a wiring contact plug(230) to be connected to the power line. A cell is formed in the first region and the sense amplifier is formed in the second region.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a SEM (Scanning Electron Microscope) photograph for explaining the problems caused in the method of manufacturing a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with Example 1 of the present invention.

3 is a cross-sectional view showing a semiconductor device according to Embodiment 2 of the present invention.

<Explanation of symbols for main parts of drawing>

100: substrate

110, 130, 160, 180, 220: interlayer insulation film

120: landing plug

140: bit line

150: bit line spacer

170, 190: Storage node contact plug

200: power line

210: power line spacer

230: wiring contact plug

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for forming metal wiring in a semiconductor device.

In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices have been highly integrated, the size of unit devices, for example, transistors and capacitors, has gradually decreased since devices must be formed at a high density on a constant cell area. Accordingly, the gap between the connecting wires electrically connecting them is also decreasing. As such, the leakage current increases due to a decrease in the distance between the semiconductor device and the wirings.

In particular, in the case of a DRAM device, a current flow increases due to a leakage path in the semiconductor device when it is in a standby state, which causes a failure of device operation. In the area where the double sense amplifier is to be formed, the power supply wirings (hereinafter, referred to as power lines) and the bit lines extend in a direction perpendicular to each other and are connected to each other through metal contacts. Connected. However, as mentioned above, as the size of the device is gradually reduced, as shown in FIG. 1, a bridge causing leakage between adjacent wires and contacts, or between wires and wires, or between wires and devices is generated. (See area A). In particular, such bridges frequently occur in areas where a large number of patterns are formed, such as areas where patterns are dense. In the case of mobile products, standby leakage current is controlled in microamps. However, there is a problem in that the leakage current amount is caused to be more than microamps by the bridge, which causes the device operation to be defective.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and prevents the occurrence of bridges between the bit line and the power line in the region where the sense amplifier is to be formed, and thereby prevents leakage current generation. It relates to a manufacturing method of.

According to an aspect of the present invention, there is provided a semiconductor device including a first region in which a cell is to be formed and a second region in which a sense amplifier is to be formed. Forming a landing plug connected to the active region of the substrate, forming a bit line on the landing plug so as not to overlap the landing plug, and passing through the bit line to the first story connected to the landing plug Forming a second node contact plug; forming a second storage node contact plug on the first storage node contact plug; and wherein the second region forms a power line on the second storage node contact plug. It provides a method for manufacturing a semiconductor device comprising the step.

According to another aspect of the present invention, there is provided a semiconductor device manufacturing method including a first region in which a cell is to be formed and a second region in which a sense amplifier is to be formed. Forming a landing plug connected to an active region of the substrate in a region, forming a bit line on the landing plug so as not to overlap the landing plug, and passing through the bit line to the first plug connected to the landing plug; Forming a storage node contact plug, forming a second storage node contact plug on the first storage node contact plug, and forming a wire contact plug on the second storage node contact plug in the second region It provides a method for manufacturing a semiconductor device comprising the step of.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals (reference numerals) throughout the specification represent the same elements.

Example 1

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with Example 1 of the present invention. Here, only the region in which the sense amplifier is to be formed except the cell region is shown in the core region.

First, as shown in FIG. 2A, a first interlayer insulating layer 110 is formed on a semiconductor substrate 100 on which various elements for forming a semiconductor device such as a well and a transistor (including a gate and a junction region) are formed. do. In this case, the first interlayer insulating layer 110 may include boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), un-doped silicate glass (USG), tetra thyle ortho silicate (TEOS), spin on glass (SOG), and sod. At least one selected from the group consisting of (Spin On Dielectric) is used. Of course, the present invention is not limited thereto, and an inorganic or organic low dielectric constant film may be used in addition to the oxide film series.

Meanwhile, an additional dummy gate pattern is formed in the transistor manufacturing process formed in the cell region in a region corresponding to the power line through a subsequent process among the regions where the sense amplifier is to be formed.

Subsequently, the first interlayer insulating layer 110 is selectively etched to form a contact hole (not shown) that exposes the impurity diffusion region, that is, the junction region, of the substrate 100 such as the source and drain regions. In this case, the etching process is a self-aligned contact (hereinafter referred to as SAC) etching process.

Subsequently, polysilicon is deposited with a landing plug conductive film so as to fill the contact holes. In this case, although polysilicon is used as the landing plug conductive film, all conductive films including silicon such as amorphous silicon, selective epitaxial growth silicon film, and conductive films such as metals are possible. .

Subsequently, a CMP (Chemical Mechanical Polishing) process is performed using a SAC nitride film (not shown) as a polishing stop film. As a result, a plurality of cell contact plugs, that is, a landing plug 120 is formed.

Subsequently, a second interlayer insulating layer 130 is formed on the first interlayer insulating layer 110 on which the landing plug 120 is formed. In this case, the second interlayer insulating layer 130 may be formed of the same material as the first interlayer insulating layer 110. Of course, the second interlayer insulating film 130 may be formed in a stacked structure in which two films having different etching characteristics are stacked.

Although not shown in the drawings, the second interlayer insulating layer 130 is selectively etched to expose a portion of the landing plug 120 to define a bit line formation region, and then the bit line contact is performed in a similar process to the landing plug 120. A plug (not shown) is formed.

Subsequently, a bit line 140 is electrically connected to the bit line contact plug. In this case, the bit line 140 has a structure in which the bit line conductive layer 141 and the hard mask layer 142 are stacked. For example, the bit line conductive layer 141 uses at least one selected from the group consisting of polysilicon, tungsten (W), tungsten nitride (WN), and tungsten silicide (Wsi), or is formed in a stacked structure in which they are stacked. do. The bit line hard mask 142 is to protect the bit line conductive layer 141 when misalignment occurs in the process of forming the contact hole by etching the interlayer insulating layer during the subsequent etching process for forming the contact hole for the storage node. A material having a significantly different etching selectivity from the insulating film is used. For example, when an oxide-based layer is used as an interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used. When a polymer-based low dielectric film is used as an interlayer insulating film, an oxide-based material is used. do.

For example, the bit line conductive layer 141 including tungsten and the bit line hard mask 142 including nitride are sequentially formed on the second interlayer insulating layer 130, and then CF ₄ / CHF ₃ / O ₂ is formed. A portion of the bit line hard mask 142 is etched using a gas combination such as / Ar. Subsequently, the bit line conductive layer 141 is etched using a gas combination such as SF ₆ / BCl ₃ / N ₂ / Cl ₂ using the etched bit line hard mask 142 as an etch mask to fabricate the bit line 140. do.

Subsequently, an insulating film for a spacer is formed on the entire structure where the bit line 140 is formed, and then an etch back process is performed to form the bit line spacer 150 on both sidewalls of the bit line 140. Since the bit line spacer 150 plays the same role as the bit line hard mask 142, it is preferable to use the same material film as the bit line hard mask 142. Of course, the present invention is not limited thereto, and an insulating film having an interlayer insulating film and a high etching selectivity may be used. For example, a silicon nitride film or a silicon oxynitride film is used.

Subsequently, as illustrated in FIG. 2B, a third interlayer insulating layer 160 is formed on the substrate 100 including the bit line 140. In this case, the third insulating interlayer 160 uses the same insulating material film as the first and second interlayer insulating layers 110 and 130.

Subsequently, although not shown, a lower mask may be further formed on the third interlayer insulating layer 160.

Subsequently, a photoresist film is coated on the lower mask film, and then a photoresist mask pattern (not shown) is formed through an exposure and development process. On the other hand, an anti-reflection film for preventing diffuse reflection may be further formed before the photosensitive film is applied.

Subsequently, the lower mask is etched through an etching process using the photoresist mask pattern as an etching mask to expose the third interlayer insulating layer 160 in the region where the lower storage node contact hole is to be formed.

Subsequently, the third interlayer insulating layer 160 and the second interlayer insulating layer 130 are sequentially etched using the etched hard mask to form a lower storage node contact hole exposing the landing plug 120. In this case, etching is performed such that the etching selectivity between the third interlayer insulating layer 160 and the hard mask is 10: 1 or more. For example, the etching process may be C _x F _y (x, y is a natural number)-for example, C ₄ F ₈ , C ₅ F ₈ , C ₄ F ₆ Etc., C _x H _y F _z (x, y, z is a natural number)-for example, CH ₂ F ₂ and the like,-Ar / O ₂ / CO / N ₂ It is preferably carried out using a gas combination. As a result, even if an alignment error of the etched hard mask occurs, the bit line hard mask 142 and the bit line spacer 150 are provided on the bit line conductive layer 141 and the sidewalls, respectively, to expose the bit line conductive layer 141. Instead, the landing plug 120 in the region between the bit lines 140 may be opened.

Subsequently, in order to remove the etching residue generated during the etching process for opening the landing plug 120, a solution containing H ₂ O ₂ or a ratio of HF and NH ₄ F is 300: 1 BOE (Buffered Oxide Etchant). To carry out the cleaning step. In this case, the cleaning process may be performed between all the processes described above and the processes.

Meanwhile, in the etching process for opening the landing plug 120, first, the third interlayer insulating layer 160 is etched to expose a portion of the second interlayer insulating layer 130, and then a portion of the exposed second interlayer insulating layer 130 is removed. It may be etched to open the landing plug 120.

Subsequently, the storage node contact hole is filled with a conductive material layer to form a lower storage node contact plug 170 connected to the landing plug 120. For example, a conductive material layer is formed on the third interlayer insulating layer 160 where the storage node contact hole is formed. In this case, polysilicon is used as the conductive material film. Of course, it is not limited to this, A metal, such as tungsten, can also be used. Thereafter, the lower storage node contact plug 170 is formed by removing the conductive material layer on the third interlayer insulating layer 160 through a planarization process using the third interlayer insulating layer 160 as the polishing stop layer. At this time, it is preferable to perform an etch back process or a CMP process using a gas combination such as C ₂ F ₆ / Cl ₂ / HBr / CHF ₃ as the planarization process.

Subsequently, as illustrated in FIG. 2C, a fourth interlayer insulating layer is formed on the third interlayer insulating layer 160 on which the lower storage node contact plug 170 connected to the landing plug 120 is formed. In this case, the fourth interlayer insulating layer 180 is formed of any one insulating film selected from the same insulating material layers as those of the first to third interlayer insulating layers 110, 130, and 160.

Subsequently, after forming a hard mask (not shown) on the fourth interlayer insulating layer 180, a part of the fourth interlayer insulating layer 180 is exposed by etching. A portion of the fourth interlayer insulating layer 180 is removed using the etched hard mask as an etch mask to form an upper storage node contact hole that opens the lower storage node contact plug 170.

Subsequently, a conductive film is formed on the fourth interlayer insulating film 180 provided with the upper storage node contact hole, and then the conductive film on the fourth interlayer insulating film 180 is formed through a planarization process using the fourth interlayer insulating film 180 as a polishing stop film. The upper storage node contact plug 190 connected to the lower storage node contact plug 170 is removed to form the upper storage node contact plug 190.

Subsequently, as illustrated in FIG. 2D, the power line conductive layer 201 and the power line hard mask 202 are sequentially formed on the fourth interlayer insulating layer 180 on which the upper storage node contact plug 190 is formed. In this case, at least one selected from the group consisting of polysilicon, tungsten, tungsten nitride, and tungsten silicide is used as the power line conductive film 201. As the power line hard mask 202, a nitride film-based material such as a silicon nitride film or a silicon oxynitride film is used.

Subsequently, a photoresist film is coated on the power line hard mask 202 and then exposed and developed to form a photoresist mask pattern (not shown).

Subsequently, the power line hard mask 202 is etched through an etching process using the photoresist mask pattern as an etching mask.

Subsequently, the power line conductive layer 201 is etched through an etching process using the etched power line hard mask 202 as an etch mask to form a power line 200 connected to the upper storage node contact plug 190. Here, the power line hard mask 202 may be omitted as necessary. The photoresist mask pattern may be removed after the power line hard mask 202 is etched.

Next, an insulating film for the power line spacer is formed on the entire structure where the power line 200 is formed.

Subsequently, the front surface is etched to form the power line spacer 210 on the sidewall of the power line 200.

Subsequently, as illustrated in FIG. 2E, a fifth interlayer insulating layer 220 is formed on the fourth interlayer insulating layer 180 on which the power line 200 is formed.

Subsequently, a photoresist mask pattern (not shown) is formed on the fifth interlayer insulating film 220, and a portion of the fifth interlayer insulating film 220 and the power line hard mask 202 are formed through an etching process using the photoresist mask pattern (not shown). To form a wiring contact hole (not shown).

Subsequently, a conductive film is formed on the substrate 100 including the wiring contact hole, and the contact plug 230 connected to the power line 200 is formed through a planarization process using the fifth interlayer insulating film 220 as a polishing stop film. Form. In this case, as the conductive film, a metal film such as tungsten, aluminum, copper, as well as a polysilicon film may be used.

As described above, the upper and lower storage node contact plugs are sequentially formed on the landing plug region, and then a power line is formed thereon, and a wire contact plug connected to the power line is formed to form a gap between the lower bit line and the power line. They can be spaced far enough to prevent bridges between the two lines, reducing the leakage current of the device. Here, a lower storage node contact plug is formed to be connected to the landing plug when the lower cell storage node contact plug is formed in the cell area, and an upper storage node contact is connected to the lower storage node contact plug when the upper storage node contact plug is formed in the cell area. The plug may be formed, and a power line connected to the upper storage node contact plug may be formed to provide power applied from the outside to the active region of the substrate through the upper and lower storage node contact plugs and the landing plug.

Example 2

3 is a cross-sectional view of a semiconductor device according to Embodiment 2 of the present invention.

In Example 2 below, without forming a power line, the upper storage node contact plug and the wiring contact plug directly connected to the landing plug are directly connected through the lower storage node contact plug.

Since the fabrication process up to the upper storage node contact plug is similar to that of FIGS. 2A to 2C, the embodiment 2 will be omitted.

First, as shown in FIG. 3, a fifth interlayer insulating layer 220 is formed on the fourth interlayer insulating layer 180 on which the upper storage node contact plug 190 is formed.

Subsequently, a photosensitive film is coated on the fifth interlayer insulating film 220, and a photosensitive film mask pattern (not shown) is formed through an exposure and development process using a mask.

Subsequently, a portion of the fifth interlayer insulating layer 220 is removed through an etching process using the photoresist mask pattern as an etching mask to form a wiring contact hole exposing the upper storage node contact plug 190.

Subsequently, after removing the photoresist mask pattern, a conductive film for wiring contact is formed on the entire structure.

Subsequently, the wiring contact plug 230 connected to the upper storage node contact plug 190 is formed by removing the conductive layer for the wiring contact on the fifth interlayer insulating layer 220 through the planarization process.

As described above, the second embodiment can omit the manufacturing process of the power line compared to the first embodiment, thereby simplifying the process.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, according to the present invention, a bit line and upper and lower storage node contact plugs may be formed, and then a power line may be manufactured to prevent the occurrence of a bridge current between the bit line and the power line, thereby preventing leakage current.

Second, according to the present invention, wiring contact plugs connected to the landing plugs through upper and lower storage node contact plugs may be formed to prevent leakage currents and simplify the process.

Claims (15)

A method of manufacturing a semiconductor device comprising a first region where a cell is to be formed and a second region where a sense amplifier is to be formed, Forming landing plugs connected to the active regions of the substrate in the first and second regions; Forming a bit line on the landing plug such that it does not overlap the landing plug; Forming a first storage node contact plug penetrating between the bit lines and connected to the landing plug; Forming a second storage node contact plug on the first storage node contact plug; And Forming a power line on the second storage node contact plug in the second region Method of manufacturing a semiconductor device comprising a. The method of claim 1, After forming the power line, And forming a wire contact plug connected to the power line. The method of claim 1, After forming the landing plug, And forming a first interlayer insulating film to cover the landing plug. The method of claim 3, wherein After forming the bit line, Forming a second interlayer insulating layer on the substrate including the bit line; And Etching a portion of the first and second interlayer insulating layers to expose the landing plugs to form contact holes Method of manufacturing a semiconductor device further comprising. The method of claim 4, wherein The forming of the first storage node contact plug may include: Depositing a material for the first storage node contact plug to fill the contact hole; And Planarizing the first storage node contact plug material using the second interlayer insulating layer as a polishing stop layer Method of manufacturing a semiconductor device comprising a. The method of claim 1, After the forming of the first storage node contact plug, Forming an interlayer insulating layer on the substrate including the first storage node contact plug; And Etching the interlayer insulating layer to expose the first storage node contact plug to form a contact hole Method of manufacturing a semiconductor device further comprising. The method of claim 6, The forming of the second storage node contact plug may include: Depositing a material for the second storage node contact plug to fill the contact hole; And Planarizing the second storage node contact plug material by using the interlayer insulating layer as a polishing stop layer Method of manufacturing a semiconductor device comprising a. The method according to any one of claims 1 to 7, Before forming the landing plug, Forming a gate pattern for a cell on the substrate in the first region and simultaneously forming a dummy gate pattern on the substrate in the second region corresponding to the power line. A method of manufacturing a semiconductor device comprising a first region where a cell is to be formed and a second region where a sense amplifier is to be formed Forming landing plugs connected to the active regions of the substrate in the first and second regions; Forming a bit line on the landing plug such that it does not overlap the landing plug; Forming a first storage node contact plug penetrating between the bit lines and connected to the landing plug; Forming a second storage node contact plug on the first storage node contact plug; And Forming a wire contact plug on the second storage node contact plug in the second region Method of manufacturing a semiconductor device comprising a. The method of claim 9, After forming the landing plug, And forming a first interlayer insulating film to cover the landing plug. The method of claim 10, After the bit line forming step, Forming a second interlayer insulating layer on the substrate including the bit line; And Etching a portion of the first and second interlayer insulating layers to expose the landing plugs to form contact holes Method of manufacturing a semiconductor device further comprising. The method of claim 11, The forming of the first storage node contact plug may include: Depositing a material for the first storage node contact plug to fill the contact hole; And Planarizing the first storage node contact plug material using the second interlayer insulating layer as a polishing stop layer Method of manufacturing a semiconductor device comprising a. The method of claim 9, After the forming of the first storage node contact plug, Forming an interlayer insulating layer on the substrate including the first storage node contact plug; And Etching the interlayer insulating layer to expose the first storage node contact plug to form a contact hole Method of manufacturing a semiconductor device further comprising. The method of claim 13, The forming of the second storage node contact plug may include: Depositing a material for the second storage node contact plug to fill the contact hole; And Planarizing the second storage node contact plug material by using the interlayer insulating layer as a polishing stop layer Method of manufacturing a semiconductor device comprising a. The method according to any one of claims 9 to 14, Before forming the landing plug, Forming a gate pattern for a cell on the substrate in the first region and simultaneously forming a dummy gate pattern on the substrate in the second region corresponding to the wiring contact plug.

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