KR20080071256A - Method of manufacturing floating gate in non-volatile memory device - Google Patents

Abstract

A method for manufacturing a floating gate in a non-volatile memory device is provided to improve a coupling ratio by adjusting a height of a floating gate. A field oxide layer pattern(112) is formed on a surface of a substrate(100) to form an opening for exposing a part of the substrate. A conductive layer for floating gate is formed along the field oxide layer pattern and the surface of the exposed substrate. A stop layer is formed on the conductive layer for floating gate. A sacrificial layer is formed on the stop layer to fill the opening. A preliminary floating gate is formed by polishing the sacrificial layer to expose the stop layer on a bottom surface of the opening. A floating gate(126) is formed by removing selectively the stop layer.

Description

Method of manufacturing floating gate in non-volatile memory device

1 to 10 are schematic cross-sectional views illustrating a method of forming a floating gate of a nonvolatile memory device according to an embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

100 semiconductor substrate 102 pad oxide film pattern

104: silicon nitride film pattern 106: hard mask pattern

108: trench 110: gap fill oxide film

112: field oxide film pattern 114: tunnel oxide film

116: opening 118: first conductive film

120: stop film 122: sacrificial film

124: preliminary floating gate 126: floating gate

128: dielectric film

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a floating gate of a nonvolatile memory device.

Semiconductor memory devices, such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), are volatile and fast data input / output that loses data over time, and data is input once. It can be maintained in this state, but it can be classified into ROM (Read Only Memory) products that have slow input / output data. Among these ROM products, there is an increasing demand for electrically erasable and programmable ROM (EEPROM) or flash memory.

The flash memory unit cell includes a vertical stacked gate structure having a floating gate. In detail, the gate of the flash memory cell has a structure in which a floating gate, a dielectric layer, and a control gate are stacked on the tunnel oxide layer.

In order to form the floating gate as described above, an opening is formed in a portion where the floating gate is to be formed, and a process of polishing the polysilicon after depositing the polysilicon for floating gate filling the inside of the opening is performed. However, not only the polishing rate of polysilicon is different at the center and periphery of the substrate, but also the polishing rate of polysilicon is different in a cell region having a high pattern density and a ferry region having a low pattern density within one chip. Because of this, it is very difficult to polish the polysilicon evenly over the entire substrate area.

Therefore, problems such as the height of the floating gate finally formed vary by region of the substrate or where the floating gate is not normally separated in a region where the polysilicon is not sufficiently polished.

As a result, since the floating gate height formed on each area of the substrate has a nonuniform distribution, a problem arises that the operating characteristics of the cells formed on the substrate are not uniform.

An object of the present invention for solving the above problems is to provide a floating gate forming method having a uniform height in the entire area of the substrate.

In the floating gate forming method of the nonvolatile memory device according to an embodiment of the present invention for achieving the above object, first to form a field oxide film pattern protruding from the surface of the substrate to form an opening for exposing a portion of the surface of the substrate; . A conductive film for a floating gate is formed along the field oxide layer pattern and the surface of the exposed substrate. A blocking film is formed on the conductive film for the floating gate. A sacrificial layer is formed on the blocking layer to fill the opening. The sacrificial layer is polished to expose the blocking layer formed on the bottom surface of the opening, thereby forming a preliminary floating gate in which the node is separated. Next, the blocking film is selectively removed to form a floating gate.

According to embodiments of the present invention, the blocking film may include silicon nitride.

According to embodiments of the present invention, before removing the blocking layer, the method may further include isotropically etching and planarizing an upper surface of the preliminary floating gate.

According to embodiments of the present invention, the isotropic etching may be performed by a wet etching or a chemical dry etching method.

In example embodiments, the field oxide layer pattern may include forming a hard mask pattern including a pad oxide layer and a nitride layer pattern on a substrate, and etching the substrate using the hard mask pattern as an etch mask to form a trench. An oxide layer for device isolation may be formed on the substrate to fill the trench, and the oxide layer for device isolation may be polished to expose the upper portion of the hard mask pattern to form a field oxide pattern, and then the nitride layer pattern may be removed. Can be.

As described above, according to the present invention, in the polishing step of forming the floating gate, by using the polishing stopper film, it is possible to form the floating gate having a uniform dispersion over the entire area of the substrate. As a result, it is possible to improve the operation characteristics of the cells formed on the substrate.

Hereinafter, a method of forming a floating gate of a nonvolatile memory device in accordance with embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, Those skilled in the art will be able to implement the present invention in various other forms without departing from the spirit of the present invention. In the accompanying drawings, the dimensions of substrates, layers (films), openings, gates or patterns are shown in greater detail than actual for clarity of the invention. In the present invention, each layer (film), opening, gate or pattern is referred to as being formed "on", "top" or "bottom" of the substrate, each layer (film), opening, gate or pattern. In this case, it means that each layer (film), opening, gate or pattern is formed directly over or below the layer (film), opening, gate or patterns, or another layer (film), another opening, another gate or other Patterns may be additionally formed on the substrate. In addition, where layers (films) or gates are referred to as "spare", "first" and / or "second", they are not intended to limit these members but merely to distinguish each layer (film) or gates. . Thus, "preliminary", "first" and / or "second" may be used selectively or interchangeably for each layer (film) or gates, respectively.

1 to 10 are schematic cross-sectional views illustrating a method of forming a floating gate of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, a pad oxide film (not shown) and a silicon nitride film for a hard mask (not shown) are formed on a semiconductor substrate 100. The pad oxide layer may be formed by a thermal oxidation process. In addition, the pad oxide layer is formed to reduce stress generated when the silicon nitride layer formed thereafter is in direct contact with the semiconductor substrate 100.

The silicon nitride film may be formed by a low pressure chemical vapor deposition (LPCVD) process. In this case, an organic anti-reflection layer (ARL, not shown) may be further formed on the silicon nitride layer. The holding antireflection film is provided to prevent the sidewall profile of the photoresist pattern from being deteriorated by diffuse reflection in a subsequent photographic process.

A photoresist pattern (not shown) is formed on the silicon nitride film to expose a portion of the silicon nitride film. The silicon nitride film and the pad oxide film are sequentially etched using the photoresist pattern as an etching mask to form a hard mask pattern 106 in which the pad oxide film pattern 102 and the silicon nitride film pattern 104 are stacked. The hard mask pattern 106 is formed to selectively expose a portion corresponding to a field region of the semiconductor substrate 100. Thereafter, the photoresist pattern may be removed through an ashing process or a strip process.

Referring to FIG. 2, the trench 108 is formed by selectively etching the exposed region of the semiconductor substrate 100 using the hard mask pattern 106 as an etching mask. In this case, the organic anti-reflection film may be removed while etching the semiconductor substrate 100.

After the trench 106 is formed, a thermal oxide film (not shown) and an insulating film liner (not shown) may be selectively formed. In more detail, the thermal oxide film is provided to cure surface damage generated during the previous dry etching process. The thermal oxide film may be thermally oxidized on the surface of the trench 108 to have a very thin thickness. Subsequently, an insulating film liner is formed on the inner side and the bottom of the trench 108 where the thermal oxide film is formed, and the surface of the hard mask pattern 106 with a thickness of several hundreds of microseconds.

The insulating film liner is provided to reduce stress inside the silicon isolation film (not shown) embedded in the trench 108 by a subsequent process and to prevent impurity ions from penetrating into the field region. The insulating film liner should be formed of a material having a high etching selectivity with a silicon oxide film to be subsequently formed under specific etching conditions. For example, the insulating film liner may be formed of silicon nitride (SiN).

Referring to FIG. 3, a gap buried oxide film 110 is formed to fill the trench 108.

The gap buried oxide film 110 may be a USG (Undoped Silicate Glass) oxide, an O ₃ -TEOS USG (O ₃ -Tetra Ethyl Ortho Silicate Undoped Silicate Glass) oxide, or a High Density Plasma (HDP) oxide film having excellent gap filling characteristics. It may be deposited by performing a chemical vapor deposition (CVD) method. The high density plasma oxide layer may be deposited using SiH ₄ , O _2, and Ar gas as a plasma source, and the gap of the high density plasma oxide layer may be such that cracks or voids are not formed in the trench 108. The trench 108 may be buried by improving the buried capability.

In addition, if necessary, annealing is performed under a high temperature and inert gas atmosphere of about 800 to 1050 ° C. to densify the gap buried oxide film 110 to lower the wet etching rate for the subsequent cleaning process. can do.

Referring to FIG. 4, the gap buried oxide film 108 is polished to expose the hard mask pattern 106. The polishing process may be performed using an etch back or chemical mechanical polishing (CMP) process. As a result, a field oxide film pattern 112 is formed in the trench 108.

By removing the nitride layer pattern 104 and the pad oxide layer pattern 102, an opening 114 exposing a portion of the substrate 100 is formed between the field oxide layer pattern 112. The nitride layer pattern 104 may be selectively removed using a phosphoric acid solution, and the pad oxide layer pattern 102 may be selectively removed using a diluted hydrofluoric acid solution.

Thereafter, a tunnel oxide layer 114 is formed on the exposed semiconductor substrate 100. The tunnel oxide layer 114 may be formed by a thermal oxidation process.

Referring to FIG. 5, the first conductive layer 118 for floating gate is formed along the surfaces of the tunnel oxide layer 114 and the field oxide layer pattern 112.

The first conductive layer 118 may be formed by depositing polysilicon or amorphous silicon by low pressure chemical vapor deposition (LPCVD), and then doping impurities by a doping method. The first conductive layer 114 may be doped with a high concentration of N-type impurities by, for example, a doping method such as POCl ₃ diffusion, ion implantation, or in-situ doping.

Referring to FIG. 6, a blocking layer 116 is formed on the first conductive layer 118.

The stopper layer 116 may have the first conductive layer 118 and the field oxide layer pattern 120 uniformly polished in the subsequent polishing process so that the first conductive layer 118 and the field oxide layer pattern 120 are uniformly polished. It is formed of a material that is polished very slowly compared to).

That is, when polishing the first conductive film 118 and the field oxide film pattern 120, the surface of the blocking film 116 is exposed to expose the first conductive film 118 and the field oxide film pattern 120. ) Can be polished to a uniform thickness. Specifically, the blocking layer 118 may be formed by depositing silicon nitride.

In this case, when the blocking film 118 is formed thick enough to fill the inside of the opening 114, the polishing rate is very slow by the blocking film 118 formed on the field oxide film pattern 120. Therefore, the blocking film 118 is preferably formed thin along the surface profile of the first conductive film 118 without filling the inside of the opening 114.

Referring to FIG. 7, a sacrificial layer 122 is formed on the blocking layer 120 to fill the opening 114.

The sacrificial layer 122 may be formed of a material having an etching selectivity similar to that of the first conductive layer 122 as well as an excellent gap filling property. The sacrificial film 122 may be formed by depositing a USG (Undoped Silicate Glass) oxide film by a chemical vapor deposition method.

Referring to FIG. 8, the sacrificial layer 122, the first conductive layer 118, and the field oxide layer pattern 120 are polished to expose the blocking layer 116 formed on the bottom surface of the opening 114. . As a result, the preliminary floating gate 124 is formed.

The polishing process may be performed using an etch back or chemical mechanical polishing process. In the polishing process, since the blocking layer 122 has a slower polishing rate than the sacrificial layer 122, the first conductive layer 118, and the field oxide layer pattern 112, the blocking layer 122 is formed on the entire surface of the opening 114. The polishing process can be easily adjusted so that the stopper film 116 is exposed.

As a result, a uniform polishing process may be performed over the entire region such that the blocking layer 116 formed on the bottom surface of the opening 114 is exposed. Accordingly, since the polishing of the first conductive layer 118 is not sufficiently performed in the past, neighboring floating gates may not be separated, thereby preventing a short circuit between the neighboring floating gates.

In addition, since the field oxide film pattern is conventionally used as the polishing stop layer, the height of the floating gate is limited according to the height of the field oxide film pattern. However, when the polishing stopper layer is used, not only the thickness of the initially deposited floating gate can be maintained but also the height of the floating gate can be minimized, thereby improving the coupling ratio.

9, the upper surface of the preliminary floating gate 124 is planarized using an isotropic etching process.

The isotropic etching process may be performed by using a wet etch method or a chemical dry etch method using a SC-1 (standard clean-1) solution containing ammonia, hydrogen peroxide and water.

The isotropic etching process is performed such that an upper surface of the preliminary floating gate 124 is positioned on the same plane as a lower surface of the blocking layer 120. That is, the upper surface of the preliminary floating gate 124 adjacent to the blocking layer 120 is etched by the thickness of the blocking layer 120. As a result, the top surface of the preliminary floating gate 124 is planarized.

Referring to FIG. 10, the blocking layer 120 is selectively removed. Since the stopper layer 120 is formed of a silicon nitride layer, it may be removed by performing a phosphate strip process. As a result, the floating gate 126 is formed.

Thereafter, a dielectric film 128 is formed along the floating gate 126. The dielectric layer 128 is provided to insulate the floating gate 126 from a control gate (not shown) to be formed subsequently. Examples of the dielectric film 128 include a composite dielectric film made of an oxide film / nitride film / ONO, a high dielectric material film made of a high dielectric constant material, and the like.

The composite dielectric film may be formed by a low pressure chemical vapor deposition (LPCVD) process. In addition, the high-k material film may be formed of Y ₂ O ₃ , HfO ₂ , ZrO ₂ , Nb ₂ O ₅ , BaTiO ₃ , SrTiO ₃ , and the like, and may be formed by atomic layer deposition (ALD) or chemical vapor deposition (ALD). Can be formed by a CVD process

Subsequently, although not shown in detail, a control gate (not shown) including a second conductive layer (not shown) and a third conductive layer (not shown) are formed on the dielectric layer 128. The second conductive layer may be made of polysilicon doped with impurities, and the third conductive layer may be made of metal silicide such as tungsten silicide (WSix), titanium silicide (TiSix), cobalt silicide (CoSix), tantalum silicide (TaSix), or the like. Can be.

As a result, a gate structure of a flash memory device in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked may be completed.

As described above, according to the present invention, the coupling ratio can be improved by adjusting the height of the floating gate, as well as forming a floating gate having a uniform dispersion for each of the center and the periphery of the substrate using the polishing stopper film.

As a result, the operating characteristics and the reliability of the nonvolatile memory device can be improved.

As described above, the present invention has been described with reference to a preferred embodiment of the present invention, but a person having ordinary skill in the relevant art may make the present invention without departing from the spirit and scope of the present invention described in the claims below. It will be understood that various modifications and changes can be made.

Claims (5)

Forming a field oxide pattern protruding from the surface of the substrate such that an opening is formed to expose a portion of the surface of the substrate; Forming a conductive film for a floating gate along the field oxide pattern and a surface of the exposed substrate; Forming a blocking film on the conductive film for the floating gate; Forming a sacrificial layer on the blocking layer to fill the opening; Polishing the sacrificial layer to expose a stop layer formed on the bottom of the opening to form a node-prepared pre-floating gate; And Selectively removing the blocking layer to form a floating gate. The method of claim 1, wherein the blocking layer comprises silicon nitride. The method of claim 1, further comprising isotropically etching and planarizing an upper surface of the preliminary floating gate before removing the blocking layer. The method of claim 3, wherein the isotropic etching is performed by a wet etch or chemical dry etch method. The method of claim 1, wherein the field oxide film pattern, Forming a hard mask pattern having a pad oxide film and a nitride film pattern stacked on a substrate; Etching the substrate using the hard mask pattern as an etch mask to form a trench; Forming an isolation layer on the substrate to fill the trench; Forming a field oxide layer pattern by polishing the oxide layer for isolation of the device to expose an upper portion of the hard mask pattern; And And removing the nitride film pattern.

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