KR20080060722A - A shift register - Google Patents

Abstract

A shift register is provided to prevent a voltage accumulation of a node of respective stages due to coupling by discharging the node of respective stages whenever clock pulses are supplied to respective stages during a non-output period. A shift register includes plural stages that supply scan pulses to plural gate lines. At least one of the stages includes a pull-up switching element(Trpu), a pull-down switching element(Trpd), a node controller(NC), and a discharge unit(DU). The pull-up switching element, which is turned on or off according to a logical state of a node signal, receives a first clock in the turn on thereof, outputs scan pulses, and supplies the scan pulses to gate lines. The pull-down switching element supplies a discharge voltage to the gate line in response to a first control signal from outside. The node controller controls the logical state of the node. The discharge unit discharges the node whenever a first clock pulse is supplied to the pull-up switching element during a non-output period where the scan pulses is not outputted at the stage.

Description

A shift register

1 shows one stage in a conventional shift register.

2 illustrates a shift register according to an embodiment of the present invention.

3 is a timing diagram of various signals supplied or output to each stage of FIG.

4 is a diagram illustrating a circuit configuration of a second stage of FIG. 2.

5 is a view illustrating the first to third stages of FIG.

FIG. 6 illustrates another circuit configuration of the second stage of FIG. 2.

FIG. 7 illustrates another circuit configuration of the second stage of FIG. 2.

FIG. 8 illustrates another circuit configuration of the second stage of FIG. 2.

FIG. 9 illustrates another circuit configuration of the second stage of FIG. 2.

* Explanation of symbols on the main parts of the drawings

Vout: Scan pulse VDD: Voltage source for charging

VSS: Voltage source for discharge Vst: Start pulse

Trpu: Pull-up Switching Device Trpd: Pull-down Switching Device

ST: Stage CLK: Clock Pulse

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display, and more particularly, to a shift register capable of preventing multiple outputs due to a coupling phenomenon.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Here, the gate lines are sequentially driven by a scan pulse, which is generated by a shift register.

1 is a diagram illustrating one stage in a conventional shift register.

The conventional stage includes a node control unit 101 for controlling the charging and discharging states of the first node n1 and the second node n2, and the scan pulse Vout according to the signal state of the first node n1. And a pull-down switching device Trpd for outputting a discharge voltage source VSS according to the signal state of the second node n2.

Here, the first node n1 and the second node n2 are alternately charged and discharged. Specifically, when the first node n1 is charged, the second node n2 is charged. The discharged state is maintained, and when the second node n2 is in a charged state, the first node n1 is maintained in a discharged state.

In this case, the scan pulse Vout is output from the pull-up switching device Trpu when the first node n1 is in a charged state, and the pull-down switching device of the output unit when the second node n2 is in a charged state. The discharge voltage source VSS is output from Trpd.

The scan pulse Vout output from the pull-up switching device Trpu and the discharge voltage source VSS output from the pull-down switching device Trpd are supplied to the corresponding gate line.

Here, the gate terminal of the pull-up switching device Trpu is connected to the first node n1, the drain terminal is connected to the clock transmission line to which the clock pulse CLK is applied, and the source terminal is connected to the gate line. do. The clock pulse CLK has a high state and a low state periodically and is supplied to the drain terminal of the pull-up switching device Trpu. In this case, the pull-up switching device Trpu outputs any one of the clock pulses CLK in the high state input every cycle. The clock pulse CLK output at this particular time point is the scan pulse Vout for driving the gate line.

This specific time point means a time point after the first node n1 is charged. That is, the pull-up switching device Trpu is at the specific time point (ie, the time point at which the first node n1 is charged) among the clock pulses CLK which are continuously input to its drain terminal periodically. The input clock pulse CLK of the high state is output as the scan pulse Vout. After the output of the scan pulse Vout, the first node n1 is maintained in a discharge state until the next frame period starts, so that the pull-up switching device Trpu has one scan pulse Vout per frame. ) Will be printed. However, since the clock pulse CLK is output several times in one frame period, the clock pulse even when the pull-up switching device Trpu is turned off, that is, even when the first node n1 is discharged. CLK is continuously input to the drain terminal of the pull-up switching element Trpu.

In other words, the pull-up switching device Trpu is turned on only once for one frame, and outputs the clock pulse CLK input to its drain terminal as a scan pulse Vout during this turn-on period. .

Thereafter, the pull-up switching device Trpu is turned off until the start of the next frame period, so that the pull-up switching device Trpu is clock pulse CLK at its drain terminal no matter how long it is turned off. Is input, it cannot be output as a scan pulse (Vout). However, as the clock pulse CLK is periodically applied to the drain terminal of the pull-up switching device Trpu, the first node n1 and the pull-up to which the gate terminal of the pull-up switching device Trpu is connected are connected. Coupling occurs between the drain terminals of the switching element Trpu. Due to such a coupling phenomenon, the first node n1 is continuously charged with a predetermined voltage corresponding to the clock pulse CLK.

Then, the first node n1 may be maintained in a charged state at any moment. That is, the first node n1 may be maintained in a charged state at an unwanted timing. In this case, the first node n1 may be maintained in the charging state more than once in one frame period, whereby the pull-up switching device Trpu may be turned on more than once in one frame period. As a result, a multi-output phenomenon in which one stage outputs two or more scan pulses Vout in one frame period may occur due to the coupling phenomenon as described above.

As such, when one stage outputs two or more scan pulses Vout during one frame period, the quality of an image displayed on the liquid crystal panel is degraded.

An object of the present invention is to provide a shift register that can prevent multiple outputs by periodically discharging a node whenever a clock pulse is supplied to a pull-up switching device.

The shift register according to the present invention for achieving the above object comprises a plurality of stages in order to sequentially output a scan pulse to the plurality of gate lines, at least one stage is a signal supplied to the node A pull-up switching device which is turned on or turned off according to a logic state of the circuit, receives a first clock pulse to output a scan pulse, and supplies the scan pulse to a gate line; A pull-down switching device configured to output a discharge voltage source and supply the discharge voltage source to the gate line in response to a first control signal from the outside; A node controller for controlling a logical state of the node; And a discharge unit for discharging the node whenever the first clock pulse is supplied to the pull-up switching element during the non-output period in which the stage does not output the scan pulse.

Hereinafter, a shift register according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a shift register according to an exemplary embodiment of the present invention, and FIG. 3 is a diagram illustrating a timing diagram of various signals supplied or output to each stage of FIG. 2.

The shift register according to the embodiment of the present invention includes n stages ST1 to STn and one dummy stage STn + 1 as shown in FIG. 2. Here, each of the stages ST1 to STn outputs one scan pulse Vout1 to Voutn + 1 for one frame period, in which case the scan pulses are sequentially sequentially from the first stage ST1 to the dummy stage STn + 1. Outputs

Here, scan pulses Vout1 to Voutn output from the stages ST1 to STn except for the dummy stage STn + 1 are sequentially supplied to gate lines of the liquid crystal panel (not shown). The gate lines are sequentially scanned.

That is, first, the first stage ST1 outputs the first scan pulse Vout1, and then the second stage ST2 outputs the second scan pulse Vout2, and then, the third stage ST3. Outputs the third scan pulse Vout3, and finally, the nth stage STn outputs the nth scan pulse Voutn.

Meanwhile, after the n-th stage STn outputs the n-th scan pulse Voutn, the dummy stage STn + 1 outputs the n + 1-th scan pulse Voutn + 1, wherein the dummy stage The nth + 1th scan pulse Voutn + 1 output from (STn + 1) is not supplied to the gate line but is supplied only to the nth stage STn.

This shift register is built in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion. The shift register is built in the non-display portion.

The entire stages ST1 to STn + 1 of the shift registers configured as described above are charged voltage sources VDD, discharge voltage sources VSS, and the first and second clock pulses CLK1 to CLK2 circulating with sequential phase differences. ) Is authorized.

The charging voltage source VDD and the discharging voltage source VSS are both DC voltage sources, the charging voltage source VDD exhibits positive polarity, and the discharging voltage source VSS exhibits negative polarity. Meanwhile, the discharge voltage source VSS may be a ground voltage.

The first and second clock pulses CLK1 and CLK2 are output with phase differences from each other. That is, the second clock pulse CLK2 is phase-delayed by one pulse width than the first clock pulse CLK1 and output. Here, the first clock pulse CLK1 and the second clock pulse CLK2 are inverted in phase with each other. Accordingly, the second clock pulse CLK2 indicates a low state when the first clock pulse CLK1 is high and the second clock pulse CLK2 when the first clock pulse CLK1 is low. Indicates a high state.

The first and second clock pulses CLK1 and CLK2 are sequentially output, and are also output in a circular manner. That is, after the first clock pulse CLK1 to the second clock pulse CLK2 are sequentially output, the first clock pulse CLK1 to the second clock pulse CLK2 are sequentially output.

According to the circuit configuration of the stage, the number of clock pulses supplied to one stage may vary.

The first stage ST1 located on the uppermost side of the stages ST1 to STn + 1 may include the above-described charging voltage source VDD, the discharge voltage source VSS, and the first and second clock pulses CLK1. , In addition to CLK2), is further supplied with a start pulse Vst.

The clock pulses CLK1 and CLK2 are output several times in one frame period, but the start pulse Vst is output only once in one frame period.

In other words, each clock pulse CLK1 and CLK2 periodically shows several active states (high states) during one frame period, but the start pulse Vst shows only one active state during one frame period.

In this case, the second clock pulse CLK2 and the start pulse Vst may be output in synchronization with each other. In this case, the second clock pulse CLK2 is first outputted among the first and second clock pulses CLK1 and CLK2.

In order for each stage ST1 to STn + 1 to output a scan pulse, an enable operation of each stage ST1 to STn + 1 must be preceded. The stage being enabled means that the stage is set to a state capable of outputting, that is, a state capable of outputting a clock pulse supplied thereto as a scan pulse. To this end, each stage ST1 to STn + 1 is enabled by receiving scan pulses from the stage located at the front end thereof.

For example, the k th stage is enabled in response to the scan pulse from the k-1 st stage.

Since the stage does not exist in front of the first stage ST1 positioned at the uppermost side, the first stage ST1 is enabled in response to the start pulse Vst from the timing controller.

In addition, each stage ST1 to STn + 1 is disabled in response to the scan pulse from the next stage. When the stage is disabled, it means that the stage is reset to a state in which the output is impossible, that is, the clock pulse supplied to the stage cannot be output as a scan pulse.

For example, the kth stage is disabled in response to the scan pulse from the k + 1th stage.

The configuration of each stage ST1 to STn + 2 in the shift register configured as described above will be described in more detail as follows.

Since the configurations of the stages ST1 to STn + 2 are the same, only the second stage ST2 will be described as an example.

4 is a diagram illustrating a circuit configuration of the second stage of FIG. 2.

As illustrated in FIG. 4, the second stage ST2 includes a node n, a node controller NC, a pull-up switching device Trpu, a pull-down switching device Trpd, and a discharge unit DU. .

The node controller NC controls the signal state of the node n. In other words, the node controller NC makes the node n in a charged state or in a discharged state.

The pull-up switching device Trpd is turned on when the node n is in a charged state, and then outputs a clock pulse input to the node n in the turned-on state. The clock pulse output from the turned-on pull-up switching device Trpu is a scan pulse.

The pull-up switching device Trpu provided in the k-th stage outputs a clock pulse in response to the charging voltage source VDD supplied to the node of the k-th stage, and the k-th gate line, the k + 1 stage, and It supplies to a k-1st stage. To this end, the gate terminal of the pull-up switching device (Trpu) is connected to the node n, the drain terminal is connected to the clock pulse supply line, the source terminal is the k-th gate line, the k + 1 stage, It is connected to the k-1st stage.

For example, the pull-up switching device Trpu provided in the second stage ST2 of FIG. 4 outputs the second scan pulse Vout2, and the second gate line, the third stage ST3, and the first stage ST3 are output. It supplies to stage ST1.

The pull-down switching device Trpd is turned on in response to a clock pulse. In this turned-on state, the discharge voltage source VSS inputted thereto is output.

The pull-down switching device Trpd included in the k-th stage outputs the discharge voltage source VSS in response to the clock pulse, and supplies it to the k-th gate line, the k + 1th stage, and the k-1th stage. To this end, the gate terminal of the pull-down switching device (Trpd) is connected to the clock transmission line, the source terminal is connected to the discharge power transmission line, and the drain terminal is a k-th gate line, a k + 1 stage, It is connected to the k-1st stage.

For example, the pull-down switching device Trpd of the second stage ST2 of FIG. 4 outputs the discharge voltage source VSS in response to the first clock pulse CLK1, and the second gate line GL2. ), The third stage ST3, and the first stage ST1.

The gate line is charged by the scan pulse output from the pull-up switching device Trpu, and is discharged by the discharge voltage source VSS output from the pull-down switching device Trpd.

The discharge unit DU discharges the node n whenever a clock pulse is supplied to the pull-up switching device Trpu during a non-output period in which the stage does not output the scan pulse.

That is, the stage has an output period for outputting a scan pulse and a non-output period for outputting a voltage source for discharge. In the output period, the node n of the stage maintains a charging state, and in the non-output period, the node n of the stage maintains a discharge state.

The discharge unit DU does not have any influence on the node n of the stage in the output period, and periodically makes the node n discharge state in the non-output period so that the node according to the coupling phenomenon. The voltage is prevented from accumulating in (n).

Herein, the configuration of the node controller NC and the discharge unit DU will be described in more detail.

The node controller NC includes first and second switching elements Tr1 and Tr2, and the discharge unit DU includes third to seventh switching elements Tr3 to Tr7.

The first switching device Tr1 included in the node control unit NC of the kth stage responds to the k-1th scan pulse output from the pull-up switching device Trpu of the k-1st stage, thereby providing a charging voltage source ( VDD) is supplied to the node n of the kth stage. To this end, the gate terminal of the first switching device Tr1 provided in the k-th stage is connected to the source terminal of the pull-up switching device Trpu provided in the k-th stage, and the drain terminal is transferred to the charging power source. Is connected to the line, and the source terminal is connected to the node n of the k-th stage.

For example, the first switching device Tr1 included in the second stage ST2 of FIG. 4 may be configured to respond to the first scan pulse Vout1 from the first stage ST1 of the second stage ST2. The node n is charged with the charging voltage source VDD.

On the other hand, the first switching device Tr1 may be turned on by the scan pulse from the front end stage to supply the scan pulse from the front end stage to the node n. That is, the first switching device Tr1 provided in the kth stage is turned on by receiving the k-1th scan pulse from the k-1st stage, and transmits the k-1th scan pulse to node n. The node n may be charged by supplying the same.

The second switching device Tr2 provided in the node controller NC of the kth stage is configured to discharge the voltage source (in response to the k + 1th scan pulse output from the pull-up switching device Trpu of the k + 1st stage). VSS) is supplied to the node n of the kth stage. To this end, the gate terminal of the second switching device Tr2 provided in the k-th stage is connected to the source terminal of the pull-up switching device Trpu provided in the k + 1th stage, and the source terminal supplies a power supply for discharging. The drain terminal is connected to the node n of the kth stage.

For example, the second switching device Tr2 provided in the second stage ST2 may respond to the node n of the second stage ST2 in response to the third scan pulse Vout3 from the third stage ST3. ) Is discharged to the discharge voltage source VSS.

The third switching device Tr3 provided in the discharge unit DU of the kth stage outputs a clock pulse supplied to itself in response to the charging voltage source VDD charged in the node n of the kth stage. do. The clock pulse is supplied to the gate terminal of the fourth switching device Tr4 provided in the kth stage. To this end, the gate terminal of the third switching device Tr3 provided in the k-th stage is connected to the node n, the drain terminal is connected to the clock transmission line for transmitting the clock pulse, and the source terminal It is connected to the gate terminal of the fourth switching device Tr4.

For example, in response to the charging voltage source VDD supplied to the node n, the third switching device Tr3 included in the second stage ST2 of FIG. Supply to the gate terminal of Tr4).

The fourth switching device Tr4 included in the discharge unit DU of the kth stage responds to the clock pulse from the third switching device Tr3 of the kth stage, thereby discharging the voltage source VSS for discharge. The gate terminal of the seventh switching device Tr7 provided in the kth stage is supplied. To this end, the gate terminal of the fourth switching device Tr4 provided in the kth stage is connected to the drain terminal of the third switching device Tr3, and the drain terminal of the seventh switching device Tr7. And a source terminal is connected to a discharge power transmission line for transmitting the discharge voltage source VSS.

  For example, the fourth switching device Tr4 included in the second stage ST2 of FIG. 4 receives the discharge voltage source VSS in response to the clock pulse from the third switching device Tr3. Supply to the gate terminal of the switching element Tr7.

The fifth switching device Tr5 provided in the discharge unit DU of the kth stage responds to a clock pulse to supply the discharge voltage source VSS to the gate terminal of the seventh switching device Tr7 provided in the kth stage. To feed. To this end, the gate terminal of the fifth switching element Tr5 provided in the kth stage is connected to the clock transmission line for transmitting the clock pulse, and the drain terminal of the fifth switching element Tr5 is connected to the gate terminal of the seventh switching element Tr7. And, the source terminal is connected to the discharge power transmission line for transmitting the discharge voltage source (VSS).

For example, the fifth switching device Tr5 included in the second stage ST2 of FIG. 4 sets the discharge voltage source VSS to the seventh switching device Tr7 in response to the first clock pulse CLK1. To the gate terminal.

The sixth switching device Tr6 provided in the discharge unit DU of the kth stage supplies the clock pulse to the gate terminal of the seventh switching device Tr7 provided in the kth stage in response to a clock pulse. . To this end, the gate terminal and the drain terminal of the sixth switching device Tr6 provided in the kth stage are connected to the clock transmission line for transmitting the clock pulse, and the source terminal of the seventh switching device Tr7. It is connected to the gate terminal.

For example, the sixth switching device Tr6 included in the second stage ST2 of FIG. 4 may transmit the second clock pulse CLK2 to the seventh switching device CLK2 in response to a second clock pulse CLK2. Supply to the gate terminal of Tr7).

The seventh switching device Tr7 included in the discharge unit DU of the kth stage includes an output from the fourth switching device Tr4, an output from the fifth switching device Tr5, and the sixth switching device. It is turned on or off depending on the output from Tr6. In operation, the discharge voltage source VSS from the gate line is supplied to the node n of the k-th stage. To this end, the gate terminal of the seventh switching device Tr7 provided in the kth stage is connected to the drain terminals of the fourth and fifth switching devices Tr4 and Tr5 and the sixth switching device Tr6. Is connected to the source terminal. The drain terminal of the seventh switching element Tr7 is connected to the node n, and the source terminal is connected to the gate line.

For example, the seventh switching device Tr7 included in the second stage ST2 of FIG. 4 is turned on in response to the outputs of the fourth, fifth, and sixth switching devices Tr4, Tr5, and Tr6. It is turned on or off, and supplies the discharge voltage source VSS from the second gate line GL2 to the node n at turn-on.

The operation of the shift register according to the embodiment of the present invention configured as described above is as follows.

FIG. 5 is a diagram illustrating the first to third stages of FIG. 2.

First, the operation during the initial period T0 will be described.

During the initial period TO, as shown in FIG. 3, only the start pulse Vst and the second clock pulse CLK2 are kept high and the first clock pulse CLK1 is kept low.

The start pulse Vst is input to the first stage ST1. Specifically, the start pulse Vst is supplied to the gate terminal of the first switching device Tr1 provided in the first stage ST1.

Then, the first switching device Tr1 of the first stage ST1 is turned on, and at this time, the charging voltage source VDD is turned on through the turned-on first switching device Tr1. It is supplied to the node n of ST1). Accordingly, the node n of the first stage ST1 is charged by the charging voltage source VDD, and the pull-up switching device Trpu and the third having the gate terminal connected to the charged node n are connected to each other. The switching element Tr3 is turned on.

On the other hand, since there is no output from the second stage ST2 in this initial period T0, the second switching element Tr2 of the first stage ST1 is turned off. In addition, since the second clock pulse CLK2 is in the low state during this initial period T0, the pull-down switching device Trpd and the fifth switching device Tr5 of the first stage ST1 are turned off. In addition, since the first clock pulse CLK1 is also low in this initial period T0, the fourth and sixth switching elements Tr4 and Tr6 of the first stage ST1 are also turned off.

Next, the operation during the first period T1 will be described.

During the first period T1, as shown in FIG. 3, only the first clock pulse CLK1 is kept high, and the start pulse Vst and the second clock pulse CLK2 are kept low. .

Therefore, the first switching device Tr1 of the first stage ST1 is turned off in response to the start pulse Vst in the low state.

At this time, as the first switching device Tr1 is turned off, the node n of the first stage ST1 is maintained in a floating state. Therefore, the node n of the first stage ST1 is kept in the charged state by the charging voltage source VDD which has been applied during the initial period T0.

Accordingly, the pull-up switching device Trpu and the third switching device Tr3 of the first stage ST1 having the gate terminal connected to the node n are turned on.

In this case, the first clock pulse CLK1 is supplied to each of the drain terminals of the turned-on pull-up switching device Trpu and the third switching device Tr3. Then, the charging voltage source VDD charged in the node n of the first stage ST1 is amplified (bootstrapping phenomenon bootstrapping).

Therefore, the first clock pulse CLK1 supplied to the drain terminal of the pull-up switching device Trpu provided in the first stage ST1 is stably output through the source terminal of the pull-up switching device Trpu. The first clock pulse CLK1 output from the pull-up switching device Trpu is the first scan pulse Vout1.

In the meantime, the first clock pulse CLK1 is supplied to the gate terminal and the drain terminal of the sixth switching element Tr6 of the first stage ST1 in the first period T1. The sixth switching device Tr6 is also turned on at T1). Then, the first clock pulse is supplied to the gate terminal of the seventh switching device Tr7 of the first stage ST1 through the turned-on sixth switching device Tr6.

The first period T1 is an output period of the first stage ST1. When the seventh switching element Tr7 is turned on during the first period T1, the node n discharges. do. Then, the scan pulse may not be properly output from the pull-up switching device Trpu in the first period T1.

In order to prevent this, the third and fourth switching devices Tr3 and Tr4 of the first stage ST1 may not turn on the seventh switching device Tr7 during the first period T1. do.

That is, the third switching device Tr3 outputs the first clock pulse CLK1 to the gate terminal of the fourth switching device Tr4 during the first period T1. Then, the fourth switching device Tr4 is turned on, and the discharge voltage source is supplied to the gate terminal of the seventh switching device Tr7 through the turned-on fourth switching device Tr4.

Accordingly, in the gate terminal of the seventh switching device Tr7 during the first period T1, the first clock pulse CLK1 and the fourth switching device Tr4 from the sixth switching device Tr6 are applied. Discharge voltage source VSS is supplied simultaneously. At this time, since the area (channel width) of the fourth switching device Tr4 is larger than that of the sixth switching device Tr6, the seventh switching device Tr7 has a larger area. It is turned off by the voltage source VSS for discharge from Tr4. Therefore, in the first period T1, the node n of the first stage may maintain a charged state, and the pull-up switching device Trpu provided in the first stage ST1 may stably have a first scan pulse. (Vout) can be output.

The first scan pulse Vout1 output from the first stage ST1 is supplied to the first gate line GL1 and serves as a scan pulse for driving the first gate line GL1.

In addition, the first scan pulse Vout1 output from the pull-up switching device Trpu of the first stage ST1 is supplied to the second stage ST2 to supply the node n of the second stage ST2. It acts as a start pulse Vst for charging.

That is, in the first period T1, the first scan pulse Vout1 output from the first stage ST1 is supplied to the gate terminal of the first switching element Tr1 provided in the second stage ST2. .

Accordingly, the node n of the second stage ST2 is charged by the charging voltage source VDD.

Meanwhile, as the first clock pulse CLK1 changes to a low state at the end of the first period T1, the first clock pulse in the low state through the turned-on third switching device Tr3. CLK1 is supplied to the fourth switching element Tr4. Accordingly, before the second period T2 starts, the fourth switching device Tr4 is turned off.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 3, only the second clock pulse CLK2 remains high. On the other hand, the start pulse Vst, the first clock pulse CLK1, and the first scan pulse Vout1 are kept low.

Accordingly, the first switching device Tr1 of the second stage ST2 is turned off in response to the first scan pulse Vout1 in the low state.

At this time, as the first switching device Tr1 is turned off, the node n of the second stage ST2 is maintained in a floating state.

Therefore, the node n of the second stage ST2 is continuously maintained in the charging state by the charging voltage source VDD applied during the first period T1. Accordingly, the pull-up switching device Trpu and the third switching device Tr3 of the second stage ST2 having the gate terminal connected to the node n are turned on.

In this case, the second clock pulse CLK2 is supplied to each of the drain terminals of the turned-on pull-up switching device Trpu and the third switching device Tr3. Then, the charging voltage source VDD charged in the node n of the second stage ST2 is amplified (bootstrapping phenomenon bootstrapping).

Therefore, the second clock pulse CLK2 supplied to the drain terminal of the pull-up switching device Trpu provided in the second stage ST2 is stably output through the source terminal of the pull-up switching device Trpu. The second clock pulse CLK2 output from the pull-up switching device Trpu is the second scan pulse Vout2.

The second scan pulse Vout2 output from the second stage ST2 acts as a scan pulse supplied to the second gate line GL2 to drive the second gate line GL2, and the third stage. It is supplied to ST3 and acts as a start pulse Vst for charging the node n of the third stage ST3.

In addition, the second scan pulse Vout2 output from the second stage ST2 in the second period T2 is supplied to the first stage ST1 to supply the node n of the first stage ST1. It serves to discharge. That is, the first stage ST1 is disabled in response to the second scan pulse Vout2 from the second stage ST2. If this is explained in more detail as follows.

The second scan pulse Vout2 output from the second stage ST2 in the second period T2 is supplied to the gate terminal of the second switching element Tr2 provided in the first stage ST1.

Then, the second switching device Tr2 is turned on, and the discharge voltage source VSS is connected to the node n of the first stage ST1 through the turned-on second switching device Tr2. Supplied. Then, the node n is discharged, and the pull-up switching device Trpu and the third switching device Tr3 having the gate terminal connected to the discharged node n are turned off.

In addition, the second clock pulse CLK2 output in the second period T2 is supplied to the pull-down switching device Trpd provided in the first stage ST1. Accordingly, the pull-down switching device Trpd is turned on. The discharge voltage source VSS is supplied to the first gate line GL1 through the turned on pull-down switching device Trpd. Accordingly, the first gate line GL1 is discharged.

In addition, the second clock pulse CLK2 output in the second period T2 is supplied to the gate terminal of the fifth switching device Tr5 provided in the first stage ST1. Then, the fifth switching device Tr5 is turned on, and a room voltage source is supplied to the gate terminal of the seventh switching device Tr6 through the turned-on fifth switching device Tr5. Accordingly, the seventh switching device Tr7 is maintained in the turned off state.

In this manner, in the third period T3, the third stage ST3 outputs the third scan pulse Vout3.

At this time, the first clock pulse CLK1 is kept high and the second clock pulse CLK2 is kept low in the third period T3.

The first clock pulse CLK1 in the high state output in the third period T3 is also supplied to the first stage ST1.

That is, the first clock pulse CLK1 may include drain terminals of the pull-up switching device Trpu and the third switching device Tr3 and the sixth switching device Tr6 of the first stage ST1. It is supplied to the gate terminal and the drain terminal.

Since the third period T3 is a non-output period of the first stage ST1, the node n of the first stage ST1 is in a discharged state during the third period T3. Therefore, in the third period T3, both the pull-up switching device Trpu and the third switching device Tr3 are turned off. In addition, since the second clock pulse CLK2 is in the low state during the third period T3, the fourth and fifth switching elements Tr4 and Tr5 are also turned off.

Therefore, only the sixth switching device Tr6 to which the first clock pulse CLK1 of the high state is supplied to the gate terminal is turned on.

The first clock pulse CLK1 is supplied to the gate terminal of the seventh switching device Tr7 through the turned-on sixth switching device Tr6. Then, the seventh switching element Tr7 is turned on, and the discharge voltage source VSS from the first gate line GL1 is transferred to the first stage through the turned-on seventh switching element Tr7. It is supplied to the node n of ST1. Thus, the node n is discharged.

As such, whenever the clock pulse is supplied to each stage in the non-output period, the seventh switching element Tr7 is turned on to discharge the node of each stage. Therefore, it is possible to prevent the voltage from accumulating at the node n according to the coupling phenomenon.

FIG. 6 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

The circuit configuration shown in FIG. 6 is the same as the circuit configuration shown in FIG. 4, and only the connection relationship of the seventh switching element Tr7 is different.

That is, as shown in Fig. 6, the source terminal of the seventh switching element Tr7 is not connected to the gate line, but instead is connected to the discharge power transmission line.

For example, as shown in FIG. 6, the source terminal of the seventh switching element of the second stage ST2 is not connected to the second gate line GL2, but instead is connected to the discharge power transmission line.

Accordingly, the seventh switching element Tr7 supplies the discharge voltage source VSS from the discharge power transmission line to the node n in the non-output period to discharge the node n.

FIG. 7 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

The circuit configuration shown in FIG. 7 is the same as the circuit configuration shown in FIG. 4 and further includes only the eighth switching element Tr8.

The eighth switching device Tr8 discharges the node n by supplying a discharge voltage source VSS to the node n in response to the start pulse Vst.

The eighth switching device Tr8 is provided in the remaining stages except the first stage ST1, that is, the stage that first outputs the scan pulse within one frame period. In other words, the eighth switching device Tr8 is not provided in the first stage ST1.

When the start pulse Vst is output, the node n of the remaining stages except the first stage ST1 is discharged.

 FIG. 8 is a diagram illustrating another circuit configuration of the second stage of FIG. 2, wherein the circuit configuration illustrated in FIG. 8 includes the seventh switching element Tr7 illustrated in FIG. 6 and the eighth illustrated in FIG. 7. And a switching element Tr8.

FIG. 9 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

The circuit configuration shown in Fig. 9 is the same as the circuit configuration shown in Fig. 8, and only the connection relationship of the pull-down switching element Trpd is different.

That is, as shown in Fig. 9, the gate terminal of the pull-down switching element Trpd is not connected to the clock transmission line, but instead is connected to the gate terminal of the seventh switching element Tr7.

For example, as shown in FIG. 9, the gate terminal of the pull-down switching device Trpd of the second stage ST2 is not connected to the clock transmission line that transmits the second clock pulse CLK2, but instead the seventh gate. It is connected to the gate terminal of the switching element Tr7.

Therefore, the pull-down switching device Trpd operates in the same manner as the seventh switching device Tr7. That is, the pull-down switching device Trpd is turned on together when the seventh switching device Tr7 is turned on, and is turned off together when the seventh switching device Tr7 is turned off.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The shift register according to the present invention as described above has the following effects.

The shift register of the present invention includes a discharge portion.

The discharge unit periodically discharges the node of the stage every time a clock pulse is supplied to the pull-up switching device of the stage in the non-output period of the stage, thereby preventing multiple outputs due to the coupling phenomenon.

Claims (10)

It includes a plurality of stages that sequentially output the scan pulse to the plurality of gate lines, At least one stage, A pull-up switching device which is turned on or turned off according to a logic state of a signal supplied to a node, receives a first clock pulse to output a scan pulse, and supplies the scan pulse to a gate line; A pull-down switching device configured to output a discharge voltage source and supply the discharge voltage source to the gate line in response to a first control signal from the outside; A node controller for controlling a logical state of the node; And, And a discharge unit for discharging the node each time a first clock pulse is supplied to the pull-up switching element during a non-output period in which the stage does not output a scan pulse. The method of claim 1, The node controller provided in the nth stage (n is a natural number), A first switching element for supplying a charging voltage source to a node of the nth stage in response to a scan pulse from a pth stage (p is a natural number smaller than n); And, And a second switching element for supplying a discharge voltage source to the node of the nth stage in response to a scan pulse from the qth stage (q is a natural number greater than n). The method of claim 2, The discharge unit provided in the nth stage, A third switching device configured to output a first clock pulse to the node in response to a charging voltage source; A fourth switching device for outputting a discharge voltage source in response to the first clock pulse from the third switching device; A fifth switching device for outputting the discharge voltage source according to a second control signal from the outside; A sixth switching element configured to output the first clock pulse in response to the first clock pulse; And, And a seventh switching element which is turned on or off according to the output from the fourth, fifth and sixth switching elements, and supplies a voltage source for discharging to the node at turn-on. register. The method of claim 3, wherein And the seventh switching element supplies a discharge voltage source from the discharge power transmission line to the node. The method of claim 3, wherein And the seventh switching element supplies a voltage source for discharge from the gate line to the node. The method of claim 3, wherein And the second control signal is a second clock pulse having a phase difference from the first clock pulse. The method of claim 3, wherein And the second control signal is a scan pulse from a next stage. The method of claim 3, wherein And the first control signal is a signal supplied to a gate electrode of the seventh switching element. The method of claim 3, wherein The node control unit of the remaining stages except for the first stage which first outputs the scan pulse within one frame period of the stages, And an eighth switching device for supplying a discharge voltage source to the node in response to a start pulse from the outside. The method of claim 1, And the first control signal is a second clock pulse having a phase difference from the first clock pulse.

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