KR20080060366A - Method for manufacturing non volatile memory device - Google Patents

Abstract

A method for manufacturing a non-volatile memory device is provided to reduce interference between adjacent cells by increasing a gap between adjacent floating gates on a substrate. An active region and a field region are defined on a substrate(10). A recess part is formed by etching a part of the substrate corresponding to the active region. A gate insulating layer(18) is formed along a surface step of the substrate formed through the recess part. A conductive layer for floating gate is formed along the surface step on the gate insulating layer. A hard mask is buried into a stepped part formed by the conductive layer. A floating gate(19A) is formed by etching the conductive layer exposed by the hard mask, to expose the gate insulating layer.

Description

Non-volatile memory device manufacturing method {METHOD FOR MANUFACTURING NON VOLATILE MEMORY DEVICE}

1A to 1I are cross-sectional views illustrating a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

2 is a plan view illustrating a flash memory cell array in accordance with an embodiment of the present invention.

3 is a plan view of a flash memory cell array in which a floating gate is formed in accordance with FIG. 1G;

4 is an enlarged perspective view of a floating gate formed according to an embodiment of the present invention.

   <Description of the symbols for the main parts of the drawings>

10 substrate 11 screen insulating film

12 pad nitride film 13 pad oxide film

14 silicon oxynitride film 15 trench

16 device isolation layer 17 recessed portion

18 gate insulating film 19 conductive film for floating gate

20: hard mask 19A: floating gate

21 dielectric film 22 control gate

A: active area B: field area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device manufacturing technology, and more particularly, to a method of manufacturing a nonvolatile memory device, and more particularly, a flash memory device having a floating gate.

Semiconductor memories are classified into volatile memory, in which stored information is lost when electricity supply is interrupted, and non-volatile memory, which can maintain information even when electricity supply is interrupted. Nonvolatile memories include erasable programmable read only memory (EPROM), electrically EPROM (EEPROM), and flash memory.

In particular, in recent years, there is an increasing demand for flash memory devices that can be electrically programmed and erased and that do not require a refresh function to rewrite data at regular intervals. In order to develop a large-capacity memory device capable of storing a large amount of data, researches on a high integration technology of the memory device have been actively conducted. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of removing data written to the memory cell.

On the other hand, in recent years, research on high integration technology of flash memory devices has been actively conducted in order to develop a large capacity memory device capable of storing a large amount of data at one time. As a result of this high integration, the design rule of the device is reduced, and as a result, the gate length is also reduced as the size of the device decreases. As a result, short channel effects caused by decreasing channel lengths are increased.

Therefore, a flash memory cell is manufactured using a general stack structure, for example, a flash memory cell having a structure in which a floating gate, a dielectric layer, and a control gate are sequentially stacked on a substrate. As the decrease of, the short channel effect is inevitably increased, resulting in high integration of the device.

In addition, when manufacturing a flash memory device using such a stack structure, as the design rule decreases, the spacing between neighboring floating gates decreases, and according to a pass voltage applied to a cell that should not be programmed during a program operation, The problem that the threshold voltage increases abnormally occurs. This is because, as the spacing between neighboring floating gates decreases, an interference phenomenon in which the amount of charge increases in the floating gate of the actually programmed cell is easily generated due to the pass voltage of the neighboring cells.

Accordingly, an object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of minimizing interference between neighboring cells in a highly integrated nonvolatile memory device.

According to an aspect of the present invention, there is provided a substrate including an active region and a field region, etching a portion of the substrate of the active region to form a recess, and the recess. Forming a gate insulating film along the substrate surface step formed through the portion, forming a conductive film for the floating gate along the surface step on the gate insulating film, and forming a hard mask embedded in the stepped portion formed by the conductive film. And etching the conductive film exposed by the hard mask to expose the gate insulating layer to form a floating gate.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity and may be formed directly on other layers or substrates when referred to as being on another layer or substrate. Or a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals (reference numbers) throughout the specification represent the same components.

Example

1A to 1I are cross-sectional views illustrating a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention. Here, for the convenience of description, process cross-sections cut in the word line direction will be shown in FIGS. 1A to 1C, and process cross-sections cut in the bit line direction will be shown in FIGS. 1D to 1G.

First, as shown in FIG. 1A, a screen insulating film 11 is formed on a substrate 10. The screen insulating layer 11 prevents damage to the upper surface of the exposed substrate 10 during a diffusion process (or ion implantation process) for forming subsequent well regions. In this case, the screen insulating layer 11 is formed of a silicon oxide film (SiO ₂ ) using a wet, dry, or radical oxidation process. For example, it is formed to a thickness of 50 ~ 100Å by a thermal oxidation process using O ₂ gas at a temperature of 900 ℃.

Subsequently, the pad nitride film 12 and the pad oxide film 13 are sequentially formed on the screen insulating film 11. Here, the pad nitride film 12 is deposited using nitrogen, DCS (DiCloroSilane, SiH ₂ Cl ₂ ), and NH ₃ gas at a temperature of 760 ° C. and a pressure of 0.35 Torr. At this time, the flow rate of nitrogen is preferably 50 cc, the flow rate of SiH ₂ Cl ₂ is 90 cc, and the flow rate of NH ₃ is 900 cc. The pad nitride film 12 is formed to a thickness of 500 kPa. The pad oxide film 13 is formed to a thickness of 300 kPa.

Subsequently, a silicon oxynitride film 14 is formed on the pad oxide film 13 using a hard mask for device isolation. At this time, the silicon oxynitride film 14 is preferably formed to a thickness of 300 kPa.

Subsequently, a well-known shallow trench isolation (STI) etching process is performed to continuously etch the silicon oxynitride film 14, the pad oxide film 13, the pad nitride film 12, the screen insulating film 11, and a part of the substrate 10. To form the trench 15. At this time, the trench 15 is formed to a depth of about 2000Å. In this STI etching process, CF ₄ , C ₂ F ₆ , C ₄ F ₈ , C ₄ F ₆ , C ₅ F ₈ , CF ₃ H, CF ₂ H ₂ , CFH ₃ , C ₂ HF ₅ , NF ₃ , SF At least one gas selected from the group of ₆ and CF ₃ Cl is used. Further, the addition can be carried out by the addition of H ₂ and O ₂ gas.

Subsequently, as shown in FIG. 1B, the device isolation layer 16 is deposited to fill the trench 15 (see FIG. 1A). Here, the device isolation layer 16 is deposited by an oxide film material having excellent gap-fill characteristics, for example, an HDP oxide film deposited by a high density plasma (HDP) method. At this time, the HDP oxide film is preferably deposited to a thick thickness of 5000 ~ 8000Å.

Subsequently, a thermal process can be performed in nitrogen atmosphere. This thermal process is preferably carried out at least 30 minutes at a temperature of 1050 ℃.

Subsequently, a chemical mechanical polishing (CMP) process is performed to remove all of the oxide material on the pad nitride film 12. That is, the CMP process removes the pad oxide film 13 (see FIG. 1A) and the silicon oxynitride film 14 (see FIG. 1A) on the pad nitride film 12 using the pad nitride film 12 as the polishing stop film. For example, the CMP process proceeds as follows.

First, the HDP oxide film is polished to a predetermined thickness with a silica slurry to remove a large step, and then the step of separating the device isolation layer 16 between the cell region and the peripheral region is performed with a ceria slurry. Remove That is, since the ceria slurry has a higher polishing selectivity of the silicon nitride film than the HDP oxide film, but the step removal ability is significantly lower than that of the silica slurry, the HDP oxide film is first polished with the silica slurry before using the ceria slurry.

Subsequently, as shown in FIG. 1C, both the pad nitride film 12 (see FIG. 1B) and the screen insulating film 11 (see FIG. 1B) are removed. As a result, the device isolation film 16 having a portion protruded onto the substrate 10 is completed.

In this case, the pad nitride layer 12 is removed using a phosphoric acid solution (H ₃ PO ₄ ), and the screen insulating layer 11 is removed with a hydrofluoric acid (HF) solution. Although not shown in the drawings, a buffered oxide etchant (BOE) solution may be used to remove residual material remaining on the pad nitride film 12, for example, an oxide film, before the pad nitride film 12 is removed. A used wet dip out process can also be performed.

As described above, FIGS. 1A to 1C are cut and illustrated in the word line direction, that is, along the line II ′ shown in FIG. 2. 2 is a plan view illustrating a flash memory cell array according to an exemplary embodiment of the present invention. Hereinafter, cross-sectional views (FIGS. 1D to 1F, 1H and 1I) and III shown in FIG. 3 are cut in the bit line direction of the flash memory cell array, that is, along the II-II 'cut line shown in FIG. A method of manufacturing a flash memory device according to an exemplary embodiment of the present invention will be described with reference to FIG. 1G taken along the line III ′.

Subsequently, as shown in FIG. 2, a mask M is formed on the substrate 10 of the active region A. FIG. Here, the mask M is for recessing a part of the substrate 10 of the active region A except for the field region B. FIG.

Subsequently, as illustrated in FIG. 1D, the substrate 10 exposed through the mask M illustrated in FIG. 2 is etched to form a plurality of recesses 17 in the substrate 10 of the active region. During the etching process for forming the recess 17, CF ₄ , C ₂ F ₆ , C ₄ F ₈ , C ₄ F ₆ , C ₅ F ₈ , CF ₃ H, CF ₂ H ₂ , CFH ₃ , C One gas selected from the group of ₂ HF ₅ , NF ₃ , SF ₆ and CF ₃ Cl is used. Further, the addition can be carried out by the addition of H ₂ and O ₂ gas. At this time, the recess 17 is formed to have a depth of 800 ~ 1500Å.

Subsequently, as shown in FIG. 1E, the gate insulating layer 18 is formed along the stepped top surface of the substrate 10 including the recess 17 (see FIG. 1D). In this case, the gate insulating film 18 is preferably formed to a thickness of 50 ~ 100Å using an oxide-based material.

Next, a thick floating gate conductive film 19 is deposited along the steps above the gate insulating film 18. Here, the conductive film 19 is formed of a doped or undoped polysilicon film. Preferably, the thickness of the gate conductive layer 19 is formed to a thickness of about 1000 ~ 2000Å in consideration of the thickness to be etched during the subsequent etching of the gate conductive film 19.

Subsequently, a hard mask 20 is deposited on the gate conductive film 19. In this case, the hard mask 20 uses a silicon nitride film (Si ₃ N ₄ ). In particular, the hard mask 20 is deposited so that the step portion generated when the step difference caused by the recess portion 17 formed in the substrate 10 is transferred to the gate conductive film 19 as it is is embedded. In particular, it is preferable to deposit a thickness of about 500 ~ 1000 증착 in consideration of the thickness removed during the subsequent CMP process.

Subsequently, as shown in FIG. 1F, the CMP process is performed to remove the hard mask 20 on the conductive film 19. As a result, the hard mask 20 is formed in an isolated form in the stepped portion.

In such a CMP process, the dishing of the conductive film 19 should be 50 kPa or less. To this end, in the CMP process, a ceria slurry having a polishing selectivity of the silicon nitride film constituting the hard mask 20 with respect to the polysilicon film constituting the conductive film 19 is 0.5 to 1: 1. At this time, the polishing selectivity ratio of the silicon nitride film to the polysilicon film is determined according to the dilution ratio of the slurry used in the CMP process, where the dilution ratio is the ratio of deionized water (DI Water) to abrasive 1 Say dilution ratio.

Table 1 below shows the polishing selectivity of the silicon nitride film with respect to the polysilicon film according to the dilution ratio of the ceria slurry (dilution ratio of deionized water to ceria abrasive 1) used in the CMP process.

Dilution ratio Polishing selection ratio (polysilicon: silicon nitride film) 1:30 0.91: 1 1:40 0.82: 1 1:50 0.79: 1 1:70 0.72: 1 1: 100 0.7: 1

Therefore, in the embodiment of the present invention, the dilution ratio of the ceria slurry is adjusted to 1:10 to 1: 200 so that the polishing selectivity of the silicon nitride film to the polysilicon film is 0.5 to 1: 1.

Next, as illustrated in FIGS. 1G and 3, a dry etching process using the hard mask 20 is performed to etch conductive films 19 (see FIG. 1F) exposed to both sides of the hard mask 20. As a result, the lower portion is embedded in the recess 17 (see FIG. 1D), and the upper portion protrudes onto the substrate 10, and a floating gate 19A having an uneven shape having an upper width smaller than the lower width is formed.

In particular, the dry etching process is carried out by applying a pressure of 5 ~ 1000mTorr and RF power of 200 ~ 1000W within a temperature range of 10 ~ 100 ℃. In addition, the dry etching process is CF ₄ , C ₂ F ₆ , C ₄ F ₈ , C ₄ F ₆ , C ₅ F ₈ , CF ₃ H, CF ₂ H ₂ , CFH ₃ , C ₂ HF ₅ , NF ₃ , SF _{It is} carried out by adding O ₂ gas to any one source gas selected from the group of ₆ and CF ₃ Cl. Preferably, the flow rate of the source gas is 100 ~ 300 slm and the flow rate of O ₂ gas is 100 ~ 500 slm.

3 is a plan view illustrating a flash memory cell array in which a floating gate 19A is formed in accordance with FIG. 1G, and FIG. 1G is a cross-sectional view taken along the line III-III ′ of FIG. 3. 4 is an enlarged perspective view of the floating gate 19A. 1G, 3, and 4, since the floating gate 19A is formed to have a significantly narrower width (W ₂ <W ₁ ) in the upper portion of the substrate 10 than in the substrate 10, the substrate 10 is formed. It can be seen that the spacing S between neighboring floating gates 19A at the top increases significantly. Through this, interference between neighboring cells can be minimized.

In addition, by increasing the upper surface length of the floating gate 19A itself, it is possible to increase the coupling ratio by increasing the contact area between the floating gate 19A and the subsequently formed control gate 22.

Subsequently, as illustrated in FIG. 1H, a separate etching process is performed to remove the hard mask 20 (see FIG. 1G). For example, the hard mask 20 is removed using a phosphoric acid solution.

Subsequently, a cleaning process is performed to remove organic impurities, oxide film impurities, metal impurities, particles, and the like. This is to prevent impurities in the periphery of the floating gate 19A and to prevent performance degradation of the floating gate 19A.

This cleaning process is carried out using at least one solution of SPM solution, BOE solution and SC-1 solution. Here, the SPM solution is a mixed solution of sulfuric acid (H ₂ SO ₄ ) and fruit water (H ₂ O ₂ ) It is preferable that the mixing ratio of the fruit to sulfuric acid is 1: 4. In addition, the SC-1 solution is a solution in which ammonia water (NH ₄ OH) and fruit water (H ₂ O ₂ ) are mixed so that the mixing ratio of fruit water to ammonia water is 1: 4.

Subsequently, as shown in FIG. 1I, the dielectric film 21 is formed along the stepped top surface of the entire structure on which the floating gate 19A is formed. For example, the dielectric film 21 is formed in a first oxide film / nitride film / second oxide film structure. At this time, it is preferable that the first oxide film is formed to a thickness of 30 to 50 GPa, the nitride film is formed to a thickness of 30 to 50 GPa, and the second oxide film is formed to a thickness of 50 to 70 GPa.

Subsequently, the control gate 22 is formed on the dielectric film 21. Here, the control gate 22 is preferably formed in a laminated structure of a polysilicon film / tungsten silicide film / hard silicon silicon oxynitride film / hard mask oxide film. In this case, the polysilicon film is preferably formed to have a thickness of 2000 kPa, the tungsten silicide film is 1000 to 1500 kPa, the silicon oxynitride film is 200 to 300 kPa, and the oxide film is 1500 to 2000 kPa.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects are obtained.

First, according to the present invention, by forming the floating gate to have a concave-convex shape having a significantly narrower width in the upper portion of the substrate than in the substrate, the distance between neighboring floating gates in the upper portion of the substrate can be increased. Through this, interference between neighboring cells may be reduced.

Secondly, according to the present invention, the contact surface between the floating gate and the control gate can be increased by increasing the length of the upper surface of the floating gate itself. Through this, the coupling ratio of the nonvolatile memory device may be increased.

Claims (16)

Providing a substrate comprising an active region and a field region; Etching a portion of the substrate in the active region to form a recess; Forming a gate insulating film along the substrate surface step formed through the recess; Forming a conductive film for a floating gate along a surface step on the gate insulating film; Forming a hard mask embedded in the stepped portion formed by the conductive film; And Etching the conductive layer exposed by the hard mask to expose the gate insulating layer to form a floating gate Nonvolatile memory device manufacturing method comprising a. The method of claim 1, After etching the conductive film, Removing the hard mask; Forming a dielectric film along a top surface of an entire structure including the conductive film; And Forming a control gate on the dielectric layer Non-volatile memory device manufacturing method further comprising. The method of claim 2, After removing the hard mask, And removing impurities and particles remaining on the floating gate. The method of claim 3, wherein Removing the impurities and particles, A method of manufacturing a nonvolatile memory device using an SPM solution in which sulfuric acid and fruit water are mixed, a buffered oxide etchant (BOE) solution, and an SC-1 solution in which ammonia water and fruit water are mixed. The method of claim 1, Before forming the recess portion, And forming an isolation layer on the substrate in the field region. The method of claim 5, wherein Forming the device isolation film, Sequentially forming a screen insulating film, a pad nitride film, and a pad oxide film on the entire surface of the substrate; Etching the pad oxide layer, the pad nitride layer, the screen insulating layer, and the substrate in the field region to form a trench; Forming an isolation layer to fill the trench; Removing the device isolation film on the pad nitride film so that the pad nitride film is exposed; And Removing the pad nitride film and the screen insulating film Nonvolatile memory device manufacturing method comprising a. The method of claim 6, Before removing the pad nitride film, And removing residues remaining on the pad nitride layer. The method according to claim 6 or 7, Removing the device isolation film on the pad nitride film, A method of manufacturing a nonvolatile memory device, comprising performing a chemical mechanical polishing process using the pad nitride film as a polishing stop film. The method of claim 8, The chemical mechanical polishing process, A method of manufacturing a nonvolatile memory device comprising using a silica slurry and sequentially using a ceria slurry. The method according to any one of claims 1 to 7, Forming a hard mask embedded in the step portion, Depositing a hard mask on the conductive film such that the step formed by the conductive film is buried; And Performing a chemical mechanical polishing process to polish the hard mask to expose the conductive layer Nonvolatile memory device manufacturing method comprising a. The method of claim 10, The chemical mechanical polishing process, And adjusting the dilution ratio of the ceria slurry so that the polishing selectivity of the hard mask with respect to the conductive film is 0.5 to 1: 1. The method of claim 11, The chemical mechanical polishing process, And dilution ratio of the ceria slurry to ceria abrasive: deionized water = 1:10 to 1: 200. The method according to any one of claims 1 to 7, Etching the conductive film, A nonvolatile memory device manufacturing method comprising performing a dry etching process using the hard mask. The method of claim 13, The dry etching process is performed by applying a pressure of 5 ~ 1000mTorr and RF power of 200 ~ 1000W at a temperature of 10 ~ 100 ℃. The method of claim 13, The dry etching process is CF ₄ , C ₂ F ₆ , C ₄ F ₈ , C ₄ F ₆ , C ₅ F ₈ , CF ₃ H, CF ₂ H ₂ , CFH ₃ , C ₂ HF ₅ , NF ₃ , SF ₆ And adding an O ₂ gas to any one source gas selected from a group of CF ₃ Cl. The method according to any one of claims 1 to 7, The floating gate is a nonvolatile memory device manufacturing method of the lower portion is buried in the recess portion while the upper portion is projected onto the substrate, the upper width is formed to be narrower than the lower width.

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