KR20080055195A - Method of fabricating liquid crystal display device - Google Patents

Abstract

A method for fabricating an LCD(Liquid Crystal Display) device is provided to reduce the number of masks by means of simultaneous photo-lithography for forming electrodes, and to raise the aperture ratio by means of the black matrix formation to an array substrate, and to control the transistor off-current by self-aligning LDD(Lightly Doped Drain). The first substrate is divided into a pixel part, the first circuit part and the second circuit part. A black matrix(207) is formed on the pixel part. A buffer layer is formed on the first substrate. An active pattern is formed at the pixel part and the first and second circuit part. A storage pattern is formed at a prescribed area of the active pattern of the pixel part. A second gate insulation layer is formed on the first substrate. A gate electrode is formed at the first circuit part. A p+ source/ drain area is formed at prescribed area of the active pattern of the first circuit part. The gate electrode is formed at the pixel part and the second circuit part. A common line(208) is formed at the pixel part. An LDD area is formed at prescribed area of the active pattern of the second circuit part and the pixel part. An ILD(Inter Layer Dielectric) is formed on the first substrate. A part of the first and second gate insulation layer and the ILD are removed, and the source/ drain area of the active pattern is exposed respectively.

Description

Manufacturing method of liquid crystal display device {METHOD OF FABRICATING LIQUID CRYSTAL DISPLAY DEVICE}

1 is a plan view schematically illustrating a structure of a general liquid crystal display device integrated with a driving circuit.

2 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

3A to 3I are cross-sectional views sequentially showing a manufacturing process along the line IIa-IIa 'of the array substrate shown in FIG.

4 is a schematic cross-sectional view of a liquid crystal display device taken along a line IIb-IIb 'of the array substrate shown in FIG.

5 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

6A to 6J are cross-sectional views sequentially illustrating a manufacturing process along a Va-Va ′ line of the array substrate illustrated in FIG. 5.

7A to 7E are plan views sequentially illustrating a manufacturing process along a line Va—Va ′ of the array substrate illustrated in FIG. 5.

8A to 8F are cross-sectional views illustrating the sixth mask process illustrated in FIGS. 6J and 7E in detail.

9 is a schematic cross-sectional view of a liquid crystal display device taken along a line Vb-Vb 'of the array substrate shown in FIG.

10 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a third exemplary embodiment of the present invention.

11A to 11G are cross-sectional views sequentially showing the manufacturing process along the line X-X 'of the array substrate shown in FIG.

** Explanation of symbols for main parts of drawings **

108,208,308: Common line 110,210,310: Array board

116,216,316: Gate line 117,217,317: Data line

118,218,318 Pixel electrodes 124 ', 224', 324 ': Active pattern

124 ", 224", 324 ": Storage Pattern 207,307: Black Matrix

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a liquid crystal display device, and more particularly, to implement a lightly doped drain (LDD) having a self-aligned structure, and to secure an aperture ratio to improve luminance. It is about manufacturing method

In today's information society, display is more important as a visual information transmission medium, and in order to gain a major position in the future, it is necessary to satisfy requirements such as low power consumption, thinning, light weight, and high definition. Liquid Crystal Display (LCD), the flagship product of Flat Panel Display (FPD), has not only the ability to satisfy these conditions of the display but also mass production. It has been established as a core parts industry that can gradually replace the existing cathode ray tube (CRT).

In general, a liquid crystal display device displays a desired image by individually supplying data signals according to image information to liquid crystal cells arranged in a matrix form to adjust a light transmittance of the liquid crystal cells. to be.

The active matrix (AM) method, which is a driving method mainly used in the liquid crystal display device, uses an amorphous silicon thin film transistor (a-Si TFT) as a switching device to drive the liquid crystal in the pixel portion. to be.

The amorphous silicon thin film transistors are actively used because they can be used at low temperature and can use a low-cost insulating substrate.

However, in general, the electrical mobility of the amorphous silicon thin film transistor is limited to use in peripheral circuits requiring high-speed operation of 1 MHz or more. As a result, studies are being actively carried out to simultaneously integrate the pixel portion and the driving circuit portion on a glass substrate using a polycrystalline silicon (poly-Si) thin film transistor having a larger field effect mobility than the amorphous silicon thin film transistor. It's going on.

The polycrystalline silicon thin film transistor technology has a low photosensitivity and a high field effect mobility, so that a driving circuit can be manufactured directly on a substrate.

Increasing the mobility may improve the operating frequency of the driving circuit unit that determines the number of driving pixels, thereby facilitating high definition of the display device. In addition, due to the reduction in the charging time of the signal voltage of the pixel portion, the distortion of the transmission signal may be reduced, thereby improving image quality.

Hereinafter, the structure of the liquid crystal display will be described in detail with reference to FIG. 1.

1 is a plan view schematically illustrating a structure of a general liquid crystal display device, and illustrates a driving circuit-integrated liquid crystal display device in which a driving circuit unit is integrated on an array substrate.

As shown in the figure, the liquid crystal display is largely composed of a color filter substrate 5 and an array substrate 10 and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10. .

The array substrate 10 includes a pixel portion 35, which is an image display area in which unit pixels are arranged in a matrix, and a data driving circuit portion 31 and a gate driving circuit portion 32 positioned outside the pixel portion 35. It consists of a driving circuit section (30).

In this case, although not shown in the drawing, the pixel portion 35 of the array substrate 10 is arranged on the substrate 10 vertically and horizontally to define a plurality of gate lines and data lines, the gate lines and A thin film transistor, which is a switching element formed in an intersection region of a data line, and a pixel electrode formed in the pixel region.

The thin film transistor is a switching element that applies and cuts off a signal voltage to a pixel electrode and is a type of field effect transistor (FET) that controls the flow of current by an electric field.

The driving circuit part 30 of the array substrate 10 is located outside the pixel portion 35 of the array substrate 10 protruding from the color filter substrate 5, and one side of the protruding array substrate 10. The data driving circuit part 31 is positioned at a long side, and the gate driving circuit part 32 is positioned at one end side of the protruding array substrate 10.

In this case, the data driving circuit 31 and the gate driving circuit 32 use a thin film transistor having a complementary metal oxide semiconductor (CMOS) structure, which is an inverter, in order to properly output an input signal.

For reference, the CMOS is an integrated circuit having an MOS structure which is used in a thin film transistor for driving circuits requiring high-speed signal processing. The CMOS requires both an n-channel thin film transistor and a p-channel thin film transistor. It shows the intermediate form of PMOS.

The gate driving circuit unit 32 and the data driving circuit unit 31 are devices for supplying a scan signal and a data signal to the pixel electrode through the gate line and the data line, respectively, and are connected to an external signal input terminal (not shown). It controls the external signal input through the external signal input terminal to output to the pixel electrode.

In addition, a color filter (not shown) for implementing color and a common electrode (not shown), which is an opposite electrode of the pixel electrode formed on the array substrate 10, are formed in the pixel part 35 of the color filter substrate 5. have.

The color filter substrate 5 and the array substrate 10 configured as described above are provided with a cell gap so as to be uniformly spaced apart by a spacer (not shown), and a seal formed at an outer portion of the pixel portion 35. The patterns are bonded by a seal pattern (not shown) to form a unit liquid crystal display panel. At this time, the bonding of the color filter substrate 5 and the array substrate 10 is performed through a bonding key formed on the color filter substrate 5 or the array substrate 10.

The driving circuit-integrated liquid crystal display device configured as described above has the advantage of excellent device characteristics, excellent image quality, high definition, and low power consumption because it uses polycrystalline silicon thin film transistors.

However, since the n-channel thin film transistor and the p-channel thin film transistor must be formed together on the same substrate, the driving circuit-integrated liquid crystal display device is more complicated in manufacturing process than the amorphous silicon thin film transistor liquid crystal display device forming only a single type channel. There are disadvantages.

As such, fabrication of an array substrate including the thin film transistor requires a plurality of photolithography processes.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development processes. There is a downside to dropping.

In particular, a mask designed to form a pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion thereto.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and manufactures a thin film transistor by removing the contact hole mask process for connecting the pixel electrode and the drain electrode and simultaneously forming the pixel electrode and the source / drain electrode through one mask process. It is an object of the present invention to provide a method for manufacturing a liquid crystal display device having a reduced number of masks used in the apparatus.

Another object of the present invention is to provide a method of manufacturing a liquid crystal display device having improved aperture ratio by forming a black matrix on the array substrate that requires alignment margin.

Another object of the present invention is to provide a method of manufacturing a liquid crystal display device implementing an LED having a self-aligning structure.

Further objects and features of the present invention will be described in the configuration and claims of the invention which will be described later.

In order to achieve the above object, the manufacturing method of the liquid crystal display device of the present invention comprises the steps of providing a first substrate divided into a pixel portion, a first circuit portion and a second circuit portion; Forming a black matrix on the pixel portion; Forming a buffer layer on the first substrate; Forming an active pattern on the pixel portion and the first and second circuit portions, and forming a storage pattern on a predetermined region of the active pattern of the pixel portion; Forming a gate insulating film on the first substrate; Forming a gate electrode on the first circuit portion, and forming a p + source / drain region on a predetermined region of the active pattern of the first circuit portion; Forming a gate electrode on the pixel portion and the second circuit portion, and forming a common line on the pixel portion; Forming an LED region in a predetermined region of an active pattern of the pixel portion and the second circuit portion; Forming an interlayer insulating film on the first substrate; Removing portions of the gate insulating layer and the interlayer insulating layer to form first contact holes and second contact holes exposing source and drain regions of the active pattern, respectively; Forming a source electrode electrically connected to the source region of the active pattern through the first contact hole, and forming a drain electrode electrically connected to the drain region of the active pattern through the second contact hole; Forming a pixel electrode electrically connected to the drain electrode; Providing a second substrate; Forming a liquid crystal layer on any one of the first substrate and the second substrate; And bonding the first substrate and the second substrate to each other.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the manufacturing method of the liquid crystal display device according to the present invention.

FIG. 2 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention. In particular, FIG. 2 illustrates one pixel including a thin film transistor of a pixel portion.

In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity.

As shown in the figure, a gate line 116 and a data line 117 are formed on the array substrate 110 of the first embodiment to be arranged on the array substrate 110 in a vertical direction to define a pixel area. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 116 and the data line 117, and is connected to the thin film transistor in the pixel area, and the common electrode of a color filter substrate (not shown). In addition, a pixel electrode 118 for driving a liquid crystal (not shown) is formed.

The thin film transistor includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 connected to the pixel electrode 118. In addition, the thin film transistor includes an active pattern 124 ′ that forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121. .

In this case, the active pattern 124 ′ of the first embodiment is formed of a polycrystalline silicon thin film, and a portion of the active pattern 124 ′ extends into the pixel region to form a first storage capacitor together with the common line 108. Is connected to the storage pattern 124 ". That is, the common line 108 is formed in the pixel area in substantially the same direction as the gate line 116, and the common line 108 is formed as a first line. The first storage capacitor is formed by overlapping the lower storage pattern 124 ″ with an insulating layer interposed therebetween. In this case, the storage pattern 124 ″ of the first embodiment is formed by storage doping through a separate mask process on the polycrystalline silicon thin film constituting the active pattern 124 ′.

The source electrode 122 and the drain electrode 123 are connected to the active pattern 124 ′ through the first contact hole 140a and the second contact hole 140b formed in the first insulating film and the second insulating film (not shown). Is electrically connected to the source region and the drain region. In addition, a portion of the source electrode 122 extends in one direction to form a portion of the data line 117, and a portion of the drain electrode 123 extends toward the pixel region to be formed in the third insulating layer (not shown). It is electrically connected to the pixel electrode 118 through the third contact hole 140c.

In this case, a part of the drain electrode 123 extending to the pixel region overlaps the common line 108 below the second insulating layer to form a second storage capacitor.

Hereinafter, a manufacturing process of the array substrate configured as described above will be described in detail with reference to the accompanying drawings.

3A to 3I are cross-sectional views sequentially illustrating a manufacturing process along the line IIa-IIa 'of the array substrate shown in FIG. 2, illustrating an example of a process of manufacturing an array substrate of a pixel portion where n-channel TFTs are formed. have. At this time, both the n-channel TFT and the p-channel TFT are formed in the circuit portion.

As shown in FIG. 3A, a buffer layer 111 and a silicon thin film are formed on a substrate 110 made of a transparent insulating material such as glass, and then the silicon thin film is crystallized to form a polycrystalline silicon thin film. Thereafter, the polycrystalline silicon thin film is patterned using a photolithography process (first mask process) to form a polycrystalline silicon thin film pattern 124 constituting an active pattern and a storage pattern.

3B, a portion of the polycrystalline silicon thin film pattern 124 is covered and then doped to form a storage pattern 124 ″. Here, the polycrystalline silicon thin film pattern 124 covered by photoresist is formed. ) Forms an active pattern 124 ', which requires another photolithography process (second mask process).

Next, as shown in FIG. 3C, the first insulating film 115a and the first conductive film are sequentially formed on the entire surface of the substrate 110, and then the first film is formed using a photolithography process (third mask process). By selectively patterning a conductive layer, a gate electrode 121 made of the first conductive layer is formed on the active pattern 124 'and a common line 108 formed of the first conductive layer on the storage pattern 124 ". To form.

The first conductive layer may include aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), and chromium to form the common line 108 with the gate electrode 121. It may be made of a low resistance opaque conductive material such as (chromium; Cr), molybdenum (Mo).

In this case, the common line 108 overlaps the lower storage pattern 124 ″ with the first insulating layer 115a therebetween in the pixel region to form a first storage capacitor.

After that, as shown in FIG. 3D, the n-channel TFT region of the front surface of the pixel portion array substrate 110 and the circuit portion are covered by the first blocking layer 170 made of photoresist (fourth mask process). High concentrations of p + ions are implanted into the p-channel TFT region to form a p + source region and a drain region.

3E, after the p-channel TFT region of the circuit portion, a portion of the n-channel TFT region and the storage region of the pixel portion / circuit portion are covered by the second blocking film 170 ′ (fifth mask process), A high concentration of n + ions is implanted into a predetermined region of the active pattern 124 'of the pixel portion to form an n + source region 124a and a drain region 124b. Here, reference numeral 124c denotes a channel region forming a conductive channel between the source region 124a and the drain region 124b.

Subsequently, the second blocking layer 170 ′ is removed, and then a low concentration of n − ions is implanted into the entire surface of the substrate 110 to form the n + source region 124a and the channel region 124c and the n + drain region 124b. A lightly doped drain (LDD) region 124l is formed between the channel region 124c and the channel region 124c.

In this case, the storage region may or may not be covered by the second blocking layer 170 ′, and n + ions are implanted in the same manner as the n-channel TFT region of the circuit unit so that the source region, the drain region, and the LED region of n + are formed. Will be formed.

Next, as shown in FIG. 3F, after depositing the second insulating film 115b on the entire surface of the substrate 110, the first insulating film 115a and the second film may be subjected to a photolithography process (sixth mask process). A portion of the insulating layer 115b is removed to form a first contact hole 140a for exposing a portion of the source region 124a and a second contact hole 140b for exposing a portion of the drain region 124b. .

As shown in FIG. 3G, the source region is formed through the first contact hole 140a by forming a second conductive layer on the entire surface of the substrate 110 and then patterning the same by using a photolithography process (seventh mask process). A source electrode 122 is formed to be electrically connected to 124a, and a drain electrode 123 is formed to be electrically connected to the drain region 124b through the second contact hole 140b. In this case, a portion of the source electrode 122 extends in one direction to form the data line 117, and a portion of the drain electrode 123 extends into the pixel region so that the second insulating layer 115b is interposed therebetween. The second storage capacitor overlaps with the common line 108 below the second storage capacitor.

Next, as shown in FIG. 3H, after depositing a third insulating film 115c on the entire surface of the substrate 110, patterning the third insulating film 115c using a photolithography process (eighth mask process). As a result, a third contact hole 140c exposing a part of the drain electrode 123 is formed.

3I, after the third conductive film is formed over the entire surface of the substrate 110 on which the third insulating film 115c is formed, the third conductive film is formed by using a photolithography process (ninth mask process). By selectively patterning, the pixel electrode 118 electrically connected to the drain electrode 123 through the third contact hole 140c is formed.

The third conductive layer may be formed of a transparent conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form the pixel electrode 118. Can be.

In this case, in the first embodiment, source / drain electrodes, data lines, and pixel electrodes are formed through separate mask processes, and contact holes are formed through another mask process, and then the pixel electrodes are formed through the contact holes. By electrically connecting the drain electrodes, the TFTs of the pixel portion and the circuit portion can be manufactured through a total of nine mask processes.

The array substrate of the first embodiment manufactured as described above is bonded to face the color filter substrate 105 by a sealant (not shown) formed on the outer side of the image display region, as shown in FIG. 4 to form a liquid crystal display device. The array substrate 110 and the color filter substrate 105 are bonded together through a bonding key (not shown) formed on the array substrate 110 and the color filter substrate 105.

In addition, a liquid crystal layer 190 is formed between the array substrate 110 and the color filter substrate 105.

In this case, the array substrate 110 and the color filter substrate 105 are formed by forming the black matrix 107 on the color filter substrate 105 to define the opening region la of the pixel. The color filter substrate 105 is designed in consideration of the alignment margin (m) of the black matrix 107 in consideration of misalignment that occurs during bonding. As a result, the opening area la is reduced to decrease the opening ratio.

For reference, reference numeral 106 denotes a color filter implementing color.

Hereinafter, the source electrode, the drain electrode, and the pixel electrode are simultaneously formed by one mask process using a diffraction mask or a half-tone mask (hereinafter, referred to as a half-tone mask in the case of referring to a diffraction mask). By reducing the number of masks by eliminating the contact hole mask process for connecting the pixel electrode and the drain electrode, the manufacturing process is simplified, and a black matrix is formed on the lower layer of the array substrate to align the alignment between the array substrate and the color filter substrate. A second embodiment of the present invention in which the margin is reduced to improve the aperture ratio will be described in detail with reference to the drawings.

FIG. 5 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention, in particular one pixel including a thin film transistor of a pixel portion.

In an actual liquid crystal display device, N gate lines and M data lines intersect and MxN pixels exist, but one pixel is shown in the figure for simplicity of explanation.

As shown in the figure, a gate line 216 and a data line 217 are formed on the array substrate 210 in the second embodiment, which are arranged horizontally and horizontally on the array substrate 210 to define a pixel area. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 216 and the data line 217, and is connected to the thin film transistor in the pixel area and is connected to a common electrode of a color filter substrate (not shown). A pixel electrode 218 for driving a liquid crystal (not shown) is formed.

The thin film transistor includes a gate electrode 221 connected to the gate line 216, a source electrode 222 connected to the data line 217, and a drain electrode 223 connected to the pixel electrode 218. In addition, the thin film transistor includes an active pattern 224 ′ that forms a conductive channel between the source electrode 222 and the drain electrode 223 by the gate voltage supplied to the gate electrode 221.

In this case, a portion of the active pattern 224 ′ formed of a polycrystalline silicon thin film extends to a pixel region to form a storage pattern 224 ″, and the storage pattern 224 ″ is defined as a predetermined portion of the active pattern 224 ′. N + ions are implanted into the region to be used as storage electrodes. In addition, a common line 208 is formed in the pixel area in substantially the same direction as the gate line 216, and the common line 208 has a gate insulating layer (not shown) interposed therebetween. The first storage capacitor is formed by overlapping the pattern 224 ″.

In addition, the source electrode 222, the drain electrode 223, and the data line 217 made of an opaque conductive material are formed of a transparent conductive material under the source electrode 222, the drain electrode 223, and A source electrode pattern 222 ′, a drain electrode pattern 223 ′, and a data line pattern 217 ′ patterned in the same shape as the data line 217 are formed.

The source electrode 222 and the drain electrode 223 of the active pattern 224 ′ may be formed through the first contact hole 240a and the second contact hole 240b formed in the gate insulating layer and the interlayer insulating layer (not shown). It is electrically connected to the source region 224a and the drain region 224b. In addition, a part of the source electrode 222 extends in one direction to form a part of the data line 217, and a part of the drain electrode pattern 223 ′ extends toward the pixel area to extend the pixel of the second embodiment. The electrode 218 is configured.

In this case, a part of the drain electrode 223 extending to the pixel region overlaps the common line 208 under the interlayer insulating layer to form a second storage capacitor.

Here, the liquid crystal display of the second embodiment can reduce the alignment margin by forming the black matrix 207 on the array substrate 210 instead of the color filter substrate, thereby increasing the opening area A of the pixel. have. That is, when the black matrix is formed on the color filter substrate, when the color filter substrate and the array substrate are bonded to each other, an alignment margin for alignment with the array substrate should be taken into consideration so that the black matrix has a margin in the black matrix. As a result, the opening area of the pixel is reduced. In this case, when the black matrix 207 is formed on the array substrate 210 as in the second embodiment, since the above-described alignment margin does not need to be considered, the black matrix 207 does not give a margin to the opening region of the pixel ( A) will increase.

In addition, as described above, the liquid crystal display of the second embodiment simultaneously forms the source electrode 222, the drain electrode 223, and the pixel electrode 218 in one mask process using a diffraction mask. Since the contact hole mask process for connecting the 218 and the drain electrode 223 'is unnecessary, an array substrate can be manufactured through a total of six mask processes, which will be described in detail with the following manufacturing method of the liquid crystal display device. .

6A to 6J are cross-sectional views sequentially illustrating a manufacturing process along the Va-Va 'line of the array substrate illustrated in FIG. 5, and FIGS. 7A to 7E are lined along the Va-Va' line of the array substrate illustrated in FIG. 5. It is a top view which shows the manufacturing process according to this sequentially.

In this case, in general, the thin film transistor formed in the pixel portion may be both n-channel or p-channel, and both the n-channel TFT and the p-channel TFT are formed in the circuit portion to form a CMOS. The method of manufacturing an n-channel TFT and a p-channel TFT is shown, for example.

6A and 7A, a first buffer layer 211 and an organic layer (or metal layer) are formed on an array substrate 210 made of a transparent insulating material such as glass, and then the organic layer (or metal layer) is formed. ) Is formed to form a black matrix 207 in the pixel portion.

The black matrix 207 is patterned on the boundary area of the pixels to block leakage of light generated from a backlight (not shown) of the lower portion of the liquid crystal display and to prevent color mixing of adjacent pixels.

In this case, since the black matrix 207 of the second embodiment is formed on the array substrate 210, it is not necessary to design in consideration of the alignment margin required when the array substrate 210 and the color filter substrate are bonded to each other.

For reference, the mask process for forming the black matrix 207 is not included in the total number of masks in the array process for manufacturing the array substrate 210.

Thereafter, as shown in FIG. 6B, a second buffer layer 211 ′ and a silicon thin film are formed on the entire surface of the array substrate 210 on which the black matrix 207 is formed, and then the silicon thin film is crystallized to polycrystalline silicon. Form a thin film.

In this case, the second embodiment has been described using a polycrystalline silicon thin film as the semiconductor layer of the thin film transistor, for example. However, the present invention is not limited thereto, and an amorphous silicon thin film may be used as the semiconductor layer of the thin film transistor. have.

In addition, the polycrystalline silicon thin film may be formed using various crystallization methods after depositing an amorphous silicon thin film on the array substrate 210. This will be described below.

First, an amorphous silicon thin film may be formed by depositing in various ways. Representative methods of depositing the amorphous silicon thin film may include low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (Plasma Enhanced). Chemical Vapor Deposition (PECVD) method.

As a method of crystallizing the amorphous silicon thin film, there are largely a solid phase crystallization (SPC) method for heat treating the amorphous silicon thin film in a high temperature furnace and an excimer laser annealing (ELA) method using a laser. .

As the laser crystallization, an excimer laser annealing method using a pulse-type laser is mainly used, but in recent years, sequential lateral solidification (SLS) in which grains are grown in a horizontal direction to improve crystallization characteristics. The method is being studied.

The polysilicon thin film is patterned using a photolithography process (first mask process) to form an active pattern 224 ′ on the pixel array substrate 210, and n-channel active on the circuit array array 210. The pattern 224n and the p channel active pattern 224p are formed.

6C and 7B, a portion of the active pattern 224 ′ of the pixel portion and all n and p-channel TFT regions of the circuit portion are covered with a first blocking film (second mask process) made of photoresist. After that, a high concentration of n + ions are implanted to form a storage pattern 224 ″ in a portion of the active pattern 224 ′ of the pixel portion.

As shown in FIG. 6D, a gate insulating film 215a and a first conductive film 230 are formed over the array substrate 210.

The first conductive layer 230 is formed of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (chromium) to form a common line with the gate electrode. Cr), molybdenum (Mo) and the like can be made of a low resistance opaque conductive material.

Next, as shown in FIG. 6E, after the entire n-channel TFT region of the pixel portion and the circuit portion and the predetermined region of the p-channel TFT region of the circuit portion are covered with a second blocking film 270 ′ made of photoresist ( 3 mask process) and selectively patterning the first conductive film under the mask using the second blocking film 270 'to form a circuit part gate electrode 221p including the first conductive film in the p-channel TFT region of the circuit part. .

A high concentration of p + ions is implanted into the p-channel TFT region of the circuit unit using the second blocking layer 270 'as a mask to form a p + source region 224pa and a drain region 224pb. Here, reference numeral 224pc denotes a p-channel region that forms a conductive channel between the p + source region 224pa and the drain region 224pb.

6F, 6G, and 7C, after covering all of the p-channel TFT region of the circuit portion and a portion of the n-channel TFT region of the pixel portion and the circuit portion with the third blocking film 270 ″ (fourth mask). Process) and patterning the first conductive film under the mask using the third blocking film 270 ″ to form the pixel portion gate electrode 221 and the circuit portion gate electrode 221n in the n-channel TFT region of the pixel portion and the circuit portion, respectively. At the same time, the common line 208 is formed on the storage pattern 224 ″.

In this case, the pixel portion gate electrode 221, the circuit portion gate electrode 221n, and the common line 208 may overetch the first conductive layer using wet etching to form a third blocking layer 270 ″ on the upper portion thereof. You can make it narrower than).

The common line 208 of the pixel portion overlaps the lower storage pattern 224 ″ with the gate insulating layer 215a therebetween to form a first storage capacitor.

Subsequently, n + source regions 224a and 224na and drain regions 224b and 224nb are formed by implanting high concentrations of n + ions into the n-channel TFT region of the pixel portion and the circuit portion using the third blocking layer 270 ″ as a mask. Here, reference numerals 224c and 224nc denote n-channel regions that form conductive channels between the n + source regions 224a and 224na and the drain regions 224b and 224nb.

As shown in FIG. 6H, the n + source regions 224a and 224na and the channel regions 224c and 224nc are formed by removing the third blocking layer and implanting low concentrations of n− ions into the entire surface of the array substrate 210. LED regions 224l, 224nl, 224l, and 224nl are formed between the n + drain regions 224b and 224nb and the channel regions 224c and 224nc.

At this time, the LED areas 224l, 224nl, 224l, 224nl are connected to the n-channel gate electrodes 221, 221n with the n-channel source regions 224a, 224na and the drain regions 224b, 224nb formed. As a mask is formed by implanting n- ions into the entire surface of the array substrate 210, an LED having a self-aligning structure is formed to control the off-current of the TFT.

Next, as shown in FIGS. 6I and 7D, after the interlayer insulating film 215b is deposited on the entire surface of the array substrate 210, the gate insulating film 215a and the gate insulating film 215a are formed through a photolithography process (a fifth mask process). A portion of the first contact holes 240a, 240na and 240pa and the drain regions 224b, 224nb and 224pb exposing a part of the source regions 224a, 224na and 224pa by removing a portion of the interlayer insulating layer 215b. The second contact holes 240b, 240nb, and 240pb exposing the same may be formed.

The interlayer insulating layer 215b may be a double layer of silicon nitride (SiNx) / silicon oxide (SiO ₂ ). In this case, an activation heat treatment may be performed after SiO ₂ deposition, and hydrogenation heat treatment may be performed after SiNx deposition. Alternatively, both SiNx / SiO ₂ may be hydrogenated and activated simultaneously through one heat treatment after deposition.

In addition, the interlayer insulating layer 215b may be variously applied to a single SiNx layer or a triple layer of SiO ₂ / SiNx / SiO ₂ .

As described above, the present invention adopts a structure including a silicon nitride film (SiNx) as the interlayer insulating film 215b, wherein the SiNx serves as a hydrogen source that can contribute to hydrogenation.

However, when the SiNx / SiO ₂ structure or the SiNx single layer structure is adopted as the interlayer insulating film 215b as described above, the SiNx has the same lamination compared to SiO ₂ having a dielectric constant of 6.5 to 7.0 and a dielectric constant of 3.9. The capacitance per unit area with respect to thickness becomes large. Accordingly, the electrical delay between the gate line 216 and the data line 217 arranged on the upper and lower portions of the interlayer insulating film 215b increases, resulting in an increase in signal delay. This can be problematic in view of high speed operation or high resolution implementation.

Thus, to solve this problem, the dielectric constant on the SiNx as the interlayer insulating layer (215b) can adopt three of the structure of SiO ₂ / SiNx / SiO ₂ by laminating a low SiO _2. As such, when the interlayer insulating layer 215b adopts a triple structure of SiO ₂ / SiNx / SiO _2, the capacitance per unit area can be reduced for the same stacking thickness as compared to the SiNx / SiO ₂ structure or the SiNx single layer structure. Can be. As a result, an electrical effect is reduced between the gate line 216 and the data line 217, thereby reducing a signal delay element.

In this case, when the second contact hole 240b of the pixel portion is formed, the drain region 224b of the pixel portion and a portion of the storage pattern 224 ″ may be exposed together, and the drain region 224b and the pixel portion of the pixel portion may be exposed. Two second contact holes may be formed to partially expose the storage pattern 224 ″ and then connected to each other by a drain electrode.

6J and 7E, a second conductive film and a third conductive film are formed on the entire surface of the array substrate 210 and then patterned using a photolithography process (sixth mask process). A source electrode 222, 222n, 222p and a second contact hole formed of three conductive layers and electrically connected to the source regions 224a, 224na, 224pa through the first contact holes 240a, 240na, 240pa. Drain electrodes 223, 223n and 223p electrically connected to the drain regions 224b, 224nb and 224pb through 240b, 240nb and 240pb are formed of the second conductive layer and the drain electrode 223 of the pixel portion. ) And a pixel electrode 218 electrically connected thereto.

In this case, the source electrodes 222, 222n and 222p, the drain electrodes 223, 223n and 223p, and the lower portion of the data line 217 are formed of the second conductive layer, respectively. Source electrode patterns 222 ', 222n' and 222p 'patterned in the same manner as the data lines 223 and 223n and 223p and the data line 217, and the drain electrode patterns 223', 223n 'and 223p' and data line patterns ( Not shown) is formed. A portion of the drain electrode pattern 223 'of the pixel portion extends into the pixel region to form the pixel electrode 218, so that the drain electrode 223 and the drain electrode pattern 223' are disposed through the drain electrode pattern 223 'without additional contact holes. The pixel electrode 218 is electrically connected.

In this case, a part of the source electrode 222 of the pixel portion extends in one direction to form a part of the data line 217, and a part of the drain electrode 223 of the pixel portion extends into the pixel region to extend the interlayer insulating film 215b. ) And overlap the common line 208 below to form a second storage capacitor.

As described above, the second embodiment uses the diffraction mask in the sixth mask process, so that the source electrodes 222, 222n and 222p, the drain electrodes 223, 223n and 223p and the pixel electrode 218 are subjected to one mask process. It can be formed at the same time, it will be described in detail with reference to the drawings.

8A to 8F are cross-sectional views illustrating the sixth mask process illustrated in FIGS. 6J and 7E in detail.

As shown in FIG. 8A, the second conductive layer 220 and the third conductive layer 230 are formed on the entire surface of the array substrate 210 including the first contact hole and the second contact hole.

In this case, the second conductive layer 220 may be made of a transparent conductive material having excellent transmittance, such as indium tin oxide or indium zinc oxide, to form the pixel electrode. Aluminum (Al), Al alloy, Tungsten (W), Copper (Cu), Chromium (Cr), Molybdenum (molybdenum) to form source and drain electrodes and data lines A low resistance opaque conductive material such as Mo).

Next, as shown in FIG. 8B, after forming the photoresist film 270 on the array substrate 210, light is selectively irradiated onto the photoresist 270 through the diffraction mask 280 of the second embodiment.

In this case, the diffraction mask 280 used in the second embodiment is applied with the transmission region I and the slit pattern for transmitting all the irradiated light, so that only a part of the light is transmitted and the slit region II is partially blocked and all the irradiated light is applied. A blocking region III for blocking light is provided, and only the light passing through the diffraction mask 280 is irradiated to the photosensitive film 270.

Subsequently, after developing the photosensitive film 270 exposed through the diffraction mask 280, as shown in FIG. 8C, light is blocked or partially blocked through the blocking region III and the slit region II. The first photoresist pattern 270a to the fifth photoresist pattern 270e having a predetermined thickness remain in the region, and the photoresist layer is completely removed in the transmission region I through which all the light is transmitted. The surface is exposed.

In this case, the first photoresist pattern 270a to the fourth photoresist pattern 270d formed in the blocking region III may have a thicker fifth photoresist pattern 270e formed through the slit region II. In addition, the photoresist film is completely removed in the region where all the light is transmitted through the transmission region I. This is because a positive photoresist is used, and the present invention is not limited thereto, and a negative photoresist may be used.

Next, as shown in FIG. 8D, the second conductive film and the third conductive film formed below are selectively formed using the first photosensitive film pattern 270a to fifth photosensitive film pattern 270e formed as described above as a mask. When removed, the source substrates 224a and 224na of the active patterns 224 ′, 224n and 224p may be formed of the third conductive layer on the array substrate 210 and may be formed through the first and second contact holes, respectively. Source electrodes 222, 222n and 222p and drain electrodes 223, 223n and 223p that are electrically connected to the drain electrodes 224pa) and the drain regions 224b, 224nb and 224pb.

In this case, the second conductive layer is formed under the source electrodes 222, 222n and 222p and the drain electrodes 223, 223n and 223p, and the side surfaces of the source electrodes 222, 222n and 222p and the drain electrodes 223, 223n and Source electrode patterns 222 ', 222n', 222p 'and drain electrode patterns 223', 223n ', 223p' patterned in the same shape as 223p remain.

A part of the drain electrode pattern 223 ′ of the pixel portion extends into the pixel region to form the pixel electrode 218, wherein the conductive film pattern 230 ′ formed of the third conductive film is formed on the pixel electrode 218. ) Will remain.

Subsequently, when the ashing process of removing a portion of the first photoresist pattern 270a to the fifth photoresist pattern 270e is performed, as illustrated in FIG. 8E, the pixel region, that is, the slit region to which diffraction exposure is applied ( The fifth photosensitive film pattern of II) is completely removed to expose the surface of the conductive film pattern 230 ′.

In this case, the first photoresist pattern to the fourth photoresist pattern correspond to the blocking region III by the sixth photoresist pattern 270a 'through the ninth photoresist pattern 270d' whose thickness is equal to that of the fifth photoresist pattern. It remains only at the top of the area.

Subsequently, as illustrated in FIG. 8F, the conductive layer pattern on the pixel electrode 218 is removed by using the remaining sixth photoresist pattern 270a ′ to ninth photoresist pattern 270d ′ as a mask. The surface of the electrode 218 is exposed to the outside.

As described above, in the second embodiment, the source electrodes 222, 222n and 222p, the drain electrodes 223, 223n and 223p and the pixel electrode 218 are formed through one mask process, and the pixel electrode 218 and the drain are formed. By removing the contact hole mask process for connecting the electrodes 223, the array substrate 210 of the liquid crystal display integrated with the driving circuit may be manufactured through a total of six mask processes.

At this time, in the second embodiment, since the black matrix 207 is formed on the lower layer of the array substrate 210, the alignment margin is not required as compared with the case where the black matrix is formed on the color filter substrate, thereby substantially increasing the aperture ratio. It will have an effect, which will be described in detail with reference to the following drawings.

FIG. 9 is a diagram schematically illustrating a cross-sectional structure of the liquid crystal display device along the line Vb-Vb ′ of the array substrate illustrated in FIG. 5.

As shown in the drawing, the array substrate manufactured according to the second embodiment is bonded to face the color filter substrate 205 by a sealant (not shown) formed on the outside of the image display area to form a liquid crystal display device. The bonding between the array substrate 210 and the color filter substrate 205 is performed through a bonding key (not shown) formed on the array substrate 210 and the color filter substrate 205.

The liquid crystal layer 290 is formed between the array substrate 210 and the color filter substrate 205.

In this case, the liquid crystal display of the second embodiment forms a black matrix 207 on the array substrate 210 to define the opening region la 'of the pixel, so that the array substrate as in the liquid crystal display of the first embodiment. There is no need to consider the misalignment that occurs when the color filter substrate and the bonding.

That is, when the black matrix 207 is formed on the array substrate 210, even if a misalignment occurs when the color filter substrate and the array substrate 210 are bonded together, the black matrix 207 is related to the misalignment. Since it is formed in the array substrate 210, there is no need to form an alignment margin on the black matrix in consideration of the misalignment as in the first embodiment.

As a result, the opening area la is increased compared to the opening area la when the alignment margin of the first embodiment is taken into consideration, and the opening ratio is improved.

For reference, reference numeral 206 denotes a color filter for implementing color.

In this case, the second embodiment describes a case in which n + doping of the active pattern is separately performed when the gate electrode is formed after the storage doping, but the present invention is not limited thereto. Alternatively, before forming the gate electrode, n + doping and storage doping of the active pattern may be simultaneously performed, which will be described in detail with reference to the following third embodiment.

10 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a third exemplary embodiment of the present invention.

As shown in the figure, a gate line 316 and a data line 317 are formed in the array substrate 310 of the third embodiment, which is arranged vertically and horizontally on the array substrate 310 to define a pixel region. In addition, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 316 and the data line 317, and is connected to the thin film transistor in the pixel area and is connected to a common electrode of a color filter substrate (not shown). A pixel electrode 318 for driving a liquid crystal (not shown) is formed.

The thin film transistor includes a gate electrode 321 connected to the gate line 316, a source electrode 322 connected to the data line 317, and a drain electrode 323 connected to the pixel electrode 318. In addition, the thin film transistor includes an active pattern 324 ′ that forms a conductive channel between the source electrode 322 and the drain electrode 323 by a gate voltage supplied to the gate electrode 321.

In this case, a portion of the active pattern 324 'made of a polycrystalline silicon thin film extends to a pixel area to form a storage pattern 324 ", and the storage pattern 324" is formed of a predetermined portion of the active pattern 324'. N + ions are implanted into the region to be used as storage electrodes. In addition, a common line 308 is formed in the pixel area in substantially the same direction as the gate line 316, and the common line 308 is disposed below the gate line with a gate insulating layer (not shown) therebetween. The first storage capacitor is formed to overlap with the pattern 324 ". In this case, the storage pattern 324" of the third embodiment is made of a silicon thin film constituting the active pattern 324 ', but the second embodiment Unlike the example, storage doping is performed using the n + doping process of the active pattern 324 '.

In addition, the source electrode 322, the drain electrode 323, and the data line 317 made of an opaque conductive material may be formed of a transparent conductive material under the source electrode 322, the drain electrode 323, and A source electrode pattern 322 ', a drain electrode pattern 323', and a data line pattern 317 'patterned in the same shape as the data line 317 are formed.

The source electrode 322 and the drain electrode 323 of the active pattern 324 ′ may be formed through the first contact hole 340a and the second contact hole 340b formed in the gate insulating layer and the interlayer insulating layer (not shown). It is electrically connected to the source region 324a and the drain region 324b. In addition, a portion of the source electrode 322 extends in one direction to form a portion of the data line 317, and a portion of the drain electrode pattern 323 ′ extends toward the pixel region to extend the pixel electrode 318. Will be constructed.

In this case, a part of the drain electrode 323 extending to the pixel region overlaps the common line 308 beneath the interlayer insulating layer and forms a second storage capacitor.

In addition, in the liquid crystal display of the third embodiment, alignment margins can be reduced by forming the black matrix 307 on the array substrate 310 instead of the color filter substrate, thereby increasing the opening area A of the pixel. have.

In this case, the liquid crystal display of the third embodiment simultaneously forms a source electrode 322, a drain electrode 323, and a pixel electrode 318 by using a diffraction mask in one mask process, and the pixel electrode 318 and the drain are simultaneously formed. By removing the contact hole mask process for connecting the electrode 323 ', the array substrate can be manufactured through a total of six mask processes, which will be described in detail with the following manufacturing method of the liquid crystal display.

11A to 11G are cross-sectional views sequentially illustrating a manufacturing process along the line X-X 'of the array substrate shown in FIG.

In this case, in general, the thin film transistor formed in the pixel portion may be both n-channel or p-channel, and both the n-channel TFT and the p-channel TFT are formed in the circuit portion to form a CMOS. The method of manufacturing an n-channel TFT and a p-channel TFT is shown, for example.

As shown in FIG. 11A, a first buffer layer 311 and an organic film (or metal film) are formed on an array substrate 310 made of a transparent insulating material such as glass, and then the organic film (or metal film) is formed. Patterning forms a black matrix 307 in the pixel portion.

The black matrix 307 is patterned on the boundary region of the pixels to block leakage of light generated from a backlight (not shown) under the liquid crystal display and to prevent color mixing of adjacent pixels.

For reference, the mask process for forming the black matrix 307 is not included in the total number of masks in the array process for manufacturing the array substrate 310.

Subsequently, as shown in FIG. 11B, after forming the second buffer layer 311 ′ and the polycrystalline silicon thin film on the entire surface of the array substrate 310 on which the black matrix 307 is formed, a photolithography process (first mask) Process pattern) to selectively pattern the polycrystalline silicon thin film to form an active pattern 324 'on the pixel array substrate 310, and n-channel active pattern 324n and p-channel active on the circuit array substrate 310. The pattern 324p is formed.

As shown in FIG. 11C, after all of the p-channel TFT region of the circuit portion and a portion of the n-channel TFT region of the pixel portion and the circuit portion are covered with a first blocking film made of photoresist (second mask process), the first High concentrations of n + ions are implanted using the blocking film as a mask to form n + source regions 324a and 324na and drain regions 324b and 324nb. Here, reference numerals 324c and 324nc denote n-channel regions that form conductive channels between the n + source regions 324a and 324na and the drain regions 324b and 324nb.

In this case, the partial pattern of the active pattern 324 ′ into which the n + ion is implanted constitutes the storage pattern 324 ″, thereby eliminating a separate mask process for storage doping.

Thereafter, as illustrated in FIG. 11D, a gate insulating film 315a and a first conductive film are formed over the array substrate 110.

Next, the entire area of the n-channel TFT region of the pixel portion and the circuit portion and the predetermined region of the p-channel TFT region of the circuit portion are covered with a second blocking film (third mask process), and then the second blocking film is masked under the second blocking film. The first conductive film is selectively patterned to form a circuit part gate electrode 321p formed of the first conductive film in the p-channel TFT region of the circuit part. The p + source region 324pa and the drain region 324pb are formed by implanting high concentration p + ions into the circuit portion p-channel TFT region using the second blocking film as a mask. Here, reference numeral 324pc denotes a p-channel region that forms a conductive channel between the p + source region 324pa and the drain region 324pb.

Subsequently, as shown in FIG. 11E, after all of the p-channel TFT region of the circuit portion and a portion of the n-channel TFT region of the pixel portion and the circuit portion are covered with a third blocking film (fourth mask process), the third blocking film is masked. The first conductive layer under the log is patterned to form the pixel portion gate electrode 321 and the circuit portion gate electrode 321n in the pixel portion and the circuit portion, respectively, and the common line 308 is formed on the storage pattern 324 ″. do.

In this case, as in the above-described second embodiment, the pixel portion gate electrode 321, the circuit portion gate electrode 321n, and the common line 308 may overetch the first conductive layer by wet etching to form a third upper portion thereof. It can make the width smaller than the barrier.

Thereafter, after removing the third blocking layer, a low concentration of n − ions are implanted into the entire surface of the array substrate 310 to form the n + source regions 324a and 324na and the channel regions 324c and 324nc and the n + drain regions 324b and 324nb. ) And the LED areas 324l, 324nl, 324l, 324nl between the channel regions 324c, 324nc.

Next, as shown in FIG. 11F, after the interlayer insulating film 315b is deposited on the entire surface of the array substrate 310, the gate insulating film 315a and the interlayer insulating film ( A portion of the first contact holes 340a, 340na, and 340pa exposing a portion of the source regions 324a, 324na, and 324pa by removing a portion of the region 315b and exposing a portion of the drain regions 324b, 324nb, and 324pb are exposed. Second contact holes 340b, 340nb, and 340pb are formed.

Here, the interlayer insulating layer 315b may be a double layer of SiNx / SiO ₂ . In this case, an activation heat treatment may be performed after SiO ₂ deposition, and hydrogenation heat treatment may be performed after SiNx deposition. Alternatively, both SiNx / SiO ₂ may be hydrogenated and activated simultaneously through one heat treatment after deposition.

In addition, the interlayer insulating layer 315b may be variously applied to a single layer of SiNx or a triple layer of SiO ₂ / SiNx / SiO ₂ .

In this case, when the second contact hole 340b of the pixel portion is formed, the drain region 324b of the pixel portion and a portion of the storage pattern 324 ″ may be exposed together, and the drain region 324b and the pixel portion of the pixel portion may be exposed. Two second contact holes may be formed so that a portion of the storage pattern 324 "is exposed separately, and then connected to each other by a drain electrode.

Thereafter, as shown in FIG. 11G, the second conductive film and the third conductive film are formed on the entire surface of the array substrate 310, and then patterned by using a photolithography process (sixth mask process). And source electrodes 322, 322n and 322p and second contact holes 340b and 340nb electrically connected to the source regions 324a, 324na and 324pa through the first contact holes 340a, 340na and 340pa. And drain electrodes 323, 323n and 323p electrically connected to the drain regions 324b, 324nb and 324pb through 340pb, and are formed of the second conductive layer and electrically connected to the drain electrode 323 of the pixel portion. The pixel electrode 318 to be connected is formed.

In this case, the source electrodes 322, 322n and 322p, the drain electrodes 323, 323n and 323p, and the lower portion of the data line (not shown) are formed of the second conductive layer, respectively. Source electrode patterns 322 ', 322n' and 322p 'patterned in the same form as electrodes 323, 323n and 323p and data lines, drain electrode patterns 323', 323n 'and 323p' and data line patterns (not shown). ) Is formed. A portion of the drain electrode pattern 323 ′ of the pixel portion extends into the pixel region to form the pixel electrode 318, so that the drain electrode 323 and the drain electrode 323 ′ may be formed through the drain electrode pattern 323 ′ without additional contact holes. The pixel electrode 318 is electrically connected.

The array substrates of the first to third embodiments configured as described above are bonded to face the color filter substrate by sealants formed on the outer side of the image display area to form a liquid crystal display device, and the bonding of the array substrate and the color filter substrate is performed. Is achieved through a bonding key formed on the array substrate and the color filter substrate.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

As described above, in the method of manufacturing the liquid crystal display according to the present invention, n + doping and storage doping can be performed simultaneously, and the source / drain electrodes and the pixel electrodes can be formed through one mask process. As a result, the number of masks used for manufacturing the thin film transistor is reduced, thereby reducing the manufacturing process and cost.

In addition, the manufacturing method of the liquid crystal display according to the present invention can further reduce the manufacturing process and cost by eliminating the contact hole mask process for connecting the pixel electrode and the drain electrode.

In addition, the manufacturing method of the liquid crystal display according to the present invention provides the effect of increasing the luminance by improving the aperture ratio by forming a black matrix on the array substrate.

In addition, the manufacturing method of the liquid crystal display according to the present invention can control the off-current of the thin film transistor by forming the LED of the self-aligned structure.

Claims (26)

Providing a first substrate divided into a pixel portion, a first circuit portion, and a second circuit portion; Forming a black matrix on the pixel portion; Forming a buffer layer on the first substrate; Forming an active pattern on the pixel portion and the first and second circuit portions, and forming a storage pattern on a predetermined region of the active pattern of the pixel portion; Forming a gate insulating film on the first substrate; Forming a gate electrode on the first circuit portion, and forming a p + source / drain region on a predetermined region of the active pattern of the first circuit portion; Forming a gate electrode on the pixel portion and the second circuit portion, and forming a common line on the pixel portion; Forming an LED region in a predetermined region of an active pattern of the pixel portion and the second circuit portion; Forming an interlayer insulating film on the first substrate; Removing portions of the gate insulating layer and the interlayer insulating layer to form first contact holes and second contact holes exposing source and drain regions of the active pattern, respectively; Forming a source electrode electrically connected to the source region of the active pattern through the first contact hole, and forming a drain electrode electrically connected to the drain region of the active pattern through the second contact hole; Forming a pixel electrode electrically connected to the drain electrode; Providing a second substrate; Forming a liquid crystal layer on any one of the first substrate and the second substrate; And And attaching the first substrate and the second substrate to each other. The method of claim 1, further comprising forming an n + source / drain region in a predetermined region of an active pattern of the pixel portion and the second circuit portion. The method of claim 2, wherein the n + source / drain region and the storage pattern are formed through a single mask process by using diffraction exposure. The method of claim 1, wherein the active pattern is formed of a polycrystalline silicon thin film. The method of claim 4, wherein the storage pattern is formed by injecting n + impurities into the polycrystalline silicon thin film. The method of claim 1, wherein forming a gate electrode in the first circuit unit and forming a p + source / drain region in a predetermined region of the active pattern of the first circuit unit is performed. Forming a first conductive film on the first substrate; Covering all of the pixel portion and the second circuit portion with a first blocking layer; Selectively removing the first conductive layer using the first blocking layer as a mask to form a gate electrode in the first circuit unit; And And forming a p + source / drain region in a predetermined region of the active pattern of the first circuit portion by implanting high concentration p + ions into the first circuit portion using the gate electrode as a mask. Way. The method of claim 1, wherein the common line overlaps the storage pattern with the gate insulating layer interposed therebetween to form a first storage capacitor. The method of claim 1, wherein the common line overlaps a portion of the drain electrode with the interlayer insulating layer therebetween to form a second storage capacitor. The method of claim 6, wherein the forming of the gate electrode on the pixel portion and the second circuit portion comprises: Covering all of the first circuit portion and a portion of the pixel portion and the second circuit portion with a second blocking layer; And And selectively removing the first conductive layer using the second blocking layer as a mask to form a gate electrode in the pixel portion and the second circuit portion. 10. The method of claim 9, wherein the gate electrode of the pixel portion and the second circuit portion has a width smaller than that of the second blocking layer by over-etching the first conductive layer using wet etching. . 10. The n + source of claim 9, wherein a high concentration of n + ions are implanted into the pixel portion and the second circuit portion using a gate electrode as a mask for the pixel portion and the second circuit portion. And / or forming a drain region. The method of claim 9, wherein after removing the second blocking layer, a low concentration of n− ions is implanted using the gate electrode as a mask to form an LED region in a predetermined region of an active pattern of the pixel portion and the second circuit portion. A method of manufacturing a liquid crystal display device. The method of claim 1, wherein the interlayer insulating film is formed of a silicon nitride film. The method of claim 1, wherein the interlayer insulating layer is formed of at least a double layer including a silicon nitride layer. The method of claim 1, wherein the second contact hole of the pixel portion exposes a portion of the storage pattern and a portion of the drain region at the same time. The method of claim 1, wherein an n-channel thin film transistor is formed in the pixel portion and the second circuit portion. The method of claim 1, wherein a p-channel thin film transistor is formed in the first circuit portion. The method of claim 1, wherein the source electrode, the drain electrode, and the pixel electrode are formed through one mask process by using a diffraction mask or a half-tone mask. 19. The method of claim 18, wherein forming the source electrode, the drain electrode, and the pixel electrode Forming a second conductive film and a third conductive film on an entire surface of the first substrate including the first contact hole and the second contact hole; Forming a first photoresist pattern having a first thickness in a first region of the first substrate, and forming a second photoresist pattern having a second thickness in a second region; By selectively patterning the second conductive layer and the third conductive layer using the first photoresist pattern and the second photoresist pattern as masks, source and drain electrodes and data lines formed of the third conductive layer are formed in the first region. Forming a pixel electrode made of the second conductive film and a conductive film pattern made of the third conductive film in the second region; Removing the second photoresist pattern and simultaneously removing a portion of the first photoresist pattern to form a third photoresist pattern having a third thickness; And And removing the conductive film pattern in the second region by using the third photoresist pattern as a mask to expose the pixel electrode. 20. The source and drain electrode patterns of claim 19, wherein the source and drain electrodes are formed under the source electrode and the drain electrode, respectively, the second conductive layer being patterned in the same shape as the source electrode, the drain electrode, and the data line. A method of manufacturing a liquid crystal display device, characterized in that a data line pattern is formed. 20. The method of claim 19, wherein the first photoresist pattern is patterned into a third photoresist pattern having a third thickness that is substantially reduced by the thickness of the second photoresist pattern through an ashing process. 20. The method of claim 19, wherein the first region is a region in which a source electrode, a drain electrode, and a data line are formed. 20. The method of claim 19, wherein the second region is a region where a pixel electrode is formed. 20. The method of claim 19, wherein the first thickness is thicker than the second thickness. 20. The method of claim 19, wherein the third conductive film is formed of an opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, or molybdenum. 20. The method of claim 19, wherein the second conductive layer is formed of a transparent conductive material such as indium tin oxide or indium zinc oxide.

Images