KR20080054035A - Flash memory device and method of manufacturing the same - Google Patents

Abstract

A flash memory device and a manufacturing method thereof are provided to perform effectively a PMD(Pre-Metal Dielectric) gap-fill process by reducing effectively thickness of spacers formed on both sidewalls of a gate. A first sidewall insulating layer(220), a second sidewall insulating layer(230), and a third sidewall insulating layer are sequentially formed on a semiconductor substrate(210) including a plurality of stack gates and transistors. Spacers are formed at both sidewalls of the stack gates and both sides of the transistors by etching the third sidewall insulating layer and the second sidewall insulating layer. Photoresist is coated on the substrate and a cell region is opened. A fourth sidewall insulating layer(260) is formed on the stack gate in order to fill up a void of the first sidewall insulating layer. A second etch process and a cleaning process for the fourth sidewall insulating layer are performed.

Description

Flash memory device and method of manufacturing the same

1A is a cross-sectional view illustrating a void generated in a process of forming a flash memory device according to the related art.

1B is a scanning electron microscope image showing a contact bridge phenomenon caused by voids of a flash memory device formed according to the prior art.

2A to 2F are sequential cross-sectional views illustrating a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

210: semiconductor substrate

220: first sidewall insulating film

230: second sidewall insulating film

240: third sidewall insulating film

250 photoresist

260: fourth sidewall insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a method of manufacturing the same, and in particular, to prevent contact bridges due to voids generated in the process of removing an insulating film of a gate spacer made of a multilayer insulating film. And a method of manufacturing the same.

The flash memory is called nonvolatile memory because the memory information does not disappear even when the power is turned off. In this regard, the flash memory differs from DRAM (Dynamic RAM) and SRAM (Static RAM).

Flash memory may be classified into a stack gate type and a split gate type according to the unit cell structure, and may be divided into a floating gate device and a silicon-oxide-nitride-oxide-silicon (SONOS) device according to the shape of the charge storage layer. have. Among them, the floating gate device typically includes a floating gate formed of polycrystalline silicon surrounded by an insulator, and the floating gate is charged by channel hot carrier injection or FN tunneling by Fowler-Nordheim Tunneling. Is injected or discharged to store and erase data.

On the other hand, an important variable that determines the performance of memory cells in flash memory devices is the gate coupling coefficient. This gate coupling coefficient has a great influence on the potential of the floating gate. Flash memory devices with higher gate coupling coefficients can form the potential of the floating gate close to the potential given to the control gate of the memory cell, thereby providing higher program and erase efficiency or read speed. The performance of can be further improved. The high gate coupling ratio simplifies the flash chip design, lowering the operating voltage of the flash memory cell, especially for lower supply voltages. An important factor in determining the gate coupling coefficient is the capacitance between poly silicon for tunnel oxide capacitance, that is, the capacitance between floating gate poly and control gate poly. to be. As the capacitance between polysilicon increases and the tunnel oxide capacitance decreases, the gate coupling coefficient can increase.

On the other hand, the design rule of the flash memory cell is reduced according to the tendency of high integration of the semiconductor device, and as a result, the size of the cell is reduced, so that the pitch between the gate and the gate is narrowed. Using spacers makes the PMD (premetal dielectric) gap fill process very difficult.

Therefore, as shown in FIG. 1A, in order to improve the PMD gapfill process, the thickness of the spacer formed on both sidewalls of the gate is reduced. (loss) occurs and the problem of void (X) appears.

That is, as shown in Figure 1b, although the word line and the word line must be insulated from each other to operate differently, when a metal material such as tungsten (W) is introduced to form a subsequent contact, As tungsten is diffused toward the void X, the adjacent gates are electrically connected to each other to generate a contact to contact bride phenomenon. Tungsten is a conductive layer formed for forming bit line contacts.

As a result, the gate formed on the word line does not operate correctly and an operation error occurs, thereby deteriorating the reliability and yield of the flash memory device.

In order to solve the above-described problem, the present invention, in particular, the flash can prevent the contact bridge (contact bridge) phenomenon caused by the void (void) generated in the process of removing the insulating film of the gate spacer made of a multi-layer insulating film It is an object to provide a method of manufacturing a memory device.

In addition, another object of the present invention relates to a flash memory device that can effectively improve the PMD (premetal dielectric) gap fill process by reducing the thickness of the spacer formed on both sidewalls of the gate.

In order to achieve the above object, the present invention is a step of sequentially forming a first sidewall insulating film, a second sidewall insulating film and a third sidewall insulating film on a semiconductor substrate formed with a plurality of stack gates and transistors, and the third sidewall insulating film And forming a spacer on both sidewalls of the stack gate and both sidewalls of the transistor by performing a first etching process on the second sidewall insulating film, applying a photoresist to the substrate including the spacers, and then Opening a region, and forming a fourth sidewall insulating layer on the stack gate so as to fill a void of the first sidewall insulating layer generated in the process of removing the third sidewall insulating layer of the spacer from the open cell region. Forming a substrate; and performing a second etching process and a cleaning process on the fourth sidewall insulating layer. A method of manufacturing a lash memory device is provided.

In the present invention, the first sidewall insulating film is formed of high temperature oxide (HTO), the second sidewall insulating film is formed of an oxide film of TEOS (Tetra Ethyl Ortho Silicate), and the third sidewall insulating film is a silicon nitride film (SiN). To form).

In an embodiment of the present invention, the first sidewall insulating film is formed to a thickness of 50 to 100 GPa, the second sidewall insulating film is formed to a thickness of 200 to 300 GPa, and the third sidewall insulating film is formed to be 700 to 1500 GPa thick.

In the present invention, in the removing of the third sidewall insulating film, the third sidewall insulating film is removed by performing wet etching using diluted HF (DHF).

In the present invention, the fourth sidewall insulating film is formed to a thickness of 180 ~ 220Å by using any one of HTO, TEOS-based oxide film and HTO and TEOS-based oxide film by thermal CVD (Thermal Chamical Mechanical Deposition) method.

In addition, in the flash memory device according to the present invention, a plurality of stack gates including a tunnel oxide film, a floating gate, an ONO film, and a control gate are provided on a semiconductor substrate, and are sequentially formed along both sidewalls of the stack gate. And a spacer comprising a sidewall insulating film and a second sidewall insulating film.

In the present invention, the first sidewall insulating film is formed of any one of HTO, TEOS-based oxide film having a thickness of 50 ~ 100 GPa, and an oxide film of the HTO and TEOS system, the second sidewall insulating film is a TEOS oxide film having a thickness of 200 ~ 300Å To form.

In the present invention, the spacer in which the first sidewall insulating film and the second sidewall insulating film are conformally formed on both sidewalls of the plurality of stack gates is at right angles.

Hereinafter, a flash memory device and a manufacturing method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Descriptions of technical contents that are well known in the art to which the present invention pertains and are not directly related to the present invention will be omitted. This is to more clearly communicate without obscure the subject matter of the present invention by omitting unnecessary description.

First, as illustrated in FIG. 2A, a cell having a plurality of stack gates including a tunnel oxide layer, a floating gate, an oxide-nitride-oxide (ONO) layer, and a control gate on a semiconductor substrate 210 is provided. The first sidewall insulating layer 220 and the second sidewall are formed on the entire surface of the substrate 210 including the stack gate and the transistor in the cell region A and the logic region B including the plurality of transistors. The sidewall insulating film 230 and the third sidewall insulating film 240 are sequentially and sequentially formed.

Here, the first sidewall insulating film 220 is formed of high temperature oxide (HTO), the second sidewall insulating film 230 is formed of an oxide film of TEOS (Tetra Ethyl Ortho Silicate), and the third sidewall insulating film 240 is It is formed of a silicon nitride film (SiN). In this case, the first sidewall insulating film 220 may be formed to have a thickness of 50 to 100 GPa, the second sidewall insulating film 230 may be formed to have a thickness of 200 to 300 GPa, and the third sidewall insulating film 240 may be formed to have a thickness of 700 to 1500 GPa. have.

Next, as shown in FIG. 2B, a first etching process is performed on the third sidewall insulating layer 240 and the second sidewall insulating layer 230 to form spacers on both sidewalls of the stack gate and both sidewalls of the transistor. . That is, after main etching is about 90% with respect to the third sidewall insulating layer 240 made of SiN, the remaining 10% is overetched. Subsequently, after the main etching is performed about 90% with respect to the second sidewall insulating film 230 formed of the TEOS-based oxide film, the remaining 10% over etching process is performed. The etching process for forming the spacer is preferably performed by an isotropic reactive ion etching (RIE) or an isotropic plasma etching process.

Next, as shown in FIG. 2C, a photoresist 250 is applied to the entire surface of the substrate 210 including the spacers including the third sidewall insulating film 240 of SiN including the second sidewall insulating film 230 of TEOS. Thereafter, the photoresist 250 applied to the cell region A is removed to open the cell region A having the plurality of stack gates. Here, the photoresist 250 is preferably applied to a thickness of 0.85 ~ 3㎛.

Next, as shown in FIG. 2D, the third sidewall insulating layer 240 of the spacer is removed from the open cell region A. FIG. This is because the design rule of the flash memory cell is reduced and the size of the cell is reduced so that the pitch between the gate and the gate is narrowed. In this case, when the gate spacer is used, the PMD ( This is to reduce the thickness of the spacer to improve the PMD gapfill process as the gap fill process becomes very difficult.

However, at this time, in the process of removing the third sidewall insulating layer 240 of the spacer, a loss occurs with respect to the first sidewall insulating layer 220, thereby causing a void (Y) problem.

Thus, as shown in FIG. 2E, the fourth sidewall on the plurality of stack gates to fill the void (Y) of the first sidewall insulating film 220 on the stack gate generated in the process of removing the third sidewall insulating film 240. The insulating film 260 is formed. Here, the fourth sidewall insulating layer 260 is formed to have a thickness of 180 to 220 kV by using any one of HTO, TEOS oxide, and HTO and TEOS oxide by thermal thermal vapor deposition (CVD). At this time, since it is deposited by the thermal CVD method, it is effective to spread out well in the word line direction and fill the void Y.

Next, as shown in FIG. 2F, a second etching process is performed on the fourth sidewall insulating layer 260 deposited to fill the void Y by using an isotropic reactive ion etching (RIE) or an isotropic plasma etching process. After performing, a predetermined washing process is performed. Therefore, since the void Y is filled with the same material as the first sidewall insulating layer 220 or the oxide film of the TEOS system, the contact bridge phenomenon due to the void Y problem can be suppressed.

In addition, since the spacer formed by the present invention is formed as a spacer having a right-angled shape on both sidewalls of the stack gate rather than the conventional round-shaped spacer, the thickness of the spacer can be reduced, so that the PMD gapfill process can be effectively performed.

Although specific embodiments of the present invention have been described with reference to the drawings, this is intended to be easily understood by those skilled in the art and is not intended to limit the technical scope of the present invention. Therefore, the technical scope of the present invention is determined by the matters described in the claims, and the embodiments described with reference to the drawings may be modified or modified as much as possible within the technical spirit and scope of the present invention.

As described above, according to the present invention, metal deposition for forming a contact by filling an insulating material of an oxide film with a void, which may occur in a process of removing an insulating film of a gate spacer made of a multilayer insulating film, is performed. As a result, a contact bridge phenomenon can be prevented.

In addition, by effectively reducing the thicknesses of the spacers formed on both sidewalls of the gate, an efficient premetal dielectric (PMD) gap fill process may be performed even if the distance between the cells is reduced.

Claims (9)

Sequentially forming a first sidewall insulating film, a second sidewall insulating film, and a third sidewall insulating film on a semiconductor substrate on which a plurality of stack gates and transistors are formed; Performing a first etching process on the third sidewall insulating film and the second sidewall insulating film to form spacers on both sidewalls of the stack gate and both sidewalls of the transistor; After applying the photoresist to the substrate with the spacer, opening the cell region; Forming a fourth sidewall insulating film on the stack gate to fill a void of the first sidewall insulating film generated in the process of removing the third sidewall insulating film of the spacer in the open cell region; And performing a second etching process and a cleaning process on the fourth sidewall insulating film. The method of claim 1, The first sidewall insulating film is formed of high temperature oxide (HTO), the second sidewall insulating film is formed of an oxide film of TEOS (Tetra Ethyl Ortho Silicate), and the third sidewall insulating film is formed of silicon nitride (SiN). Method for manufacturing a flash memory device, characterized in that. The method according to claim 1 or 2, The first sidewall insulating film is formed to a thickness of 50 ~ 100Å, the second sidewall insulating film is formed to a thickness of 200 ~ 300Å, the third sidewall insulating film is formed to a thickness of 700 ~ 1500Å Way. The method of claim 1, And removing the third sidewall insulating layer, wherein the third sidewall insulating layer is wet etched using diluted HF (DHF) to remove the third sidewall insulating layer. The method of claim 1, The fourth sidewall insulating film is formed using a thermal chemical vapor deposition (CVD) method by using any one of HTO, TEOS oxide, and HTO and TEOS oxide, having a thickness of about 180 to 220 kV. Manufacturing method. The method of claim 1, And the first etching process and the second etching process are isotropic reactive ion etching (RIE) or an isotropic plasma etching process. In a state where a plurality of stack gates including a tunnel oxide film, a floating gate, an ONO film, and a control gate are provided on a semiconductor substrate, And a spacer including a first sidewall insulating film and a second sidewall insulating film sequentially along both sidewalls of the stack gate. The method of claim 7, wherein The first sidewall insulating film is formed of any one of HTO, TEOS-based oxide film having a thickness of 50 to 100 GPa and an oxide film of the HTO and TEOS-based film, and the second sidewall insulating film is formed of a TEOS-based oxide film having a thickness of 200 to 300 GPa. Flash memory device. The method of claim 7, wherein And a spacer having the first sidewall insulating film and the second sidewall insulating film conformally formed on both sidewalls of the plurality of stack gates.

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