KR100262000B1 - Gate flash cell and fabricating method thereof - Google Patents

Abstract

PURPOSE: A gate flash cell and a fabricating method thereof are provided to realize a fast read operation and the high integration of semiconductor devices by reducing the resistance of word lines and increase the number of rewrite operation by attaching two erase gates to one cell. CONSTITUTION: Erase gates(315) are respectively inserted between control gates(310,312) for minimizing the increase of cell area due to adding the erase gate. The respective erase gates(315) are adjacent through a floating gate(38) and an inter poly oxide film(314) of adjacent two cells. The erase gates utilizes the same poly-poly erase method as prior method. But, the difference from the prior method is that the erase operation is performed from both sides because the erase gates are positioned on both sides of one floating gate.

Description

Gate flash cell of semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a separate gate flash cell of a semiconductor device, and is particularly advantageous for high-speed read operations and high integration of semiconductor devices by reducing the resistance of cell word lines, and fixing two erase gates per cell. The present invention relates to a flash cell capable of increasing the number of writes and a method of manufacturing the same.

A structure of a general split gate flash cell will be described with reference to FIGS. 1A to 1B. 1A to 1B are cross-sectional structural views of a structure of a separate gate flash cell of a semiconductor device according to the related art in a channel length direction and a channel width direction, respectively.

As shown in FIG. 1A, a channel of a separate gate cell has a source / drain section formed with a BN + section (2, 3), and the channel includes a channel in which the floating gate 8 and the control gate 10 overlap, and a control gate ( 10) consists of only channels connected. Programming in the cell applies a high voltage of about 12 V and 7 V to the control gate 10 and the drain section 3, respectively, so that channel hot electrons generated at the drain end of the channel are suspended. To be injected).

On the other hand, the separate gate flash cell has a separate erase gate for the erase operation of the cell, and the erase gate is disposed between the control gate 10 and the control gate 10 as shown in FIG. A process of inserting and removing the erase gate 15 is used. One erase gate 15 is adjacent with the floating gate 8 of two adjacent cells and the interpoly oxide film 14 therebetween.

In order to perform the erase operation, a high voltage of about 15 V or more is applied to the erase gate, and electrons of the floating gate are tunneled to the erase gate by the high voltage. Such an erase method is called a poly-poly erase method.

The manufacturing process of the separate gate flash cell according to the prior art using the poly-pearly erasing method is as follows.

2A to 2E are cross-sectional views of a manufacturing process of a discrete gate flash cell of a semiconductor device in a channel width direction.

In FIG. 2A, a CVD oxide film 5 is formed by depositing a silicon substrate 1 on the silicon substrate 1 in order to isolate the cell in the width direction of the cell. Then, the photolithography process is performed dry to define a region where a channel is to be formed, and then remains. The first sidewall 6 is formed of a first high temperature low pressyre dielectric layer on the side of one CVD oxide film 5.

In FIG. 2B, the gate oxide film 7 is formed on the surface of the channel forming region, and then the first polysilicon layer 8 for floating gate is formed by depositing and controlling the floating gate 8 and the floating gate 8 thereon. The first interpoly oxide film 9 for isolation of the gate 10 is grown and formed.

In FIG. 2C, the second polysilicon layer 10 for the control gate is formed by depositing, and the second HDL layer 11 for capping is deposited thereon, and the second poly is formed by a photolithography process by a dry method. The control gate 10 is formed by removing the silicon layer 10 and a part of the second HDL layer for capping. Then, a second sidewall 12 is formed on the sidewalls of the second HDL layer 11 for capping and the control gate 10 which remain, and then the sidewall of the second sidewall 12 is formed. The third sidewall 13 is formed of boronphospho silicate glass.

In FIG. 2D, the first polysilicon layer 8 for floating gate is dry-etched using the capping second HDL 11 and the BPS third sidewall 13 as a masking object located above the control gate 10. Then, the first polysilicon layer of the unmasked portion is removed, and then the BPS third sidewall 13 is removed by wet etching.

In FIG. 2E, in order to protect the side surface of the floating gate first polysilicon layer 8 exposed by dry etching with respect to the polysilicon, the second interpoly oxide film 14 is grown on the side surface thereof. Thereafter, the third polysilicon layer 15 for the erase gate is deposited and formed, and then the erase gate 15 is patterned by performing a photolithography process using a dry etching method. In this case, since one erase gate 15 is adjacent to two floating gates 8, in the conventional cell, the erase gate 15 does not exist between all control gates, and alternately exists one by one. Therefore, in the conventional cell, the erase gates do not exist between all the control gates and exist one by one. When viewed from the channel of the cell, the cell has a left-right asymmetric structure, and deep valleys exist in the part without the erase gate.

As described above, one of the fundamental problems of the poly-poly erasing method in the related art is the electron trapping phenomenon in the interpoly oxide film 14 between the floating gate and the erasing gate. The electrons trapped in the interpoly oxide film inhibit the electron tunneling from the floating gate to the erasing gate during the erasing operation, thereby suppressing cell erasure. Therefore, as the number of rewrites increases, the threshold voltage of the erased cell increases to limit the number of rewrites of the flash cell.

In addition, since there is a high temperature tube process such as interpoly oxide film growth after the control gate process, which is the word line of the cell, the polyside process cannot be used for the deposition of polysilicon for the control gate, and only the polysilicon can form the control gate. . As a result, the cell's word line resistance becomes relatively large, which causes a decrease in reading speed during the cell's read operation, and limits the number of cells that can be driven by one word line, resulting in a total area occupied by the cell array. Is increased. In the case of wrapping the control gate with a metal line to reduce the resistance at the word line, the contact hole and the metal process design rule to be formed on the control gate are used in the direction of the channel width of the cell. The size must be large, resulting in an increase in cell size.

In addition, the deep valley portion between the control gate and the control gate in which the erase gate is not formed causes a deep step in the cell array, which is bad in terms of planarization and increases the difficulty of the metal process.

Accordingly, in order to solve the above problem, the present invention reduces the resistance of a cell word line, which is advantageous for high-speed read operations and high integration of semiconductor devices. Provided are a flash cell and a method of manufacturing the same.

A method of manufacturing a gate flash cell of a semiconductor device according to the present invention for achieving the above object comprises the steps of: forming a field oxide film on a first conductive semiconductor substrate and defining a field region; Forming a first sidewall on an exposed side portion of the field oxide film remaining as the first HDL layer on the exposed portion, forming a gate oxide film on the exposed surface of the semiconductor substrate, and forming a first conductive layer on the gate oxide film. Forming a first interpoly oxide film on the surface of the first conductive layer, forming a second conductive layer on the surface of the first interpoly oxide film, and forming a first cap on the surface of the second conductive layer. Forming a ping nitride film, removing a portion of the first capping nitride film, the second conductive layer and the first interpoly oxide film to form a sub control gate; Forming a second sidewall on the side of the control gate and the first capping nitride film, forming a third sidewall on the side of the second sidewall, and removing a portion of the first conductive layer to form a floating gate Removing the third sidewall, forming a second interpolyoxide film on the exposed side of the floating gate, forming a third conductive layer on the entire surface of the semiconductor substrate, and over the first conductive layer. Forming a second capping oxide film, removing a portion of the third conductive layer to form an erase gate, and forming a fourth sidewall on the exposed side of the second capping oxide film and a side of the erase gate Removing the remaining first capping nitride film to expose a portion of the sub-control gate; and exposing the surface portion of the exposed erase gate and the side surface of the first capping nitride film remaining under the fourth sidewall and the exposed fourth film. With sidewall Forming a fourth conductive layer with a thickness sufficient to fill the valleys and remaining the formed valleys; and forming a main control gate by removing a portion of the fourth conductive layer.

In addition, the gate flash cell of the semiconductor device manufactured according to the present invention comprises a first conductive substrate, a device isolation field oxide film formed on the first conductive substrate, and a gate oxide film formed on the surface of the first conductive substrate between the field oxide film. And a floating gate formed between the field oxide film and a portion of the upper portion of the field oxide film, a first oxide film positioned on the surface of the floating gate except a portion of the side and upper surfaces of the field oxide film and the gate insulating film and the contact portion, and a first oxide film. A sub control gate having a width smaller than the width of the floating gate positioned on the surface thereof, a main control gate in contact with the sub control gate and positioned above the sub control gate, and an upper portion of the main control gate; The second insulating film on the side and the side of the sub control gate, except at the end, and simultaneously on the field oxide film The first insulating gate positioned on the side of the first insulating film and the side of the second insulating film, the third insulating film covering the upper surface of the first insulating gate, the second symmetrically positioned with respect to the floating gate, the sub control gate, and the main gate. It has a structure composed of an erase gate.

1A to 1B are cross-sectional structural views of a structure of a detachable gate flash cell of a semiconductor device according to the related art in a channel length direction and a channel width direction, respectively. 2A to 2E are cross-sectional views of a manufacturing process of a discrete gate flash cell of a semiconductor device in a channel width direction.

3A to 3B are cross-sectional views of the structure of the separate gate flash cell of the semiconductor device in the channel length direction and the channel width direction, respectively.

4A to 4E are cross-sectional views of a manufacturing process of the removable gate flash cell of the semiconductor device according to the present invention, viewed in a channel width direction.

3A to 3B are cross-sectional views of the structure of the separate gate flash cell of the semiconductor device in the channel length direction and the channel width direction, respectively.

As shown in the figure, the longitudinal shape of the channel of the device according to the present invention is the same as the shape of a conventional cell, and thus the operation mechanism of the cell is also the same.

However, in the structure of the channel width direction, as shown in FIG. 3B, the control gate 315 of the cell is present between all the floating gates. Thus, two erase gates are adjacent to the left and right sides of one floating gate. The control gate has a dual structure of the sub control gate 310 and the main control gate 318.

As shown in FIG. 3A, a channel of a separate gate cell has a source / drain section formed with BN + sections 32 and 33, and the channel includes a channel in which the floating gate 38 and the sub control gate 310 overlap, and the sub control. A channel consisting of only the gate 310 is connected to each other. In the cell programming, a high voltage of about 12 V and 7 V is applied to the sub control gate 310 and the drain cushion 33, respectively, so that channel hot electrons generated at the drain terminal of the channel are suspended. 38).

On the other hand, the separate gate flash cell has a separate erase gate for the erase operation of the cell and the control gates 310 and 312 and the control gate 310, as shown in FIG. A process of inserting and removing the erase gate 315 between 312 is used. Each of the erase gates 310 is adjacent to each other with the floating gate 38 of two adjacent cells interposed therebetween.

A separate erase gate 315 is positioned next to the floating gate 38 for the erase operation of the cell. The erasing method uses a poly-poly erasing method, which is a conventional erasing method. However, the difference with the prior art is that since there is an erase gate 315 on both sides of one floating gate, the erase operation can be performed in both directions. That is, there are two erase gates that can be used for erasing a cell, whereas the present invention has two erase gates. Therefore, as the erase count of a cell is increased by one erase gate, when the erase of the cell is disturbed due to the electronic trapping phenomenon, the cell erase operation may be completed by using another erase gate.

4A to 4E are cross-sectional views of a manufacturing process of the removable gate flash cell of the semiconductor device according to the present invention, viewed in a channel width direction.

In FIG. 4A, a field oxide film 35 is formed of silicon by chemical vapor deposition for isolation in a channel width direction on a silicon substrate 31, and then a photolithography process is performed to form an oxide film 35. Defining a field area by removing part of Next, the first HDL layer 36 is deposited on the exposed portions of the remaining field oxide film 35 and the exposed portions of the silicon substrate 31, and then etched back to expose the remaining side oxide portions of the remaining field oxide film 35. After the first sidewall 36 is formed on the gate oxide film 37 by thermal growth on the exposed surface of the substrate 31, the first polysilicon layer 38 for floating gate formation is deposited. . The first interpolyoxide film 39 is grown on the surface of the first polysilicon layer 38 for floating gate formation.

In FIG. 4B, a second polysilicon layer 310 for forming a sub control gate is formed by depositing on the surface of the first interpoly oxide film 39, and again, a first capping nitride film 311 is formed on the 310. It is formed by depositing. Then, a photolithography process using a mask for forming a sub-control gate is performed to protect the first capping nitride film 311, the second polysilicon layer 310, and the first interpoly oxide film 39 which are not protected by the photoresist. Is removed by dry etching to form the sub-control gate 310 by patterning. Subsequently, the first capping nitride film 311 and the second polysilicon layer 310 which are formed by depositing HDL on the entire surface are etched back using the etch stop as a reference to the sub control gate 310 and the first capping nitride film. The second sidewall 312 is formed on the side of the 311, and then a low viscosity boronphospho silicate glass layer is formed on the entire surface and etched back to form a third sidewall of the second sidewall 312. Sidewalls 313 are formed.

In FIG. 4C, a floating gate forming agent is formed by using the remaining first capping nitride film 311 and the BPS third sidewall 313 as a masking material and using the remaining field oxide film 35 as an etch stop layer. 1 Dry etching is performed on the polysilicon layer 38 to form the floating gate 38. Thereafter, the non-PSG third sidewall (not shown) is removed by wet etching to expose a portion of the surface of the floating gate 38 made of the remaining first polysilicon layer. At this time, the level of the exposed part is a level higher than the remaining field oxide film.

In FIG. 4D, the second interpoly oxide film 314 is thermally grown on the exposed side of the floating gate 38 to secure electrical insulation at the exposed portion, and then the third polysilicon layer 315 for forming the erase gate is formed. Is deposited on the entire surface of the substrate 31 and then formed on the 315 by depositing a second capping oxide film 316 for erasing gate with HDL. Then, a part of the second capping oxide layer 316 and the third polysilicon layer 315 are removed by performing a photolithography process using a mask for forming an erase gate to expose the surface of the first nitride layer 311 remaining by dry etching. The erase gate 315 made of the remaining third polysilicon layer 315 by patterning is completed. At this time, the erase gate 315 is formed to be located on both sides of all the floating gate (38). Next, HDL is formed on the entire surface, and then HLC is formed on the side of the second capping oxide layer 316 and the side of the eliminating gate 315 by etching back to expose the surface of the sub control gate 310. A fourth sidewall 317 is formed. And the first capping remaining on the sub control gate 310 using the second capping oxide film 316 of HDL on the erase gate 315 and the fourth sidewall 317 of HDL as a masking material. The nitride film 311 is removed by dry etching so that a part of the sub control gate 310 is exposed.

In FIG. 4E, the valley formed by the exposed surface portion of the erase gate 315, the side surface of the first capping nitride film 311 remaining under the fourth sidewall 317, and the exposed fourth sidewall 317 is sufficiently buried. Polysilicon and silicide are deposited to the remaining thickness, and then the main control gate 318 is formed by performing a photolithography process using a mask for forming a main control gate.

When a high voltage is applied to the erasing gate 315 for the erasing operation, the strongest electric field is generated at the lower side edge portion of the floating gate 38, so Fowler-Nordheim tunneling is performed at this corner portion. .

Therefore, in the present invention, since two erase gates correspond to one floating gate unlike the related art, when the threshold voltage of an erased cell increases as the number of erased cells using one erase gate increases, an extra other An erase operation of the cell may be performed using the erase gate. As a result, the number of times of rewriting can be increased by at least twice as compared with the conventional cell erase operation.

And since the structure of the cell has a perfect symmetry structure, the flatness within the cell array is improved because it does not cause a large height step in the cell array, thereby reducing the difficulty of the metal process.

In addition, since the control gate has a dual structure consisting of a sub control gate and a main control gate, the main control gate positioned at the upper portion may be made of a material having a low resistance such as silicide. Therefore, the resistance of the word line in the cell array is reduced, which is advantageous for the high speed read operation. In addition, since it is not necessary to strap the metal line on the control gate to reduce the resistance of the word line, the width of the cell can be made smaller than that of the conventional cell, which is advantageous in high integration of the device.

Claims (8)

Defining a field region by forming a field oxide film on the first conductive semiconductor substrate; Forming a first sidewall on an exposed side portion of the field oxide film remaining as a first HD layer on an exposed part of the remaining field oxide film and an exposed part of the semiconductor substrate; Forming a gate oxide film on the exposed surface of the semiconductor substrate; Depositing a first conductive layer on the gate oxide film; Forming a first interpoly oxide film on a surface of the first conductive layer; Forming a second conductive layer on the surface of the first interpolyoxide film; Forming a first capping nitride film on the surface of the second conductive layer; Removing a portion of the first capping nitride film, the second conductive layer, and the first interpoly oxide film to form a sub control gate; Forming a second sidewall on side surfaces of the sub control gate and the first capping nitride film; Forming a third sidewall at a side of the second sidewall; Removing a portion of the first conductive layer to form a floating gate; Removing the third sidewall; Forming a second interpoly oxide film on the exposed side of the floating gate; Forming a third conductive layer on the entire surface of the semiconductor substrate; Forming a second capping oxide film on the first conductive layer; Removing a portion of the third conductive layer to form an erase gate; Forming a fourth sidewall on a side surface of the exposed second capping oxide layer and a side surface of the erase gate; Removing the remaining first capping nitride film to expose a portion of the sub control gate; Forming a fourth conductive layer with a thickness sufficient to fill a valley formed by the exposed surface portion of the erase gate and the side surface of the first capping nitride film remaining under the fourth sidewall and the exposed fourth sidewall. Steps, Removing a portion of the fourth conductive layer to form a main control gate. The method of claim 1, wherein the first sidewall, the second sidewall, the fourth sidewall, and the second capping oxide layer are formed of HDL. The method of claim 1, wherein the third sidewall is formed by depositing non-PS paper. The method of claim 1, wherein the floating gate is dry-etched to the first conductive layer by using the remaining first capping nitride film and the third sidewall as a masking material and using the remaining surface oxide film surface as an etch stop layer. And forming a gate flash cell of the semiconductor device. The method of claim 1, wherein the first conductive layer, the second conductive layer, and the third conductive layer are formed of doped polysilicon. The method of claim 1, wherein the fourth conductive layer is formed by depositing doped polysilicon and silicide. A first conductivity type substrate, A device isolation field oxide film formed on the first conductivity type substrate; A gate oxide film formed on a surface of the first conductivity type substrate different from the field oxide film; A floating gate formed between the field oxide film and a portion of an upper portion of the field oxide film; A first oxide film positioned on a part of a side surface and an upper surface of the field oxide film and a surface of the floating gate except for a contact portion with the gate insulating film; A sub control gate positioned on the surface of the first oxide film and having a width smaller than a width of a floating gate positioned below the first gate; A main control gate in contact with the sub control gate and positioned above the sub control gate; A second insulating film disposed on a side surface and a side surface of the sub control gate except for an upper end portion of the main control gate; A first erase gate positioned on the side surface of the first insulating film and the side of the second insulating film simultaneously with the field oxide film; A third insulating film covering an upper surface of the first erase gate; And a second erase gate positioned symmetrically with respect to the floating gate, the sub-control gate, and the main gate. 8. The gate flash cell of claim 7, wherein the second erase gate has the same structure as the first erase gate.

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