KR20080048267A - Driving liquid crystal display and apparatus for driving the same - Google Patents

Abstract

An LCD device and a driving method thereof are provided to generate positive/negative analog gamma compensating voltages into voltages with gray levels lower than one gray level or two gray levels to reduce the analog voltage of second data compared with first data out of two data of the same polarity when an LCD panel operates in a two-dot inversion method, thereby preventing moire generated by a difference between the charge characteristics of the first and second data to display the image of high quality. In an LCD(Liquid Crystal Display) panel(84), gate lines(G1~Gn) and data lines(D1~Dm) cross each other, and liquid crystal cells(Clc) are arranged in a matrix. A control signal generating circuit generates a polarity control signal for directing the polarity inversion of a data voltage by N horizontal cycle(N is an integer more than two) and generates a compensated polarity control signal(POL_comp) with a shorter cycle than that of the polarity control signal. A gamma voltage generating circuit generates an analog gamma compensating voltage corresponding to gray levels displayed on an LCD panel and controls the analog gamma compensating voltage in response to the compensated polarity control signal. A data driving circuit(82) converts digital video data into the analog gamma compensating voltage in response to the polarity control signal to generate an analog data voltage and supply the analog data voltage to the data lines.

Description

Liquid crystal display and its driving method {DRIVING LIQUID CRYSTAL DISPLAY AND APPARATUS FOR DRIVING THE SAME}

1 is a view schematically showing the data polarity of a liquid crystal panel driven in a one dot inversion scheme.

FIG. 2 is a diagram schematically illustrating data polarity of a liquid crystal panel driven in a two dot inversion scheme. FIG.

3 is a waveform diagram showing a polarity control signal and a data voltage generated in a one dot inversion scheme.

4 is a waveform diagram showing a polarity control signal and a data voltage generated in a 2-dot inversion scheme.

5 is a block diagram schematically illustrating a liquid crystal display device driven in a two dot inversion scheme.

6 is an enlarged view illustrating a 4 × 4 liquid crystal cell matrix in the liquid crystal panel of FIGS. 3 and 8.

FIG. 7 is a waveform diagram illustrating a data voltage and a scan pulse of a 2-dot inversion method charged in a liquid crystal cell matrix as shown in FIG. 6.

8 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

9 is a waveform diagram illustrating a polarity control signal, a compensation polarity control signal, and a data voltage shown in FIG. 8;

FIG. 10 is a circuit diagram showing in detail the data driving circuit shown in FIG. 8; FIG.

FIG. 11 is a circuit diagram showing a switch circuit connected to the first divided resistor row shown in FIG. 10 and the divided resistor row;

FIG. 12 is a circuit diagram showing a switch circuit connected to the second divided resistor row shown in FIG. 10 and the divided resistor row;

<Description of Symbols for Main Parts of Drawings>

41, 81: timing controller 42, 82: data drive circuit

43, 83: gate driving circuit 44, 84: liquid crystal panel

101: shift register 102: latch

103: DAC 104: output circuit

106: register 111: positive DAC

112: Negative DAC 113: Multiplexer

114, 115: Dividing resistance heat

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof for improving display quality of a liquid crystal display device driven by a 2-dot inversion method.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. In an active matrix type liquid crystal display, switching elements are formed in each liquid crystal cell, which is advantageous for displaying a moving image. As the switching device, a thin film transistor (hereinafter referred to as "TFT") is mainly used.

The LCD is driven in an inversion manner to reduce flicker and afterimage by periodically inverting the polarity of data charged in the liquid crystal cell. The inversion method includes a line inversion method for inverting polarities of data between adjacent liquid crystal cells in a vertical line direction, a column inversion method for inverting polarities of data between adjacent liquid crystal cells in a horizontal line direction, a vertical line direction and a horizontal line direction. There is a dot inversion method of inverting the polarity of data between adjacent liquid crystal cells. Among these inversion methods, the dot inversion method shows little flicker in the vertical and horizontal directions.

In the one-dot inversion method, as shown in FIG. 1, polarities of data supplied to adjacent liquid crystal cells in the vertical direction are opposite to each other, and polarities of data supplied to adjacent liquid crystal cells in the horizontal direction are opposite to each other. The polarity of the data is inverted every frame (Fn-1, Fn). This one-dot inversion method is most commonly used in liquid crystal display devices because flicker is small in both the vertical and horizontal directions.

In the two-dot inversion scheme, as shown in FIG. 2, the polarity of the data is inverted by two dots in the vertical direction, that is, two liquid crystal cells. The two-dot inversion method has lower power consumption and relatively smaller flicker in both the vertical and horizontal directions than the one-dot inversion method as shown in FIG.

3 shows an example of the data voltage and the polarity control signal POL1 in the one dot inversion scheme. 4 shows an example of the data voltage and the polarity control signal POL2 in the 2-dot inversion scheme.

3 and 4, the polarity control signals POL1 and POL2 select the positive data voltage and the negative data voltage output from the digital-analog converter in the data drive integrated circuit. Therefore, the polarity of the data voltage is determined by the polarity control signals POL1 and POL2. The polarity control signal POL1 of the one dot inversion scheme as shown in FIG. 3 inverts the polarity in units of one horizontal period 1H, thereby inverting the polarity of the data voltages supplied to the data lines in every horizontal period. The polarity control signal POL2 of the two-dot inversion method as shown in FIG. 4 inverts the polarity in units of two horizontal periods 2H, thereby inverting the polarity of data voltages supplied to the data lines in units of two horizontal periods.

5 schematically illustrates a conventional liquid crystal display device driven in a two dot inversion method. FIG. 6 is an equivalent circuit diagram of a lower array substrate of a 4 × 4 liquid crystal cell matrix of the liquid crystal panel illustrated in FIG. 5.

Referring to FIGS. 5 and 6, the liquid crystal display according to the related art has a liquid crystal in which data lines D1 to Dm and gate lines G1 to Gn cross each other, and TFTs for driving the liquid crystal cell Clc are formed at the intersections thereof. Scan pulses are applied to the panel 44, the data driver circuit 42 for supplying data to the data lines D1 to Dm of the liquid crystal panel 44, and the gate lines G1 to Gn of the liquid crystal panel 44. A gate driving circuit 43 for supplying, and a timing controller 41 for controlling the data driving circuit 42 and the gate driving circuit 43 are provided.

The data driving circuit 42 inverts the polarity of the data voltages supplied to the data lines D1 to Dm in units of two horizontal periods in response to the polarity control signal POL2 supplied from the timing controller 41, and inverts the data voltages. Is supplied to the data lines D1 to Dm.

The gate driving circuit 43 sequentially supplies scan pulses to the gate lines G1 to Gn under the control of the timing controller 41.

The timing controller 41 controls the gate control signal GDC and the data driving circuit 42 for controlling the gate driving circuit 43 by using the vertical / horizontal synchronization signals V and H and the clock CLK. To generate a data control signal DDC. The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE, a polarity control signal POL2, and the like. The gate control signal GDC includes a gate shift clock GSC, a gate output enable GOE, a gate start pulse GSP, and the like.

FIG. 7 illustrates polarities and scan pulses of the data voltages supplied to the first to fourth liquid crystal cells A to D arranged in the first column in the 4 × 4 liquid crystal cell matrix shown in FIG. 6. In FIG. 7, reference numerals GP1 to GP4 denote scan pulses applied to the gate lines G1 to G4.

6 and 7, the liquid crystal display of the two dot inversion method inverts the polarity of the data voltage every two horizontal periods. Therefore, among the liquid crystal cells A to D of the first column supplied with data by the first data line DL1, the liquid crystal cell A of the first horizontal line and the liquid crystal cell B of the second horizontal line are common. While a positive data voltage higher than the voltage Vcom is applied, the liquid crystal cell C of the third horizontal line HL3 and the liquid crystal cell D of the fourth horizontal line HL4 are less than the common voltage Vcom. A low negative data voltage is applied.

However, in the two-dot inversion method, the amount of charge of the data charged in the liquid crystal cell to which the positive data voltage rising from the negative data voltage is applied and the liquid crystal cell to which the other positive data voltage is supplied subsequent to the positive data voltage are different. . In addition, in the two-dot inversion method, the amount of charge of data charged in a liquid crystal cell to which a negative data voltage descending from the positive data voltage is applied is different from a liquid crystal cell to which another negative data voltage is applied subsequent to the negative data voltage. do.

This means that the rising time of changing from the negative data voltage to the positive data voltage of the opposite polarity or the falling time of changing from the positive data voltage to the negative data voltage of the opposite polarity is very long. . On the contrary, the rising time of changing from the positive data voltage to the positive data voltage of such polarity or the falling time of changing from the negative data voltage to the negative data voltage of such polarity is relatively small.

Due to such a difference in charging characteristics, even when the data voltage of the same gray level is compared with the liquid crystal cells A and C of the first and third horizontal lines HL1 and HL3 in the normally black mode, The liquid crystal cells B and D of the second and fourth horizontal lines HL2 and HL4 appear brighter, and the liquid crystals of the first and third horizontal lines HL1 and HL3 are displayed in the normally white mode. Compared to the cells A and C, the liquid crystal cells B and D of the second and fourth horizontal lines HL2 and HL4 appear darker. As a result, in the two-dot inversion scheme, the luminance difference between the horizontal lines is generated according to whether or not the polarity of the previously generated data voltage and the subsequent data voltage is changed.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof to improve the display quality of a liquid crystal display device driven by a 2-dot inversion method.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention comprises a liquid crystal panel in which data lines and gate lines intersect and liquid crystal cells are arranged in a matrix form; A control signal generation circuit for generating a polarity control signal for instructing polarity inversion of the data voltage in units of N (N is a positive integer of two or more) horizontal periods and for generating a compensation polarity control signal having a period shorter than the polarity control signal; A gamma voltage generation circuit generating an analog gamma compensation voltage corresponding to the gray levels represented in the liquid crystal panel and adjusting the analog gamma compensation voltage in response to the compensation polarity control signal; And a data driving circuit for converting digital video data into the analog gamma compensation voltage in response to the polarity control signal to generate an analog data voltage and supplying the analog data voltage to the data lines.

In response to the compensation polarity control signal, the gamma voltage generation circuit lowers the voltage of the analog gamma compensation voltages to a voltage of 1 to 2 gradations represented by the liquid crystal panel.

The gamma voltage generation circuit includes a first voltage divider resistor circuit for dividing a plurality of positive gamma reference voltages; And a second divided resistor circuit for dividing the plurality of negative gamma reference voltages.

The first divided resistor circuit includes a first node for outputting a high potential voltage and a second node for outputting a low potential voltage.

And a switch circuit configured to select one of the high potential voltage and the low potential voltage as the analog gamma compensation voltage in response to the compensation polarity control signal, and supply the selected voltage to the data driving circuit through an output node.

The switch circuit includes a source electrode connected to the first node, a drain electrode connected to the output node, and a gate electrode to which a compensation polarity control signal is supplied, the high voltage in response to a low logic voltage of the compensation polarity control signal. A p-type MOS-FET that outputs the above voltage through the output node; And the low potential in response to the high logic voltage of the compensation polarity control signal, including a source electrode connected to the second node, a drain electrode connected to the output node, and a gate electrode to which the compensation polarity control signal is supplied. And an n-type MOS-FET for outputting a voltage through the output node.

The low potential voltage is a voltage of 1 to 2 grays lower than that of the high potential voltage.

The second divided resistor circuit includes a third node for outputting a low potential voltage and a fourth node for outputting a high potential voltage.

And a switch circuit configured to select one of the low potential voltage and the high potential voltage as the analog gamma compensation voltage in response to the compensation polarity control signal, and supply the selected voltage to the data driving circuit through an output node.

The switch circuit includes a source electrode connected to the third node, a drain electrode connected to the output node, and a gate electrode to which a compensation polarity control signal is supplied, the low voltage in response to a low logic voltage of the compensation polarity control signal. A p-type MOS-FET for outputting a potential voltage through the output node; And a high potential voltage in response to the high logic voltage of the compensation polarity control signal, including a source electrode connected to the fourth node, a drain electrode connected to the output node, and a gate electrode to which the compensation polarity control signal is supplied. And an n-type MOS-FET for outputting through the output node.

The high potential voltage is a voltage of 1 to 2 grays lower than that of the low potential voltage.

The logic control signal is inverted in a logic value in units of two horizontal periods, and the compensation polarity control signal is inverted in a logic value in units of one horizontal period.

The logic value of the compensation polarity control signal is inverted when the logic value of the polarity control signal is inverted and inverted within a period in which the logic value of the polarity control signal is maintained.

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention includes generating a polarity control signal instructing polarity inversion of a data voltage in units of N (N is a positive integer of 2 or more) horizontal period; Generating a compensation polarity control signal having a shorter period than the polarity control signal; Generating an analog gamma compensation voltage corresponding to the gray levels represented in the liquid crystal panel; Adjusting the analog gamma compensation voltage in response to the compensation polarity control signal; Converting digital video data into the analog gamma compensation voltage in response to the polarity control signal to generate an analog data voltage; And supplying the analog data voltages to data lines.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 8 to 10.

8 and 9, in the liquid crystal display according to the exemplary embodiment of the present invention, the analog data voltages supplied to the data lines D1 to Dm of the liquid crystal panel 84 in response to the compensation polarity control signal POL_comp. And the gate lines of the data driving circuit 82 and the liquid crystal panel 84 for inverting the polarity of the analog data voltage to be supplied to the liquid crystal panel 84 in units of two horizontal periods in response to the two-dot polarity control signal POL2. And a timing controller 81 for controlling the data driving circuit 82 and the gate driving circuit 83 for supplying scan pulses to the G1 to Gn.

In the liquid crystal panel 84, liquid crystal is injected between two glass substrates. The data lines D1 to Dm and the gate lines G1 to Gn formed on the lower glass substrate of the liquid crystal panel 84 are orthogonal to each other with an insulator interposed therebetween. The TFTs formed at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn liquid crystal the data on the data lines D1 to Dm in response to a scan pulse from the gate lines G1 to Gn. It supplies to the cell Clc. For this purpose, the gate electrodes of the TFTs are connected to the gate lines G1 to Gn, and the source electrodes are connected to the data lines D1 to Dm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. The common voltage Vcom is supplied to the common electrode facing the pixel electrode. Reference numeral 'Cst' denotes a storage capacitor. The storage capacitor Cst may be formed between the liquid crystal cell Clc connected to the k-th gate line (where k is a positive integer between 1 and n) and the k-1 th front gate line.

The data driving circuit 82 receives second analog data among two analog data voltages to be successively supplied to the data lines D1 to Dm with the same polarity in response to the compensation polarity control signal POL_comp from the timing controller 81. The charging voltage of the second analog data voltage compared to the first analog data voltage is compensated by converting the voltage into one or two gray analog data voltages. One period of the compensation polarity control signal POL_comp corresponds to two horizontal periods 2H as shown in FIG. 9, and its pulse width corresponds to one horizontal period 1H. Meanwhile, the period of the 2-dot polarity control signal POL2 for determining the polarity of the analog data voltage to be supplied to the data lines D1 to Dm corresponds to 4 horizontal periods as shown in FIG. 9, and the pulse width is 2 horizontal. It corresponds to period 2H. The compensation polarity control signal POL_comp is inverted to a high logic voltage at approximately 1/2 of the two-dot polarity control signal POL2 in which the two-dot polarity control signal POL2 maintains the high logic voltage or the low logic voltage.

In response to the 2-dot polarity control signal POL from the timing controller 81, the data driving circuit 82 horizontally adjusts the polarity of the analog data voltages using the positive / negative analog gamma compensation voltage. Invert by period. This data driving circuit 82 will be described in detail with reference to FIG. 10.

The gate driving circuit 83 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the control signal GDC from the timing controller 81.

The timing controller 81 controls the gate control signal GDC and the data driving circuit 82 to control the gate driving circuit 83 by using the vertical / horizontal synchronization signals V and H and the clock CLK. Generates a data control signal DDC (POL2) and a compensation polarity control signal POL_comp. The data control signal DDC POL2 includes a source start pulse SSP, a source shift clock SSC, a source output signal SOE, a 2-dot polarity control signal POL2, and the like. The gate control signal GDC includes a gate shift clock GSC, a gate output signal GOE, a gate start pulse GSP, and the like.

This liquid crystal display device includes a DC-DC converter (not shown). The DC-DC converter boosts or decompresses a DC power having a voltage of about 3.0V, ie, the driving voltage of the liquid crystal panel 42, that is, the common voltage Vcom and the gate driving circuit 83 supplied to the common electrode of the liquid crystal cell Clc. A gate high voltage supplied to the gate high voltage to determine the high logic voltage of the scan pulse, and supplied to the gate driving circuit 83 to generate a gate low voltage to determine the low logic voltage of the scan pulse. . In addition, the gamma reference voltage generation circuit in the DC-DC converter uses five or six positive gamma reference voltages (PGMA) between the high potential driving voltage (VDD) and the low potential driving voltage (VSS) using a voltage divider resistor circuit. And generate five or six negative gamma reference voltages (NGMA). The positive / negative gamma reference voltages PGMA and NGMA are supplied to the data driving circuit 82, and each gray level, for example, digital video data is 6 bits by a divided resistor circuit in the data driving circuit 82, 2 ^6. The voltage is redivided into (= 64) positive analog gamma compensation voltages and 2 ⁶ (= 64) positive analog gamma compensation voltages.

The two-dot inversion driving of the liquid crystal display according to the present invention will be described as follows.

6 and 9, the two-dot inversion driving method according to the present invention includes a two-dot polarity control signal POL2 and a two-dot polarity control signal POL whose polarities are inverted in units of two horizontal periods (2H). A compensation polarity control signal POL_comp is generated which is inverted to a low logic potential at each of the rising edge and the falling edge of and is inverted to a high logic potential at approximately half of the pulse width period of the 2-dot polarity control signal POL.

In the two-dot inversion method, positive polarity is applied to the liquid crystal cell A of the first horizontal line HL1 and the liquid crystal cell B of the second horizontal line HL2 among the liquid crystal cells A to D in the first row. The data voltage is supplied. At this time, the two-dot polarity control signal POL2 maintains a high voltage, and the compensation polarity control signal POL_comp is low during the period in which the liquid crystal cell A of the first horizontal line HL1 maintains the positive polarity data voltage. After maintaining the logic potential, when the positive data voltage starts to be supplied to the liquid crystal cell B of the second horizontal line HL2, it is inverted to a high logic potential and maintains the high logic potential for one horizontal period (1H). do. When the compensation polarity control signal POL_comp is changed to the high logic potential, the analog gamma compensation voltage to be supplied to the data lines D1 to Dm is changed to a voltage as low as one gray level or two gray levels. That is, according to the present invention, the positive data voltage to be charged in the liquid crystal cell B of the second horizontal line HL2 is lowered to the positive data voltage of one gray level or two gray levels lower than the original gray level of the digital video data.

A negative data voltage is supplied to the liquid crystal cell C of the third horizontal line HL3 and the liquid crystal cell D of the fourth horizontal line HL4 among the liquid crystal cells A to D in the first column. At this time, the 2-dot polarity control signal POL2 maintains a low logic potential, and the compensation polarity control signal POL_comp is provided during the period in which the liquid crystal cell C of the third horizontal line HL3 maintains the negative data voltage. After maintaining the low logic potential, the negative logic voltage is reversed to the high logic potential at the time when the negative data voltage starts to be supplied to the liquid crystal cell D of the fourth horizontal line HL4, and the high logic potential is changed for one horizontal period (1H). Keep it. When the compensation polarity control signal POL_comp changes to a high voltage, the analog data voltage to be supplied to the data lines is a negative analog data voltage having an absolute value of one gray level or two grays lower than the original gray level of the digital video data RGB. Change.

For example, if the second positive analog data voltage corresponding to the original gray level of the input digital video data is 5V higher than the common voltage Vcom, the data driving circuit 82 according to the embodiment of the present invention has one gray level or two gray levels higher than that. The low 4.8V is output as the second positive analog data voltage. In addition, the data driving circuit 82 adds 1.2 V, which is one gray level or two gray levels lower than the second gray level, if the second negative analog data voltage corresponding to the original gray level of the input digital video data is 1 V lower than the common voltage Vcom. Output as a polarity analog data voltage.

Due to the adjustment of the second positive / negative analog data voltage, the liquid crystal display according to the exemplary embodiment of the present invention uses the first and third horizontal lines in the normally black mode when the two-dot inversion driving method is applied. Compared to the liquid crystal cells A and C of the HL1 and HL3, the phenomenon in which the liquid crystal cells B and D of the second and fourth horizontal lines HL2 and HL4 appear brighter can be prevented. In the mode, the liquid crystal cells B and D of the second and fourth horizontal lines HL2 and HL4 are darker than the liquid crystal cells A and C of the first and third horizontal lines HL1 and HL3. You can prevent the visible phenomenon.

10 schematically shows the data driving circuit 82.

Referring to FIG. 10, the data driving circuit 82 includes a plurality of data integrated circuits, each of which register 106 receives digital video data RGB from the timing controller 81. ), A shift register 101 for sequentially generating a sampling signal, a latch 102 and a digital-to-analog converter (hereinafter, digitally connected) that are cascaded between the register 106 and the data lines D1 to Dm. 103), and an output circuit 104. The " DAC " In addition, each of the integrated circuits of the data driving circuit includes a first divided resistor string 114 for generating positive analog gamma compensation voltages PG1 to PG64 corresponding to each gray level, and a negative analog corresponding to each gray level. The second voltage divider resistor 115 generates gamma compensation voltages NG1 to NG64.

The register 106 temporarily stores digital video data RGB inputted in series from the timing controller 81, and supplies the digital video data RGB to the latch 102 in parallel.

The shift register 101 shifts the source start pulse SSP from the timing controller 81 in accordance with the source shift clock signal SSC to generate a sampling signal. In addition, the shift register 101 shifts the source start pulse SSP to transfer a carry signal to the integrated circuit of the next stage.

The latch 102 sequentially samples and latches the digital video data RGB according to the sampling signal input from the shift register 101, and then supplies the latched digital video data RGB to the DAC 104 simultaneously. .

The first divided resistor string 114 divides a plurality of positive gamma reference voltages PGMA input from an external gamma reference voltage generator circuit, thereby representing 64 positive analog gamma compensations represented by 6-bit digital video data. Voltages PG1 to PG64 are generated and the gamma compensation voltages PG1 to PG64 are supplied to the DAC 103. The first divided resistor string 114 outputs the positive analog gamma compensation voltage as one gray level or two gray levels low when the compensation polarity control signal POL_comp is generated at a high logic potential.

The second divided resistor string 115 divides a plurality of negative gamma reference voltages (NGMA) input from an external gamma reference voltage generator, thereby representing 64 negative analog gamma compensations represented by 6-bit digital video data. Voltages NG1 to NG64 are generated and the gamma compensation voltages NG1 to NG64 are supplied to the DAC 103. The second voltage divider resistor 115 outputs the negative analog gamma compensation voltage as one gray level or two gray levels low when the compensation polarity control signal POL_comp is generated at a high logic potential.

The DAC 103 includes a positive DAC 111, a negative DAC 112, and a multiplexer 113.

The positive DAC 111 decodes the digital video data and converts the positive analog data voltage corresponding to the gray level of the digital video data to the positive analog gamma compensation voltages PG1 to PG64 from the first voltage divider resistor 114. Choose from. The positive DAC 111 outputs the second generated positive data voltage among the two positive data voltages sequentially generated in the positive polarity with a voltage of one gray level or two gray levels lower. This is because the positive analog gamma compensation voltages PG1 to PG64 corresponding to the respective gray levels from the first voltage divider 114 are lowered by one or two gray levels when the compensation polarity control signal POL_comp is generated at a high logic potential. This is because the voltage is supplied to the positive DAC 111 by the voltage.

The negative DAC 112 decodes the digital video data and converts the negative analog data voltage corresponding to the gray level of the digital video data from the second voltage divider resistor string 115 to the negative analog gamma compensation voltages NG1 to NG64. Choose from. The negative DAC 112 outputs the second generated negative data voltage as one gray level or two gray low voltages, respectively, from among the two negative data voltages sequentially generated in the negative polarity. This is because the negative analog gamma compensation voltages PG1 to PG64 corresponding to the respective grayscales from the second voltage divider resistance 115 when the compensation polarity control signal POL_comp is generated at the high logic potential are 1 gray or 2 gray low. This is because the voltage is supplied to the negative DAC 112 by the voltage.

The multiplexer 113 selects the positive analog gamma compensation voltages from the positive DAC 111 and the negative analog gamma compensation voltages from the negative DAC 112 in response to the 2-dot polarity control signal POL2. Therefore, the positive analog data voltages and the negative analog data voltages supplied from the multiplexer 113 to the data lines D1 to Dm are alternated in units of two horizontal periods.

The output circuit 104 has an output buffer connected between the DAC 103 and the data lines D1 to Dm to reduce the loss of the positive / negative analog data voltages supplied to the data lines D1 to Dm. Include.

11 and 12 are circuit diagrams illustrating the first and second voltage divider resistor lines 114 and 115 in detail.

Referring to FIG. 11, the first divided resistor string 114 divides the positive polarity gamma reference voltages PGMA between the high potential driving voltage VDD and the common voltage Vcom, thereby providing the standard positive polarity analog gamma compensation voltages. The voltages of the standard positive analog gamma compensation voltages (+ V1, + V2) in response to the plurality of resistors R11 and R12 that output (+ V1 and + V2) and the compensation polarity control signal POL_comp It is equipped with adjusting switch elements PT and NT. The high potential driving voltage VDD is higher than the common voltage Vcom and is a voltage representing the highest gray level among the positive analog data voltages supplied to the liquid crystal panel 84. The common voltage Vcom is a voltage supplied to the common electrode facing the pixel electrode of the liquid crystal cell. The gray level is lower for the positive analog data voltage closer to the common voltage Vcom.

The standard positive analog gamma compensation voltages (+ V1, + V2) are divided by the resistors (R11, R12) of the divided resistor string 114, and the nodes (n1, n2) between the resistors (R11, R12). Is output from

The switch elements PT and NT have a p-type MOS-FET (PT) connected in a push-pull form between neighboring standard gamma voltage output nodes n1 and n2 and an n-type MOS-FET (NT). do. These switch elements PT and NT adjust the gray voltages of the standard positive analog gamma compensation voltages + V1 and + V2 in response to the compensation polarity control signal POL_comp. Here, the gray scale voltage refers to a voltage of the positive analog gamma compensation voltage corresponding to the gray scale represented by the liquid crystal panel. Lowering the gradation voltage of the positive analog gamma compensation voltage means that the potential difference between the positive data voltage and the common voltage supplied to the data lines is lowered, so that the gradation of the positive analog gamma compensation voltage is lowered. Increasing the voltage means that the potential difference between the positive data voltage and the common voltage supplied to the data lines is increased, thereby increasing the gray level.

The p-type MOS-FET PT has a source electrode connected to the high potential node n1 of the divided resistance row, a drain electrode connected to the compensation voltage output node nO1, and a gate to which the compensation polarity control signal POL_comp is supplied. An electrode. The p-type MOS-FET PT supplies the high potential standard positive gamma voltage (+ V1) output from the high potential node n1 to the DAC 103 in response to the low logic potential of the compensation polarity control signal POL_comp. While outputting the positive analog gamma compensation voltage to be supplied, the current path between the high potential node n1 and the compensation voltage output node nO1 is blocked when the compensation polarity control signal POL_comp has a high logic potential.

The n-type MOS-FET NT has a source electrode connected to the low potential node n2 of the divided resistance row, a drain electrode connected to the compensation voltage output node nO1, and a gate electrode supplied with the compensation polarity control signal POL_comp. It includes. The n-type MOS-FET NT supplies a low potential standard positive gamma voltage (+ V2) output from the low potential node n2 to the DAC 103 in response to the high logic potential of the compensation polarity control signal POL_comp. While outputting the positive analog gamma compensation voltage to be supplied, the current path between the low potential node n2 and the compensation voltage output node nO1 is blocked when the compensation polarity control signal POL_comp has a low logic potential. The low potential standard positive gamma voltage (+ V2) is a voltage of one gray level or two gray levels lower than the high potential standard positive gamma voltage (+ V1).

Referring to FIG. 12, the second divided resistor string 115 divides the negative gamma reference voltages NGMA between the low potential driving voltage VSS and the common voltage Vcom, and thus the standard negative analog gamma compensation voltages. Adjust the voltages of the standard negative polarity gamma compensation voltages (-V1 and -V2) in response to the plurality of resistors R21 and R22 outputting (-V1 and -V2) and the compensation polarity control signal POL_comp. It is equipped with switch elements (PT, NT). The low potential driving voltage VSS is a voltage lower than the common voltage Vcom and represents a highest gray level among the negative analog data voltages supplied to the liquid crystal panel 84. The common voltage Vcom is a voltage supplied to the common electrode facing the pixel electrode of the liquid crystal cell. The gray scale is lower for the negative analog data voltage closer to the common voltage Vcom.

The standard negative analog gamma compensation voltages (-V1, -V2) are divided by the resistors R21 and R22 of the divided resistor string 115, and the nodes n3 and n4 between the resistors R21 and R22 are divided. Is output from

The switch elements PT and NT have a p-type MOS-FET (PT) connected in a push-pull form between neighboring standard gamma voltage output nodes n3 and n4, and an n-type MOS-FET (NT). do. The switch elements PT and NT adjust the gray scale voltages of the standard negative analog gamma compensation voltages + V1 and + V2 in response to the compensation polarity control signal POL_comp. Here, the gray scale voltage refers to a voltage of the negative analog gamma compensation voltage corresponding to the gray scale represented by the liquid crystal panel. Lowering the gradation voltage of the negative analog gamma compensation voltage means that the potential difference between the negative data voltage and the common voltage supplied to the data lines is lowered, so that the gradation of the negative analog gamma compensation voltage is lowered. Increasing the voltage means that the potential difference between the negative data voltage and the common voltage supplied to the data lines is increased, thereby increasing the gray level.

The p-type MOS-FET PT has a source electrode connected to the low potential node n3 of the divided resistor row 115, a drain electrode connected to the compensation voltage output node nO2, and a compensation polarity control signal POL_comp. And a gate electrode to be supplied. The p-type MOS-FET PT supplies the low potential standard negative polarity gamma voltage -V1 output from the low potential node n3 to the DAC 103 in response to the low logic potential of the compensation polarity control signal POL_comp. While outputting the negative analog gamma compensation voltage to be supplied, the current path between the low potential node n3 and the compensation voltage output node nO2 is blocked when the compensation polarity control signal POL_comp has a high logic potential.

The n-type MOS-FET NT has a source electrode connected to the high potential node n4 of the divided resistor row 115, a drain electrode connected to the compensation voltage output node nO2, and a compensation polarity control signal POL_comp. And a gate electrode to be supplied. The n-type MOS-FET NT supplies a high potential standard positive gamma voltage (-V2) output from the high potential node n4 to the DAC 103 in response to the high logic potential of the compensation polarity control signal POL_comp. While outputting the negative analog gamma compensation voltage to be supplied, the current path between the high potential node n2 and the compensation voltage output node nO is blocked when the compensation polarity control signal POL_comp has a low logic potential. The high potential standard negative gamma voltage (-V4) is higher in voltage than the low potential standard positive gamma voltage (-V1) but is relatively close to the common voltage (Vcom) and is one or two gray voltages lower.

As a result, the switch elements PT and NT supply the DAC 103 with one or two gray levels lower than the standard positive / negative gamma voltage when the compensation polarity control signal POL_comp is generated at a high logic potential. On the other hand, when the compensation polarity control signal POL_comp maintains the low logic potential, the standard positive / negative gamma voltage is supplied to the DAC 103 as it is.

As described above, the liquid crystal display and the driving method thereof according to the present invention provide two dots by selectively generating the positive / negative analog gamma compensation voltages supplied to the DAC of the data driving circuit with a voltage of one gray level or two gray levels low. When driving the liquid crystal panel by the inversion method, the analog voltage of the second data having a larger charging characteristic is lowered than the first data among the two data of the same polarity. Therefore, the present invention can prevent streaks that may occur due to differences in charging characteristics in the two-dot inversion driving method, so that images can be displayed with high quality without streaks.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. For example, although the embodiment of the present invention has been described based on the dot inversion method, N (where N is a positive integer of 2 or more) may also be applied to the dot inversion method. In addition, embodiments disclosed in the detailed description of the invention may be used in combination. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (17)

A liquid crystal panel in which data lines and gate lines intersect and liquid crystal cells are arranged in a matrix; A control signal generation circuit for generating a polarity control signal for instructing polarity inversion of the data voltage in units of N (N is a positive integer of two or more) horizontal periods and for generating a compensation polarity control signal having a period shorter than the polarity control signal; A gamma voltage generation circuit for generating an analog gamma compensation voltage corresponding to the gray levels represented in the liquid crystal panel and adjusting the analog gamma compensation voltage in response to the compensation polarity control signal; And And a data driving circuit for converting digital video data into the analog gamma compensation voltage in response to the polarity control signal to generate an analog data voltage and supplying the analog data voltage to the data lines. . The method of claim 1, The gamma voltage generation circuit, And in response to the compensation polarity control signal, lower the voltage of the analog gamma compensation voltages to a voltage of 1 to 2 gradations represented by the liquid crystal panel. The method of claim 1, The gamma voltage generation circuit, A first divided resistor circuit for dividing the plurality of positive gamma reference voltages; And And a second divided resistor circuit for dividing the plurality of negative gamma reference voltages. The method of claim 3, wherein The first voltage divider resistance circuit, A first node for outputting a high potential voltage, And a second node for outputting a low potential voltage. The method of claim 4, wherein And a switch circuit for selecting one of the high potential voltage and the low potential voltage as the analog gamma compensation voltage in response to the compensation polarity control signal, and supplying the selected voltage to the data driving circuit through an output node. A liquid crystal display device. The method of claim 5, wherein The switch circuit, The high potential voltage in response to a low logic voltage of the compensation polarity control signal, including a source electrode connected to the first node, a drain electrode connected to the output node, and a gate electrode to which a compensation polarity control signal is supplied. P-type MOS-FET output through the output node; And The low potential voltage in response to the high logic voltage of the compensation polarity control signal, including a source electrode connected to the second node, a drain electrode connected to the output node, and a gate electrode to which the compensation polarity control signal is supplied. And an n-type MOS-FET for outputting through the output node. The method of claim 6, And the low potential voltage is a voltage of 1 to 2 grays lower than that of the high potential voltage. The method of claim 3, wherein The second voltage divider resistance circuit, A third node for outputting a low potential voltage, And a fourth node for outputting a high potential voltage. The method of claim 8, And a switch circuit for selecting one of the low potential voltage and the high potential voltage as the analog gamma compensation voltage in response to the compensation polarity control signal, and supplying the selected voltage to the data driving circuit through an output node. A liquid crystal display device. The method of claim 9, The switch circuit, The low potential voltage in response to a low logic voltage of the compensation polarity control signal, including a source electrode connected to the third node, a drain electrode connected to the output node, and a gate electrode to which a compensation polarity control signal is supplied. P-type MOS-FET output through the output node; And The high potential voltage in response to the high logic voltage of the compensation polarity control signal, including a source electrode connected to the fourth node, a drain electrode connected to the output node, and a gate electrode to which the compensation polarity control signal is supplied. And an n-type MOS-FET for outputting through the output node. The method of claim 9, And the high potential voltage is a voltage of 1 to 2 grays lower than that of the low potential voltage. The method of claim 1, The polarity control signal, 2 Logical value is reversed in units of horizontal period, The compensation polarity control signal, 1. A liquid crystal display according to claim 1, wherein a logic value is inverted in units of horizontal periods. The method of claim 11, And the logic value of the compensation polarity control signal is inverted when the logic value of the polarity control signal is inverted and inverted within a period in which the logic value of the polarity control signal is maintained. A driving method of a liquid crystal display device comprising a liquid crystal panel in which data lines and gate lines intersect and liquid crystal cells are arranged in a matrix form. Generating a polarity control signal instructing polarity inversion of the data voltage in units of N (N is a positive integer of 2 or more) horizontal period; Generating a compensation polarity control signal having a shorter period than the polarity control signal; Generating an analog gamma compensation voltage corresponding to the gray levels represented in the liquid crystal panel; Adjusting the analog gamma compensation voltage in response to the compensation polarity control signal; Converting digital video data into the analog gamma compensation voltage in response to the polarity control signal to generate an analog data voltage; And And supplying the analog data voltage to the data lines. The method of claim 14, Adjusting the analog gamma compensation voltage, And in response to the compensation polarity control signal, lower the voltages of the analog gamma compensation voltages to voltages of 1 to 2 gradations represented by the liquid crystal panel. The method of claim 14, The polarity control signal, 2 Logical value is reversed in units of horizontal period, The compensation polarity control signal, 1. A driving method of a liquid crystal display device according to claim 1, wherein a logic value is inverted in units of horizontal periods. The method of claim 16, And the logic value of the compensation polarity control signal is inverted when the logic value of the polarity control signal is inverted and inverted within a period in which the logic value of the polarity control signal is maintained.

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