KR20080039070A - Method for manufacturing a flash memory device - Google Patents

Abstract

A method of manufacturing a flash memory device is provided to prevent the degradation of cycling property by securing uniform separation distance between a substrate of an active region and a control gate. A floating gate which is separated electrically by a device isolation layer(36B) is formed. The device isolation layer is recessed to expose a part of the both sidewalls of the floating gate. An etch stop barrier layer(37A) is formed at the both side walls of the exposed floating gate. The device isolation layer is recessed by performing wet-etching using the etch stop barrier layer. The etch stop barrier is removed. A dielectric layer is formed along a step of the upper surface of the resultant structure. A control gate is formed on the dielectric layer.

Description

Flash memory device manufacturing method {METHOD FOR MANUFACTURING A FLASH MEMORY DEVICE}

1A to 1C are cross-sectional views illustrating a method of fabricating a flash memory device using a general ASA-STI scheme.

FIG. 2 is a scanning electron microscope (SEM) photograph showing a flash memory device formed by applying a general ASA-STI scheme as shown in FIGS. 1A to 1C.

3A to 3E are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

30 substrate 31 gate insulating film

32: floating gate 33: pad nitride film

34: wall oxide film 35: device isolation film

36, 36A, 36B, 36C: device isolation film

37, 37A: etching barrier layer 38: etch back process

39: wet etching process 40: groove

41 dielectric film 42 control gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory device manufacturing technology, and more particularly to a non-volatile memory device, specifically a flash memory device manufacturing method.

Recently, the demand for flash memory devices that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals is increasing. In order to develop a large-capacity memory device capable of storing a large amount of data, researches on a high integration technology of the memory device have been actively conducted. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of removing data written to the memory cell.

Recently, as the integration of devices has increased, design rules of such flash memory devices have decreased, resulting in a decrease in program speed and increased cell interference. . In particular, the cell interference characteristic is an important factor that determines the characteristics of the device in MLC (Multi Level Cell) rather than SLC (Single Level Cell). There is a need to be achieved.

On the other hand, with the reduction of design rules of flash memory devices, a new STI (Shallow Trench Isolation) scheme is proposed for the isolation of various devices. Recently, ASA- is a suitable STI scheme for MLC devices of 60nm or less. Advanced Self Aligned Shallow Trench Isolation (STI) is in the spotlight. The ASA-STI scheme has been applied to forming floating gates of flash memory devices in accordance with a reduction in the overlay margin between the active region and the floating gate. Hereinafter, a general ASA-STI scheme will be described with reference to FIGS. 1A to 1C.

First, as shown in FIG. 1A, the tunnel oxide film 11, the floating silicon polysilicon film 12, and the pad nitride film 13 are sequentially formed on the semiconductor substrate 10.

Subsequently, the pad nitride film 13, the polysilicon film 12, the tunnel oxide film 11, and the substrate 10 are etched to form trenches having a predetermined depth.

Subsequently, a wall oxidation process is performed to form a wall oxide film 14 along the inner surface of the trench, and then an insulating film 15 for device isolation is deposited to fill the trench. Thereafter, a chemical mechanical polishing (CMP) process is performed. As a result, the device isolation film 16 filling the trench is formed.

Subsequently, as shown in FIG. 1B, the pad nitride film 13 is removed. In this case, the device isolation layer 16 may also have a predetermined thickness removed.

Subsequently, the device isolation layer 16A in the cell region is recessed to a predetermined depth using a Periphery Closed Layer (PCL) mask (not shown). At this time, the effective height of the recessed device isolation layer 16A becomes 'EFH'. In general, EFH is an abbreviation of Effective Field oxide Height and refers to the height of the device isolation layer 16A protruding above the substrate 10 of the active region.

Thereafter, a stripping process is performed to remove the PCL mask.

Subsequently, as shown in FIG. 1C, the dielectric film 17 is formed along the entire top surface step formed by the recessed device isolation film 16A. Then, the control gate 18 is formed on the dielectric film 17.

FIG. 2 is a scanning electron microscope (SEM) photograph of a flash memory device formed by applying a general ASA-STI scheme as shown in FIGS. 1A to 1C. Hereinafter, a problem with the ASA-STI scheme will be described with reference to FIG. 2.

In general, when the ASA-STI scheme is applied, the EFH change is severe, and the region where the EFH is highly adjusted causes an increase in adjacent cell to cell interference due to an increase in capacitance. Therefore, when the EFH is reduced to improve such interference characteristics, the separation distance D1 between the active substrate substrate 10 and the control gate CG is further reduced, thereby reducing the substrate 10 and the control gate CG. The leakage current of the device causes a problem that the cycling characteristics of the device (repeated program and erase operation characteristics) are deteriorated.

Accordingly, an object of the present invention is to provide a method for manufacturing a flash memory device capable of minimizing interference between neighboring cells, which has been devised to solve the above problems of the prior art.

Another object of the present invention is to provide a method of manufacturing a flash memory device capable of preventing a deterioration of cycling characteristics by securing a predetermined distance between a substrate and a control gate in an active region.

According to an aspect of the present invention, there is provided a method of forming a floating gate electrically separated by a device isolation film, recessing the device isolation film to partially expose both sidewalls of the floating gate; Forming an etch barrier layer on both exposed walls of the floating gate, wet etching the device isolation layer using the etch barrier layer, removing the etch barrier layer, and removing the etch barrier layer; A method of manufacturing a flash memory device, the method comprising: forming a dielectric film along a step top surface of a resultant layer from which a layer is removed, and forming a control gate on the dielectric film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and if a layer is said to be "on" another layer or substrate it may be formed directly on another layer or substrate. Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

3A to 3E are cross-sectional views illustrating a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 3A, the gate insulating layer 31, the floating gate 32, and the pad nitride layer 33 are sequentially formed on the semiconductor substrate 30. Here, the gate insulating layer 31 functions as a tunnel oxide layer of a general flash memory device and may be formed of an oxide layer material including an oxide layer or a nitride layer. In addition, a buffer oxide layer (not shown) may be further formed between the floating gate 32 and the pad nitride layer 33 to reduce the stress applied to the floating gate 32 when the pad nitride layer 33 is formed. .

Subsequently, the pad nitride layer 33, the floating gate 32, the gate insulating layer 31, and the substrate 30 are etched to form trenches (not shown) having a predetermined depth.

Subsequently, a monthly oxidation process is performed to compensate for damage to the trench inner wall and the bottom surface during the STI etching process, to round the upper edge portion, and to reduce the critical dimension of the active region. As a result, a wall oxide film 34 is formed along the inner surface of the trench.

Subsequently, an insulating film 35 for device isolation is deposited to fill the trench. In this case, the device isolation insulating layer 35 is an oxide film (hereinafter referred to as an HDP oxide film) deposited by a high density plasma (CVD) chemical vapor deposition (CVD) method having excellent buried characteristics so that voids do not occur in the trench. It is preferable to form into). Thereafter, a CMP process is performed to form an isolation layer 36 filling the trench.

Subsequently, as illustrated in FIG. 3B, the pad nitride layer 33 is removed by performing a wet etching process. In this case, the device isolation layer 36 may also have a predetermined thickness removed.

Subsequently, the device isolation layer 36A in the cell region is recessed by a predetermined depth using a PCL mask (not shown). At this time, the effective height of the recessed device isolation layer 36A becomes 'EFH'.

Subsequently, an etching barrier layer 37 having a predetermined thickness is deposited along the stepped top surface of the floating gate 31 including the recessed device isolation layer 36A. At this time, an amorphous carbon layer is deposited as the etch barrier layer 37.

Next, as shown in FIG. 3C, an etch back process 38 is performed to etch the etch barrier layer 37. As a result, a spacer-type etching barrier layer 37A is formed on both sidewalls of the floating gate 32 exposed on the device isolation layer 36A. For example, the etchback process 38 applies a pressure of 3 to 5 Torr and proceeds at a temperature of about 250 to 350 ° C., but uses a C ₃ H ₆ / H ₂ mixed gas.

Next, as shown in FIG. 3D, a wet etching process 39 using the etching barrier layer 37A is performed. In the wet etching process 39, BOE (Buffered Oxide Etchant, a solution in which HF and NH ₄ F are mixed at 100: 1 or 300: 1) or HF is used as an etching solution. As a result, the groove 40 is formed in the bottom of the etching barrier layer 37A, and the device isolation layer 36B is recessed to a predetermined width and depth. At this time, the etching in the lateral direction is faster than the etching in the depth direction due to the etching characteristics of the wet etching process 39.

Subsequently, as shown in FIG. 3E, an etching process is performed to remove the etching barrier layer 37A. Here, the etching process may be performed by a dry method such as a strip process for removing the photoresist, or by a wet method.

For example, when the process is performed in a wet manner, the H ₂ SO ₄ / H ₂ O ₂ mixed solution may be used separately, or the same may be performed in the same etching equipment as the wet etching process 39 for recessing the device isolation layer 36B. At this time, when using the H ₂ SO ₄ / H ₂ O ₂ mixed solution, the amorphous carbon film is etched at an etching rate of 13.9 kW / min. Meanwhile, in order to proceed in the same etching equipment as the wet etching process 39 for recessing the device isolation layer 36B, the BOE or HF solution used during the wet etching process 39 is used as it is or after the use thereof, H ₂ SO ₄ / H ₂ O ₂ mixed solution can be used sequentially. At this time, the mixing ratio of the H ₂ SO ₄ / H ₂ O ₂ mixed solution is preferably set to H ₂ SO ₄ : H ₂ O ₂ = 4: 1.

When the etching barrier layer 37A is removed, there is no plasma attack applied to the substrate 30 and the device isolation film 36B EFH on both sides of the floating gate 32 remains unchanged. In addition, since the device isolation layer 36B having a predetermined thickness remains on both sides of the floating gate 32, the gap between the substrate 30 in the active region and the control gate 42 to be formed through a subsequent process may be kept constant. Therefore, deterioration of the cycling characteristics of an element can be prevented.

Next, a pre-cleaning step is performed. In this case, when the etching process for removing the etching barrier layer 37A is performed in a dry manner, the pre-cleaning process may be performed separately, and when the wet barrier layer is wet, the separate pre-cleaning process may not be performed. In this pre-cleaning process, the device isolation layer 36B may be further recessed to a predetermined depth. At this time, the reason for further recessing the device isolation film 36B is to increase the contact ratio of the dielectric film 41 to be subsequently formed to maximize the coupling ratio. Therefore, the program operation speed can be increased.

Subsequently, the dielectric film 41 is formed along the level difference of the upper surface of the floating gate 32 including the device isolation film 36B, and the control gate 42 is formed on the dielectric film 41. At this time, the dielectric film 41 is preferably formed in an oxide film / nitride film / oxide film (ONO) structure.

As described above, according to the exemplary embodiment of the present invention, as the insulating film for separating the adjacent floating gates 32 from each other, not only the device isolation film 36B but also the dielectric film 41 made of a material different from the device isolation film 36B is provided. As such, interference between neighboring cells can be minimized.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, there are various effects as follows.

First, after the device isolation film is recessed to a predetermined depth so that a part of both sides of the floating gate electrically separated from each other by the device isolation film is formed, an etch barrier layer is formed on both side walls of the floating gate, and the device isolation film is recessed again. It is possible to increase the program area of the device by increasing the contact area of the subsequently deposited dielectric film while suppressing the change in the effective height of the device isolation film on both sides of the floating gate.

Second, by recessing the device isolation layer through the etch barrier layer formed on both side walls of the floating gate as described above, the device isolation layer having a predetermined thickness remains on both sides of the floating gate even after the device isolation layer recess, so that the substrate and the control gate in the active region The distance can be kept constant to some extent, thereby improving the cycling characteristics of the device.

Third, interference between neighboring cells can be reduced by allowing the isolation layer and the dielectric layer, which is a heterogeneous layer, to exist in the recessed isolation layer.

Claims (11)

Forming a floating gate electrically separated by an isolation layer; Recessing the device isolation layer to partially expose both sidewalls of the floating gate; Forming an etch barrier layer on both exposed walls of the floating gate; Recessing the device isolation layer in a wet manner using the etch barrier layer; Removing the etch barrier layer; Forming a dielectric film along a top surface of a resultant surface from which the etch barrier layer is removed; And Forming a control gate on the dielectric layer Flash memory device manufacturing method comprising a. The method of claim 1, After removing the etch barrier layer, A flash memory device manufacturing method further comprising the step of performing a cleaning process. The method of claim 2, And a portion of the device isolation layer is etched during the cleaning process. The method according to any one of claims 1 to 3, Forming the floating gate, Sequentially forming a gate insulating film, a floating gate conductive film, and a pad nitride film on the substrate; Etching the pad nitride film, the conductive film, the gate insulating film, and the substrate to form a trench; Forming an isolation layer embedded in the trench; And Removing the pad nitride film Flash memory device manufacturing method comprising a. The method according to any one of claims 1 to 3, Recessing the device isolation film, Forming a mask having a structure of opening a cell region in which a cell of the semiconductor device is formed; And Selectively etching the device isolation layer of the cell region through the mask Flash memory device manufacturing method comprising a. The method according to any one of claims 1 to 3, Forming an etch barrier layer on both side walls of the floating gate, Depositing the etch barrier layer on the entire structure where both sidewalls of the floating gate are exposed; And Performing an etch back process to etch the etch barrier layer Flash memory device manufacturing method comprising a. The method according to any one of claims 1 to 3, Recessing the device isolation layer in the wet manner, The method of claim 1, wherein the device isolation layer has a predetermined thickness on both sides of the floating gate. The method according to any one of claims 1 to 3, The device isolation film is a high-density plasma oxide film (HDP oxide film) to form a flash memory device manufacturing method. The method of claim 8, And the etching barrier layer is formed of an amorphous carbon film. The method of claim 9, Removing the etch barrier layer, A flash memory device manufacturing method comprising a dry or wet etching process. The method of claim 10, In the wet etching process, a mixture of H ₂ SO ₄ / H ₂ O ₂ is used, BOE (Buffered Oxide Etchant) or HF is used, or BOE or HF is used, followed by H ₂ SO ₄ / H ₂ O ₂ mixed solution. Method for manufacturing a flash memory device used as a.

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