KR20080038894A - Structure and method for manufacturing semiconductor memory device - Google Patents

Abstract

A method of manufacturing a semiconductor memory device, and a structure thereof are provided to relieve concentration effect of electric field by forming an edge of an active region as a gentle curve, and to expand the width of a channel extraordinarily without increasing the design rule by realizing the active region of 3D embossing shape. A pad insulating layer is formed on a semiconductor substrate(100). The pad insulating layer is etched selectively to expose the semiconductor substrate. An LOCOS oxide layer is formed on the substrate by performing an oxidation process to the substrate. A trench is formed by etching the semiconductor substrate under the LOCOS oxide layer and the LOCOS oxide layer by performing an anisotropic etching process. An insulating layer(112) is deposited on the entire surface of the semiconductor substrate on which the insulating layer is deposited. The substrate is flattened to expose the pad insulating layer. The exposed pad insulating layer is removed. A trench device isolation layer and an active region of the domed shape are formed by leaving the insulating layer of a specified thickness within the trench by etching bird's beak of the LOCOS oxide layer and the insulating layer deposited in the trench. A tunnel oxide layer(114) and a poly-silicon layer(116) are deposited sequentially on the resultant structure. And a gate electrode is formed by removing the tunnel oxide layer and the polysilicon layer.

Description

Method for manufacturing semiconductor memory device and its structure

1 shows a cross-sectional structure of a semiconductor memory device according to the prior art.

2A to 2J illustrate a channel width expansion method of a semiconductor memory device according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100 semiconductor substrate 102 pad insulating film

104: mask pattern 108: LOCOS oxide film

110: trench 112: insulating film

114: tunnel oxide film 116: polysilicon film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a structure of a semiconductor memory device, and more particularly, to a method and a structure of a semiconductor memory device capable of further expanding a channel width.

Semiconductor memory devices used to store data may be generally classified into volatile memory devices and nonvolatile memory devices. In such a semiconductor memory device, first, a volatile memory device represented by DRAM (Dynamic Random Access Memory) or SRAM (Static Rrandom Access Memory) has a drawback in that data input / output operation is fast but data is lost when power supply is interrupted. There is this. On the other hand, nonvolatile memory devices represented by EPROM (Erasable Programmable Read Only Memory) or EEPROM (Electrically Erasable Programmable Read Only Memory), etc., have slower input / output operations than the volatile memory devices, but stored data even when power supply is interrupted. Has the advantage of being kept intact. Therefore, such a nonvolatile memory device can be widely used in areas where power is not always supplied or power supply is intermittently interrupted, such as a memory card or a mobile communication system for storing music or image data.

Among these non-volatile memory devices, in particular, the flash memory device adopting the 1 Tr / 1 Cell structure of the batch erasing method to overcome the limitation of the integration density of EEPROM can freely input / output data electrically and consumes less power. The high-speed programming is expected to replace the hard disk drive (HDD) of the computer in the future, the demand is gradually increasing. Such a flash memory device is a NOR flash memory in which two or more cell transistors are connected in parallel on one bit line, and a NAND in which two or more cell transistors are connected in series on one bit line. It can be divided into flash memory. However, these flash memory devices have the advantage of overcoming vulnerabilities that their operation speed is slower than volatile memory devices, despite the excellent advantage that the stored data is preserved even in the event of a power failure. Various cell structures and driving methods for increasing the speed have been actively studied.

In addition, in this field, as the size of each unit device constituting the memory cell is reduced due to the trend of high integration and large capacity of semiconductor memory devices, high integration technology for forming a multilayer structure within a limited area has also been remarkably developed. As part of the multilayer gate structure is widely adopted. The stacked gate structure has a structure in which a tunnel oxide film made of a silicon oxide film, a floating gate made of polysilicon, a gate interlayer dielectric film made of an oxide-nitride-oxide (ONO) film, and a control gate film made of polysilicon are sequentially stacked. .

In the stacked gate structure as described above, the floating gate has a structure in which the floating gate is electrically insulated from the outside and is isolated, and stores data by using a property in which a current of the memory cell changes according to electron injection and emission into the floating gate. Done. The electron injection (programming) to the floating gate is performed by FN tunneling (Fowler Nordheim tunneling) through the inter-gate dielectric film existing between the floating gate and the control gate or channel hot electron injection (CHEI) using high temperature electrons in the channel. . In addition, electron emission (erasure) injected into the floating gate is performed through F-N (Fowler-Nordheim) tunneling through an inter-gate dielectric layer existing between the floating gate and the control gate. In this case, the F-N tunneling is generated by applying an electric field of 6 to 8 MV / cm to the tunnel oxide film interposed between the floating gate and the semiconductor substrate. The electric field between the floating gate and the semiconductor substrate is induced by applying a high voltage of 15 to 20 V to the control gate located above the floating gate.

On the other hand, in the semiconductor memory device including the flash memory device as described above and conventional DRAM and SRAM device, the characteristics of the transistor are determined by various factors such as the width of the channel region, the gate oxide film, and the gate polysilicon. In particular, the current / voltage characteristics of the transistor are determined by the line width and length of the channel region, the line width and length of the gate polysilicon, the thickness of the gate oxide film, and the material characteristics of the gate oxide film.

Therefore, in the present field, the electrical characteristics of the transistor have been improved in pursuit of facility and process improvement along with a method of minimizing the pattern size, changing the material of the gate oxide film, and changing the thickness of the gate oxide film. As a result, it is possible to form a pattern up to 0.09 μm in recent years, and as such a fine size pattern can be formed, it is possible to store a lot of information per unit area by increasing the density of the circuit. In addition, in terms of design, the gate polysilicon pattern is formed to be inclined to increase the gate width per unit area, and is applied to a region having a large current flow.

Figure 1 shows a cross-sectional structure of a semiconductor memory device according to the prior art.

Referring to FIG. 1, an isolation layer 12 having an STI structure is formed on a semiconductor substrate 10 made of conventional doped silicon. A tunnel oxide film 14 and a gate polysilicon film 16 functioning as a gate electrode are deposited on the semiconductor substrate 10 on which the device isolation film 12 is formed. Here, the tunnel oxide film 14 may be deposited, for example, using a silicon oxide film (SiO ₂ ) at a thickness of about 100 to 200 mW, more specifically, 150 mW. The region indicated by reference numeral A becomes an active region, that is, a channel region, in which electrons moved when conducting current flow.

As shown in FIG. 1, in the related art, the channel region is flat in the semiconductor memory device. The device isolation region is a LOCOS for growing an oxide having a predetermined thickness below and above the semiconductor substrate, or as shown in FIG. 1, after forming a trench having a predetermined depth in the semiconductor substrate, and filling an insulating film in the trench. Method was used.

Since the channel region is flat, the area in which current flows is limited only to the region in which the gate electrode exerts an electric field in the channel region. Therefore, when the channel region A is formed flat as shown in FIG. 1, an area through which current flows is limited to the channel region A. FIG. In addition, scum-like bridges between gate polysilicon that function as gate electrodes are induced, which greatly reduces the electrical characteristics of the semiconductor memory device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method and a structure for fabricating a semiconductor memory device that can extend a channel region through which current flows.

Another object of the present invention is to provide a manufacturing method and a structure of a semiconductor memory device that can further improve the electrical characteristics of the semiconductor memory device.

Another object of the present invention is to provide a method and a structure for fabricating a semiconductor memory device that can solve the problem of causing inter-silicon scum bridges to function as gate electrodes.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, the method including: forming a pad insulating film on a semiconductor substrate; Selectively etching the pad insulating film to expose the semiconductor substrate; Performing an oxidation process on the semiconductor substrate to form a LOCOS oxide film on the semiconductor substrate exposed by the pad insulating film; Forming a trench by performing an anisotropic etching process on a region where the LOCOS oxide film is formed to etch a predetermined thickness of the LOCOS oxide film and the semiconductor substrate under the LOCOS oxide film; Depositing an insulating film on an upper surface of the semiconductor substrate on which the trench is formed; Performing a front planarization process on the semiconductor substrate on which the insulating film is deposited until the pad insulating film is exposed; Removing the exposed pad insulating film; The trench isolation layer and the hemispherical active region are formed by performing an etching process on the buzz beak of the LOCOS oxide film remaining on the sidewalls of the trench and the insulating film deposited in the trench to leave an insulating film having a predetermined thickness inside the trench. Forming; And depositing a tunnel oxide film and a polysilicon film on the front surface of the resultant in turn, and then forming a gate electrode by removing the tunnel oxide film and the polysilicon film on the trench isolation layer.

In addition, a semiconductor memory device according to the present invention for achieving the above objects, a plurality of trench isolation layer formed in a predetermined depth of the semiconductor substrate; A hemispherical active region formed between the plurality of trench isolation layers and having a curved edge; And a gate electrode formed of an insulating film and a conductive film formed on the active region.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention. The present invention is not limited to the embodiments disclosed below, but can be embodied in various other forms without departing from the scope of the present invention, and only the embodiments allow the disclosure of the present invention to be complete and common knowledge It is provided to fully inform the person of the scope of the invention.

2A to 2J illustrate a channel width expansion method of a semiconductor memory device according to an exemplary embodiment of the present invention.

First, referring to FIG. 2A, for example, a pad insulating layer 102 is formed on an upper portion of a P-type semiconductor substrate 100 doped with impurities contained in Group 3B (Boron). Here, the pad insulating film 102 may be formed of a silicon nitride film (SiN). Thereafter, after spin coating the photoresist film on the pad insulating film 102, the photoresist film is etched with the mask pattern 104 by performing a normal photolithography process.

Referring to FIG. 2B, the pad insulating layer 102 is anisotropically etched using the mask pattern 104 as an etching mask. As a result of the anisotropic etching, the region 106 on which the device isolation layer is to be formed is defined on the semiconductor substrate 100. The mask pattern 104 is then removed from conventional ashing and stripping processes.

Referring to FIG. 2C, a normal oxidation process is performed on the semiconductor substrate 100. As a result, a local oxidation of silicon (LOCOS) oxide film 108 is formed in the region 106 where the device isolation film is to be formed, in which the pad insulating film 102 is removed to expose the semiconductor substrate 100.

Referring to FIG. 2D, an anisotropic etching process is performed on the semiconductor substrate 100 on which the LOCOS oxide layer 108 is formed. As a result, the LOCOS oxide layer 108 and the semiconductor substrate 100 below it are etched to a predetermined depth to form the trench 110. In this case, a bird's beak 108 formed on the sidewall of the trench 110 is formed while the oxide film is grown between the pad insulating film 102 and the semiconductor substrate 100 in the process of forming the LOCOS oxide film 108. It exists. The buzz beak 108 serves to mitigate the concentration of the electric field in the channel region formed according to the embodiment of the present invention. It is explained in detail.

Referring to FIG. 2E, an insulating layer 112 is deposited on the semiconductor substrate 100 on which the trench 110 is formed. In this case, the insulating layer 112 may be a silicon oxide layer (SiO ₂ ).

Referring to FIG. 2F, the entire surface planarization process is performed on the semiconductor substrate 100 on which the insulating film 112 is deposited until the pad insulating film 102 is exposed. Here, as the front planarization process, a CMP process or a blanket etching process may be used.

Referring to FIG. 2G, the pad insulating layer 102 exposed by the front planarization process is removed by wet etching. Accordingly, the insulating layer 112 is exposed in the form of embossing on the semiconductor substrate 100.

Referring to FIG. 2H, a wet etching process is performed on the semiconductor substrate 100 from which the pad insulating film 102 is removed to etch the insulating film 112 embedded in the trench 110 to a predetermined thickness. In this case, as an etchant for wet etching the insulating layer 112, a chemical such as LAL or BOE may be used. At this time, the component of the buzz beak 108 is also the same silicon oxide film as the insulating film 112. Thus, the buzz beak 108 is also removed during the wet etching process.

As shown in FIG. 2H, the buzz beak 108 is removed, so that the semiconductor substrate 100 in which the buzz beak 108 was present has a gentle curve as indicated by the reference numeral B. The region of the semiconductor substrate 100 having the gentle curve B is a region where a channel of the semiconductor memory device according to the present invention is to be formed. As indicated by the reference B, when the edge of the channel region is formed in a gentle curve under the influence of the buzz beak, concentration of the electric field does not occur when conducting current to the channel region. As a result, the electrical characteristics of the semiconductor memory device may be more excellent than in the case where the corners of the channel region have a sharp right angle.

Referring to FIG. 2I, a tunnel oxide layer 114 is deposited on an upper surface of a semiconductor substrate 100 in which an insulating layer 112 exists only in a portion of the trench 110. In this case, the tunnel oxide film 114 may be deposited to, for example, about 100 to about 200 mW, more specifically, about 150 mW using a silicon oxide film (SiO ₂ ). Subsequently, a polysilicon film 116 doped with impurities contained in a group 5B (eg, P or As) is deposited on the tunnel oxide film 114. At this time, the polysilicon film 116 is preferably deposited to about 600 ~ 1000 600, more specifically 800 보다 m thick.

Referring to FIG. 2J, the polysilicon film 116 and the tunnel oxide film 114 are patterned by performing a conventional photolithography process to form a gate electrode of a semiconductor memory device.

In the semiconductor memory device shown in FIG. 2J, the region denoted by reference numeral C is an active region, ie, a channel region, in which electrons moved when current is conducted. The active region (refer to FIG. 1) of the semiconductor memory device according to the related art has a flat straight line as indicated by reference numeral A. However, the active region of the semiconductor memory device implemented according to the embodiment of the present invention has a hemispherical shape (C) that extends to both sidewalls obtained by forming the trench 110 and to the upper portion of the semiconductor substrate. It can be seen that the length of the semiconductor memory device is much larger than that of the active region. As such, when the active region is expanded, the width of the gate electrode formed on the active region is also expanded, and thus, the width of the channel through which the electrons are moved during the conduction of the current is expanded, resulting in an increase in the electrical characteristics of the semiconductor memory device. There is an effect to be improved.

When the semiconductor memory device is implemented as illustrated in FIGS. 2A to 2J, the edges of the active regions are formed to have gentle curves, thereby reducing the electric field concentration effect. In addition, since the area of the active region is widened, the width of the channel is greatly expanded, and the gate electrode is formed on the active region that has risen compared to the other regions, the inter-silicon scum bridge which functions as the gate electrode is caused. As a result, the electrical characteristics of the semiconductor memory device can be further improved. In forming the active region, by realizing the area in three dimensions rather than in the horizontal length, it is possible to substantially increase the area of the active region while faithfully following the design rules. That is, since it is possible to secure a wider channel width than the same area, there is an advantage that can be advantageously applied to the high integration device.

As described above, in implementing the semiconductor memory device, the electric field concentration effect is alleviated by forming the edge of the active region in a smooth curve. In addition, by embodying the active region in a three-dimensionally raised embossed shape, the width of the channel is greatly expanded without increasing the design rule, thereby improving the electrical characteristics of the semiconductor memory device.

Claims (14)

Manufacturing Method of Semiconductor Memory Device: Forming a pad insulating film on the semiconductor substrate; Selectively etching the pad insulating film to expose the semiconductor substrate; Performing an oxidation process on the semiconductor substrate to form a LOCOS oxide film on the semiconductor substrate exposed by the pad insulating film; Forming a trench by performing an anisotropic etching process on a region where the LOCOS oxide film is formed to etch a predetermined thickness of the LOCOS oxide film and the semiconductor substrate under the LOCOS oxide film; Depositing an insulating film on an upper surface of the semiconductor substrate on which the trench is formed; Performing a planarization process on the entire surface of the semiconductor substrate on which the insulating film is deposited until the pad insulating film is exposed; Removing the exposed pad insulating film; The trench isolation layer and the hemispherical active region are formed by performing an etching process on the buzz beak of the LOCOS oxide film remaining on the sidewalls of the trench and the insulating film deposited in the trench to leave an insulating film having a predetermined thickness inside the trench. Forming; And depositing a tunnel oxide film and a polysilicon film on the front surface of the resultant in turn, and then forming a gate electrode by removing the tunnel oxide film and the polysilicon film on the trench isolation layer. . The method of claim 1, wherein the pad insulating layer is formed of a silicon nitride layer (SiN). The method of claim 2, wherein the insulating film deposited in the trench is a silicon oxide film. The method of claim 3, wherein the front planarization process is a CMP or blanket etching process. The method of claim 4, wherein the insulating film in the buzz beak and the trench is wet etched by a chemical such as LAL or BOE. 6. The method of claim 5, wherein the tunnel oxide film is formed of a silicon oxide film. 7. The method of claim 6, wherein the tunnel oxide film is deposited to a thickness of 100 to 200 mV, more specifically 150 mV. 8. The method of claim 7, wherein the polysilicon film is deposited to a thickness of 600 to 1000 mW, more specifically 800 mW. In a semiconductor memory device: A plurality of trench isolation layers formed at a predetermined depth of the semiconductor substrate; A hemispherical active region formed between the plurality of trench isolation layers and having a curved edge; And And a gate electrode formed of an insulating film and a conductive film formed over the active region. The semiconductor memory device of claim 9, wherein the trench isolation layer is a silicon oxide layer. The semiconductor memory device according to claim 10, wherein said insulating film is a tunnel oxide film, and is formed of a silicon oxide film. 12. The semiconductor memory device according to claim 11, wherein the insulating film is deposited to a thickness of 100 to 200 mW, more specifically to 150 mW. 13. The semiconductor memory device of claim 12, wherein the conductive film is formed of a polysilicon film. The semiconductor memory device as claimed in claim 13, wherein the conductive film is deposited at a thickness of 600 to 1000 kW, more specifically 800 kW.

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