KR20080029566A - Method for manufacturing flash memory device - Google Patents

Abstract

A method for manufacturing a flash memory device is provided to improve interference characteristics by forming automatically a sidewall protection layer on both sidewalls of a polysilicon layer for floating gate. A substrate including a stacked structure of a tunnel oxide layer, a conductive layer for floating gate, and a pad nitride layer is provided. A trench is formed by etching the pad nitride layer, the conductive layer, the tunnel oxide layer, and a part of the substrate. An isolation oxide layer is deposited on the entire structure to bury a part of the trench(S20,S21). A spin-on dielectric is formed on the oxide layer to bury fully the trench(S22). The spin-on dielectric is planarized to expose the pad nitride layer(S23). A thermal process for the spin-on dielectric is performed(S24). The pad nitride layer is removed to expose a part of the oxide layer(S25). The spin-on dielectric is etched by performing a dry-etch process.

Description

Flash memory device manufacturing method {METHOD FOR MANUFACTURING FLASH MEMORY DEVICE}

1 is a flowchart illustrating a method of manufacturing a flash memory device according to the related art.

2 is a flowchart for briefly explaining a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

3A to 3F are cross-sectional views illustrating a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

4A and 4B are transmission electron microscope (TEM) photographs showing a flash memory device formed according to an exemplary embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

30 substrate 31 tunnel oxide film

32: polysilicon film for floating gate

33: buffer oxide film 34: pad nitride film

35: monthly oxide film 36: liner HDP oxide film

37: HTO film 38, 38A: PSZ film

39, 39A, 39B: device isolation film 40: sidewall protection film

41: etch back process

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a method of manufacturing a flash memory device using the SA-STI process.

With the development of memory processing technology, the line width of flash memory devices has gradually decreased. As a result, the field region line width between the active regions is reduced, and as a result, the aspect ratio of the trenches formed in the field region is increased, which makes it difficult to fill the device isolation film. Therefore, PSZ, which is a type of spin on dielectric (SOD) film deposited by spin coating instead of HDP (High Density Plasma) USG (Undoped Silicate Glass) used to improve the buried characteristics of the device isolation film, A technique for embedding trenches using (PolySilaZane) has been proposed. However, PSZ has a material property that the wet etch rate is fast and uneven, so that the effective field oxide height (EFH) of the device isolation layer is uneven when the wet etch process is applied.

As a result, recently, in order to solve this problem, a technique of first forming a PSZ film filling a trench when forming an isolation layer, and then recessing a predetermined depth and depositing HDP on the upper portion thereof has been proposed. This is also applied to the Self Align-Shallow Trench Isolation (SA-STI) process as it is. Hereinafter, a description will be given of a flash memory device manufacturing method according to the prior art applying the SA-STI process as described above with reference to FIG. 1 is a flowchart illustrating a method of manufacturing a flash memory device according to the related art.

As shown in FIG. 1, first, a trench is formed in a substrate in which a tunnel oxide film, a floating gate polysilicon film, and a pad nitride film are sequentially stacked, and a monthly oxide film is formed along the inner surface of the trench (S10).

Subsequently, a liner high density plasma (HDP) oxide film (hereinafter referred to as HDP oxide film) having a predetermined thickness is deposited on the upper surface of the entire structure to fill a portion of the trench (S11). .

Subsequently, a PSZ film, which is a kind of SOD film, is deposited on the liner HDP oxide film so as to completely fill the trench (S12). At this time, the PSZ film is deposited by coating the PSZ film using a spin coating method and then curing the PSZ film.

Subsequently, chemical mechanical polishing (CMP) is performed to planarize the PSZ film (S13). Thereafter, the PSZ film is recessed to a predetermined depth through a wet etching process to expose the upper portion of the trench (S14).

Subsequently, an ISO (ISOlation) HDP oxide film, which is an insulating film for isolation, is thickly deposited to a thickness of about 3500 kV so that the trench is completely filled (S15). Thereafter, after pre-cleaning, an annealing process is performed to densify the ISO HDP oxide film (S16).

Subsequently, another CMP process is performed to planarize the ISO HDP oxide film (S17). Subsequently, post-cleaning is performed (S18). Then, the pad nitride film is removed (S19). As a result, the liner HDP oxide film / PSZ film / ISO HDP oxide film are stacked in this order to complete the device isolation film having a structure protruding onto the substrate.

However, in the SA-STI process according to this technique, a total of two CMP processes are performed to planarize the PSZ film and the HDP film. As a result, the EFH difference between the center part and the edge part of the device isolation layer is increased. Causes the problem to increase. This leads to a greater variation in EFH during the subsequent removal process of the pad nitride film, resulting in difficulty in controlling the appropriate EFH. In addition, the CMP process for planarizing the PSZ film and the HDP film, respectively, has to be performed separately.

In addition, the current technology lacks an interference margin due to the increase in the degree of integration of flash memory devices. This lack of interference freedom is one of the main factors that degrade the characteristics of the flash memory device is a problem that must be solved.

Accordingly, the present invention has been made to solve the above problems, there are various objects as follows.

First, it is an object of the present invention to provide a method for manufacturing a flash memory device capable of easily adjusting the effective height of a device isolation layer when manufacturing a flash memory device.

Secondly, an object of the present invention is to provide a method for manufacturing a flash memory device, which can simplify the process steps when manufacturing a flash memory device.

Third, an object of the present invention is to provide a method of manufacturing a flash memory device capable of increasing interference freedom.

According to an aspect of the present invention, there is provided a substrate in which a tunnel oxide film, a floating gate conductive film, and a pad nitride film are sequentially stacked, and the pad nitride film, the conductive film, the tunnel oxide film, and the Etching a portion of the substrate to form a trench, depositing an isolation layer for forming an isolation layer on an upper surface of the entire structure such that a portion of the trench is embedded, and spin-on separation for forming the isolation layer on the oxide layer so that the trench is completely embedded Forming an insulating film (Spin On Dielectric), planarizing the spin-on insulating film to expose the pad nitride film, heat-treating the spin-on insulating film, and exposing a portion of the oxide film over the conductive film. Removing the pad nitride film and etching the spin-on insulating film by performing a dry etching process. Provides a method for manufacturing a flash memory device.

In the present invention, in order to improve the interference characteristics of the flash memory device, that is, increase the degree of freedom of interference, a sidewall protective film having a spacer wing shape is formed on both sidewalls of the conductive film for the floating gate.

In addition, in order to easily control the effective height of the device isolation layer, the effective height of the device isolation layer is controlled by performing dry etching (etch back) during the etching of the PSZ film constituting the device isolation layer. In particular, the planarization process for forming the isolation layer may be performed once, that is, only the PSZ layer is planarized, thereby minimizing the EFH variation of the isolation layer itself.

In addition, by depositing and then annealing the PSZ film on the liner HDP oxide film during the formation of the device isolation layer, various processes required for the deposition of the conventional ISO HDP oxide film may be omitted. This can lead to overall process simplification and cost reduction.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

First, a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention will be described with reference to FIG. 1 and FIG. 2. 2 is a flowchart for briefly explaining a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

1 and 2, according to the embodiment of the present invention, it can be seen that the process of about four steps can be omitted as compared with the conventional method. For example, conventionally, the process of forming a trench and removing the pad nitride film had to go through a total of nine steps, whereas in the embodiment of the present invention, the process of forming a trench and removing the pad nitride film has a total of five steps. Just go through. Therefore, according to the embodiment of the present invention, by omitting the four-step process as compared to the conventional, it is possible to simplify the overall process and thereby bring a cost reduction effect.

Hereinafter, a method of manufacturing a flash memory device according to an embodiment of the present invention will be described in detail with reference to the related art.

First, a trench is formed on a substrate in which a tunnel oxide film, a floating gate polysilicon film, and a pad nitride film are sequentially stacked in the same manner as before, and a monthly oxide film is formed along the inner surface of the trench (S20).

Subsequently, a liner high density plasma (HDP) oxide film (hereinafter referred to as HDP oxide film) and a high temperature oxide (HTO) film of a predetermined thickness are successively deposited on the upper surface of the entire structure so that a portion of the trench is embedded. (S21). That is, in the past, only the liner HDP oxide film was deposited. In the embodiment of the present invention, the HTO film as well as the HDP oxide film is continuously deposited. For example, a liner HDP oxide film is deposited to a thickness of about 1300 GPa, and then immediately HTO film is deposited to a thickness of about 80 GPa.

Subsequently, a PSZ film, which is a kind of SOD film, is deposited on the liner HDP oxide film so as to completely fill the trench (S22). At this time, the PSZ film is coated by using a spin coating method, and then deposited by curing it.

Subsequently, chemical mechanical polishing (CMP) is performed to planarize the PSZ film (S23).

Subsequently, unlike the conventional one, the PSZ film is immediately annealed (S24). As a result, the film quality of the PSZ film becomes dense. This is to minimize damage to the PSZ film from subsequent processes. For example, an annealing process is performed to secure an etching selectivity of the PSZ film for a subsequent process of forming a peripheral region closed layer (PCL) mask and etching back, pad nitride removal, or cleaning. In particular, this annealing process is preferably performed for about 60 minutes at a temperature of about 900 ℃ using N ₂ gas. Therefore, in the exemplary embodiment of the present invention, the ISO HDP oxide film, which is conventionally used as a device isolation film, is not required. Therefore, it is possible to omit various processes that have been progressed to form the ISO HDP oxide film. For example, the conventional PSZ wet etching step (S14), the ISO HDP oxide film deposition step (S15), the ISO HDP CMP step (S16) and the post-cleaning step (S18) can be omitted.

Subsequently, the pad nitride film is removed by performing a wet etching process immediately (S25). As a result, a device isolation film filling the trench in a lamination structure of the liner HDP oxide film / HTO film / PSZ film is completed.

Hereinafter, a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3A to 3F.

First, as shown in FIG. 3A, a tunnel oxide film 31, a floating silicon polysilicon film 32 (hereinafter referred to as a polysilicon film), a buffer oxide film 33, and a pad nitride film 34 are formed on a substrate 30. Form in turn.

Next, a hard mask pattern (not shown) is formed on the pad nitride film 34. For example, the hard mask pattern is formed of a silicon oxynitride film (SiON).

Subsequently, the pad nitride layer 34, the buffer oxide layer 33, the polysilicon layer 32, and the tunnel oxide layer 31 are etched through the hard mask pattern to expose a portion of the substrate 30. Thereafter, the exposed substrate 30 is etched to a certain depth to form a trench (not shown).

Subsequently, a wall oxidation process is performed to form a monthly oxide film 35 along the inner surface of the trench. For example, the monthly oxide film 35 is formed using a furnace or a radical oxidation method, but formed to a thickness of 30 to 80 kPa in a temperature range of 700 to 900 ° C. Preferably, the monthly oxide film 35 is formed to have a constant thickness of 30 kPa.

Thereafter, a wet etching process is performed to remove the hard mask pattern.

Then, as shown in FIG. 3B, a liner HDP oxide layer 36 is deposited on the top surface of the entire structure so that a portion of the trench is embedded. Here, the liner HDP oxide film 36 functions as a sidewall protective film for protecting both side walls of the polysilicon film 32. At this time, the liner HDP oxide layer 36 is deposited to a thickness of 1000 ~ 1300Å in total, which has a film quality characteristic that the deposition characteristic in the horizontal direction than the vertical direction is remarkably excellent, and has a thickness of 100Å in the sidewall portion of the trench At the bottom of, it has a significantly thicker thickness, for example 150-1000 mm 3. In addition, the hydrogen concentration of the liner HDP film 36 is preferably 100 sccm.

Subsequently, a high temperature oxide (HTO) film 37 is deposited along the upper surface of the liner HDP oxide film 36. Here, the HTO film 37 functions as another sidewall protective film for protecting the sidewall of the polysilicon film 32. The HTO film 19 is deposited to a thickness of 80 kHz using DCS (DiChloroSilane, SiH ₂ Cl ₂ ) as a source.

Subsequently, although not shown in the drawings, the FN and BON cleaning processes may be performed in advance to prevent coating defects during subsequent PSZ film deposition. For example, the FN cleaning process is performed for about 10 seconds and the BON cleaning process is performed for about 2 seconds. Here, the FN cleaning process is F washing using a first solution in which H ₂ O and hydrofluoric acid are mixed at a ratio of 50: 1, and NH ₄ OH, H ₂ O ₂ , and H ₂ O are mixed at a ratio of 1: 4: 20. say that to proceed with the cleaning using the N 2 a solution of 25 ℃ temperature in sequence, refers to a cleaning process using a mixture of BON cleaning is _{H 2 SO 4 + H 2 O} 2.

3C, a PSZ film 38 is formed on the HTO film 37 so that the trench is completely filled. The PSZ film 38 is a type of SOD (Spin On Dielectric) film formed by using a spin coating method, and is formed by sequentially performing a coating and curing process. For example, the coating is performed at a thickness of 5500 to 6000 mm, and curing is performed at a temperature of about 350 ° C. for 2 hours.

Subsequently, a back side strip process is performed. This proceeds to remove the nitride film material present at the back side.

3D, the PSZ film 38A is polished by performing a planarization process such as a chemical mechanical polishing (CMP) process. As a result, an isolation layer 39 is formed to completely fill the trench. At this time, the CMP process sets the thickness margin of the CMP stop target, that is, the remaining pad nitride film 34 to be Δ5 to 15 kPa. In addition, during the CMP process, it is preferable to sequentially use Low Selectivity Slurry (LSS) and High Selectivity Slurry (HSS).

Next, an annealing process is performed to densify the film quality of the PSZ film 38. This is to minimize damage of the PSZ film 38 from subsequent processes. For example, an annealing process may be performed to secure an etching selectivity of the PSZ film 38 for the subsequent process of forming a peripheral region closed layer (PCL) mask and etching back process or removing the pad nitride film 34 or cleaning process. Conduct. In particular, this annealing process is preferably performed for about 60 minutes at a temperature of about 900 ℃ using N ₂ gas.

Subsequently, although not shown in the drawing, an etch back process is performed without a mask to simultaneously etch the device isolation layer 39 existing in the cell region and the peripheral region. For example, the etch back process proceeds for about 4 seconds. Since the etchback process may not be completely removed since the cleaning time for the subsequent removal of the pad nitride film 34 may not be sufficient, the etch back process may be performed to block such a possibility in advance. .

Subsequently, as shown in FIG. 3E, a wet cleaning process is performed to remove the pad nitride film 34 (see FIG. 3D). In this wet cleaning, due to the difference in the etching selectivity between the HTO film 37 and the PSZ film 38A, the HTO film 37 remains as it is and only the PSZ film 38A is etched with the pad nitride film 34 to a certain depth. . As a result, a wing-side sidewall protection layer 40 protrudes from the buffer oxide layer 33, and the device isolation layer 39A is surrounded by the sidewall protection layer 40. At this time, the thickness of the sidewall protective film is less than 200 GPa.

Preferably, during the wet cleaning process, a PSZ membrane (using a buffered oxide etchant (BOE) solution in which HF and NH ₄ F are 300: 1 mixed or HF solution diluted with H ₂ O at a ratio of 100: 1) is used. Recess 38A) to a certain depth. Here, the loss depth of the PSZ film 38A is smaller in the peripheral region in which other peripheral elements are formed than in the cell region in which the semiconductor memory cell is formed. For example, the loss depth in the peripheral region is half the loss depth in the cell region. This is because the pattern density of the peripheral region is lower than that of the cell region.

Subsequently, although not shown in the drawing, a PCL mask having a structure that selectively covers only the peripheral region in which the peripheral elements except the semiconductor memory cell are formed is formed.

Subsequently, as illustrated in FIG. 3F, an etch back process 41 using a PCL mask (not shown) is performed to selectively etch the PSZ film 38A in the cell region where the semiconductor memory cell is formed. As a result, the PSZ film 38A in the cell region is selectively etched to a predetermined depth, and at the same time, a portion of the sidewall protective film 40 in the form of a wing (W) having no etching selectivity and the buffer oxide film 33 are removed together. At this time, the sidewall protective film 40 of the peripheral region is preserved as it is. The reason why the PSZ film 38A can be properly etched in accordance with the desired EFH is that a dry etching process such as an etch back is performed instead of wet etching.

The etching process using the PCL mask (not shown) is performed to separately control the effective field oxide height (EFH) between the cell region and the peripheral region.

Subsequently, the strip process is performed to remove the PCL mask, followed by a washing process. This cleaning process is finally performed to control the EFH of the cell region and the peripheral region. As a result, the device isolation layer 39B having the appropriate EFH is formed in the cell region, and the sidewall protective layer 40 having the wing shape W exists on both sidewalls of the polysilicon layer 32. At this time, the thickness of the sidewall protective film is less than 150 GPa.

Therefore, the freedom of interference of the flash memory device can be secured due to the formation of the sidewall protective film. Through this, the interference characteristics of the flash memory device may be improved to improve device characteristics.

For reference, FIGS. 4A and 4B are transmission electron microscope (TEM) images illustrating a flash memory device formed according to an exemplary embodiment of the present invention.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the sidewall protective film is automatically formed on both sidewalls of the polysilicon film for the floating gate when the SA-STI process is applied, thereby improving the interference characteristics of the flash memory device.

In addition, according to the present invention, the effective height of the device isolation film is controlled by dry etching during the etching of the PSZ film constituting the device isolation film, and in particular, the planarization process for forming the device isolation film is performed only once, that is, the PSZ CMP is performed. It is possible to minimize its own change in EFH. Therefore, the effective height EFH of the device isolation film can be easily controlled.

In addition, according to the present invention, it is possible to simplify the overall process by omitting the four-step process than the conventional, thereby obtaining a cost reduction effect.

Claims (10)

Providing a substrate in which a tunnel oxide film, a floating gate conductive film, and a pad nitride film are sequentially stacked; Etching a portion of the pad nitride film, the conductive film, the tunnel oxide film, and the substrate to form a trench; Depositing a device isolation oxide film on an upper surface of an entire structure such that a portion of the trench is buried; Forming a spin on dielectric film on the oxide layer to completely fill the trench; Planarizing the spin-on insulating film to expose the pad nitride film; Heat-treating the spin-on insulating film; Removing the pad nitride layer to expose a portion of the oxide layer over the conductive layer; And Etching the spin-on insulating layer by performing a dry etching process Flash memory device manufacturing method comprising a. The method of claim 1, The spin-on insulating film is a method of manufacturing a flash memory device formed of a polysilazane film. The method of claim 2, And the oxide film is formed by continuously depositing a high density plasma oxide film and a high temperature oxide film. The method of claim 3, wherein Before depositing the oxide film, And forming a monthly oxide film along the inner surface of the trench. The method of claim 4, wherein The monthly oxide film is a flash memory device manufacturing method to form a thickness of 30 ~ 80Å by using a furnace or radical method at a process temperature of 700 ~ 900 ℃. The method of claim 4, wherein And forming a buffer oxide film on the conductive film after forming the conductive film. The method of claim 6, And the buffer oxide layer is removed together with the spin-on insulating layer during dry etching. The method according to any one of claims 1 to 7, The heat treatment of the spin-on insulating film is a flash memory device manufacturing method using N ₂ gas. The method of claim 8, The planarization of the spin-on insulating film is performed by a chemical mechanical polishing process. The method according to any one of claims 1 to 7, Dry etching the spin-on insulating film, Forming a mask having a structure for selectively covering a peripheral area in which peripheral devices except for a flash memory cell are formed; And Selectively dry etching the SOD layer in the cell region through the mask Flash memory device manufacturing method comprising a.

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