KR20080022275A - Method for manufacturing demos device - Google Patents

Method for manufacturing demos device Download PDF

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KR20080022275A
KR20080022275A KR1020060085493A KR20060085493A KR20080022275A KR 20080022275 A KR20080022275 A KR 20080022275A KR 1020060085493 A KR1020060085493 A KR 1020060085493A KR 20060085493 A KR20060085493 A KR 20060085493A KR 20080022275 A KR20080022275 A KR 20080022275A
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well
layer
drain
source
forming
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KR1020060085493A
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Korean (ko)
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KR100840659B1 (en
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정진효
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method for manufacturing a DEMOS device is provided to lower resistance of a high-voltage well region by forming a doped layer of high concentration under a well region. The impurity ion of low concentration is implanted on the entire surface of a silicon substrate(200) to form a well. The impurity ion of high concentration is implanted on a region under the well to form a doped layer. Both sides of the well receive impurity ion to be a first conductive-type first source/drain region. A gate oxide layer(202a) and a gate polysilicon layer pattern(206a) are formed on the substrate, and then a nitride layer is formed on the entire surface of the substrate. The nitride layer is patterned to form a gate spacer(210), and then a silicide blocking layer(212) is deposited on the entire surface of the substrate. The substrate is subjected to an ion implantation process by using the silicide blocking layer to form a second conductive-type second source/drain. A silicide layer(216) is formed on the second source/drain and the gate polysilicon layer pattern.

Description

디이모스 소자의 제조 방법{Method for Manufacturing DEMOS Device}Method for manufacturing DEMOS device {Method for Manufacturing DEMOS Device}

도 1a 내지 도 1e는 종래기술에 따른 고전압소자의 웰 형성방법을 설명하기 위한 공정단면도,1A to 1E are cross-sectional views illustrating a method of forming a well of a high voltage device according to the prior art;

도 2a 내지 도 2g는 본 발명의 실시예에 따른 디이모스 소자의 제조 방법을 나타낸 공정 단면도이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a DIM device according to an exemplary embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

200: 실리콘 기판 202: 버퍼 산화막200: silicon substrate 202: buffer oxide film

202a: 게이트 산화막 204: P웰202a: gate oxide film 204: P well

204a: 고농도 P형 도핑층 206: 게이트 폴리실리콘막204a: high concentration P-type doping layer 206: gate polysilicon film

206a: 게이트 폴리실리콘막 패턴 208: N-형 소스/드레인 영역206a: gate polysilicon film pattern 208: N-type source / drain region

210: 게이트 스페이서 212: 실리사이드 차단막210: gate spacer 212: silicide blocking film

214: N+형 소스/드레인 영역 216: 실리사이드막214: N + type source / drain region 216: silicide film

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 더욱 상세하게는 반도체 소자의 스냅백 특성 및 래치업 특성을 향상시키기 위한 디모스 트랜지스터의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a MOS transistor for improving the snap-back characteristics and latch-up characteristics of the semiconductor device.

최근에, 반도체 회로의 고집적화에 따라 다양한 기능의 집적회로가 동일 제품에 공존하면서 다중 전압/전류 구동용 고전압 트랜지스터(High Voltage Transistor)가 요구되고 있다. 한편, 박막트랜지스터 액정 디스플레이 소자(TFT-LCD: Thin Film Transistor-Liquid Crystal Device)는 구동회로와 제어회로로 구성되는데, 제어회로는 5 V 로직으로, 구동부는 30 V 이상의 고전압 트랜지스터로 구성되어 있어 표준 CMOS(Complementary Metal Oxide Semiconductor FET)공정으로는 제조가 불가능하며 고전압 소자의 제조 공정을 적용할 경우 제어회로의 전력소모가 크고 제품의 크기도 증가하는 문제점이 있다.In recent years, with the high integration of semiconductor circuits, integrated circuits of various functions coexist in the same product, and high voltage transistors for driving multiple voltage / current are required. On the other hand, TFT-LCD (Thin Film Transistor-Liquid Crystal Device) is composed of driving circuit and control circuit. It is not possible to manufacture by CMOS (Complementary Metal Oxide Semiconductor FET) process and there is a problem that the power consumption of the control circuit is large and the size of the product increases when the manufacturing process of the high voltage device is applied.

이러한 문제점을 해결하기 위해 0.6 ㎛ 로직기술에 고전압 트랜지스터를 적용하기 위해 마스크 공정과 이온주입공정을 추가하여 로직소자의 특성은 변하지 않고 전압과 전류수준을 용이하게 조절할 수 있는 방법이 제안되고 있다.In order to solve this problem, a method of adding a mask process and an ion implantation process to apply a high voltage transistor to a 0.6 μm logic technology has been proposed to easily adjust voltage and current levels without changing the characteristics of the logic device.

도 1a 내지 도 1e는 종래기술에 따른 고전압소자의 웰 형성방법을 설명하기 위한 공정단면도로서, 구체적으로는 표준 고전압 16 V 공정의 웰 형성을 보인 것이다.1A to 1E are cross-sectional views illustrating a well forming method of a high voltage device according to the related art, and specifically, illustrates well formation in a standard high voltage 16 V process.

종래기술에 따른 고전압소자의 웰 형성방법은, 도 1a에 도시된 바와 같이, 먼저, 고전압 N웰 형성영역(Ⅰ), 고전압 P웰 형성영역(Ⅱ), 로직 P웰 형성영역(Ⅲ) 및 로직 N웰 형성영역(Ⅳ)이 각각 구비된 P형 실리콘기판(1)을 제공한다.A well forming method of a high voltage device according to the prior art, as shown in FIG. 1A, first, a high voltage N well forming region (I), a high voltage P well forming region (II), a logic P well forming region (III), and a logic. A P-type silicon substrate 1 is provided, each having an N well forming region IV.

이어서, 기판(1) 위에 산화막(3) 및 질화막(미도시)을 형성하고, 질화막 위에 고전압 N웰(HNWELL)형성영역(Ⅰ)을 노출시키는 제1 감광막 패턴(7)을 형성한다. 이어서, 제1 감광막패턴(7)을 마스크로 하여 질화막을 식각하고 나서, 기판 전면에 고전압 N웰 형성을 위한 제1 이온주입 공정(9)을 실시한다. 도 1a에서 미설명된 도면부호 5는 식각 후 잔류된 질화막을 나타낸다.Subsequently, an oxide film 3 and a nitride film (not shown) are formed on the substrate 1, and a first photosensitive film pattern 7 exposing the high voltage N well (HNWELL) formation region I is formed on the nitride film. Subsequently, the nitride film is etched using the first photosensitive film pattern 7 as a mask, and then a first ion implantation step 9 for forming a high voltage N well is performed on the entire surface of the substrate. Reference numeral 5 not described in FIG. 1A denotes a nitride film remaining after etching.

그런 다음, 제1 감광막 패턴(7)을 제거하고, 도 1b에 도시된 바와 같이, 기판 전면에 로직 N웰 형성영역(Ⅳ)을 노출시키는 제2 감광막패턴(11)을 형성한다. 이후, 제2 감광막패턴(11)을 마스크로 하여 기판 전면에 로직 N웰 형성을 위한 제2 이온주입공정(13)을 실시한다.Thereafter, the first photoresist layer pattern 7 is removed and a second photoresist layer pattern 11 exposing the logic N well forming region IV is formed on the entire surface of the substrate as shown in FIG. 1B. Subsequently, a second ion implantation process 13 is performed to form logic N wells on the entire surface of the substrate using the second photoresist pattern 11 as a mask.

이후, 제2 감광막패턴(11)을 제거하고, 도 1c에 도시된 바와 같이, 잔류된 질화막을 마스크로 기판의 제1 산화막을 산화시켜 고전압 N웰 형성영역(Ⅰ) 및 로직 N웰 형성영역(Ⅳ)에 선택적으로 제2 산화막(15)을 형성한다. 그런 다음, 잔류된 질화막을 제거한다. 이때, P웰 형성영역(Ⅱ)(Ⅲ)에는 제1 산화막(3)이 존재한다.Thereafter, the second photoresist film pattern 11 is removed, and as shown in FIG. 1C, the first oxide film of the substrate is oxidized using the remaining nitride film as a mask to form the high voltage N well forming region I and the logic N well forming region ( A second oxide film 15 is optionally formed in IV). Then, the remaining nitride film is removed. At this time, the first oxide film 3 is present in the P well forming regions II and III.

이어서, 도 1d에 도시된 바와 같이, 제2 산화막(15)이 구비된 기판 전면에 P웰 형성을 위한 제3 이온주입 공정(17)을 실시한다. 이때, 고전압 N웰 형성영역(Ⅰ) 및 로직 N웰 형성영역(Ⅳ)에는 상대적으로 두꺼운 제2 산화막(15)이 형성되어 P웰 형성을 위한 제3 이온주입 공정에 영향을 받지 않고, P웰 형성영역(Ⅱ)(Ⅲ)에만 선택적으로 이온주입이 실시된다.Subsequently, as illustrated in FIG. 1D, a third ion implantation process 17 for forming a P well is performed on the entire surface of the substrate provided with the second oxide film 15. At this time, a relatively thick second oxide film 15 is formed in the high voltage N well forming region I and the logic N well forming region IV, so that the P well is not affected by the third ion implantation process for forming the P well. Ion implantation is selectively performed only in the formation regions (II) and (III).

그런 다음, 기판 결과물에 열처리를 하여 주입된 이온들을 확산시켜, 도 1e에 도시된 바와 같이, 고전압 N웰(HNWELL)(19), 고전압 P웰(HPWELL)(21), P웰(PWELL)(23) 및 N웰(NWELL)(25)을 형성한다.Then, the implanted ions are diffused by heat treatment on the substrate resultant, and as shown in FIG. 1E, a high voltage N well (HNWELL) 19, a high voltage P well (HPWELL) 21, and a P well (PWELL) ( 23 and NWELL 25 are formed.

하지만, 종래기술에 따른 고전압소자의 웰 형성방법에 의하면, 고전압 DEMOS 소자의 정션 브레이크 다운 전압(Junction Break Down Voltage)을 높이기 위해 저농도로 고전압 P웰과 고전압 N웰 영역에 이온주입을 한 후 고온 드라이브-인(Drive-in) 공정을 통해 고전압 P웰과 고전압 N웰을 P형 기판 깊숙이 확산시켜 저농도의 균일한 고전압 P웰과 고전압 N웰을 형성함으로써, 저농도의 고전압 P웰은 정션 브레이크 다운 전압은 향상시키지만, 고전압 P웰 저항을 증가시켜 중전압 NMOS와 고전압 DENMOS의 스냅백(Snap Back) 특성을 감소시키고, 래치업(Latch up) 특성도 함께 나쁘게 하여 중전압 NMOS와 고전압 DENMOS의 신뢰성을 떨어뜨리는 문제점이 있었다.However, according to the well-formed method of forming a high voltage device according to the prior art, in order to increase the junction break down voltage of a high voltage DEMOS device, ion implantation is performed at a high concentration in a high voltage P well and a high voltage N well region at a low concentration, and then a high temperature drive Through the drive-in process, high voltage P wells and high voltage N wells are diffused deep into the P-type substrate to form low concentration uniform high voltage P wells and high voltage N wells. Increase the high voltage P well resistance to reduce the snap back characteristics of the medium voltage NMOS and high voltage DENMOS, and also worse the latch up characteristics to reduce the reliability of the medium voltage NMOS and high voltage DENMOS. There was a problem.

본 발명은 상기한 바와 같은 문제점을 해결하기 위하여 안출된 것으로서, 반도체 소자의 스냅백 특성 및 래치업 특성을 향상시키기 위한 디모스 트랜지스터의 제조 방법을 제공한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a manufacturing method of a MOS transistor for improving snapback characteristics and latchup characteristics of a semiconductor device.

본 발명의 다른 목적은 디이모스 소자의 제조 시 웰 영역 아래에 고농도의 도핑층을 형성함으로써, 고전압 웰 영역의 저항을 낮추기 위한 제조 방법을 제공한다.Another object of the present invention is to provide a manufacturing method for lowering the resistance of a high voltage well region by forming a high concentration doping layer under the well region when manufacturing a DMOS device.

이와 같은 목적을 달성하기 위한 본 발명은, 디이모스 소자의 제조 방법에 있어서, (a) 실리콘 기판의 전면에 저농도의 불순물 이온을 주입하여 웰을 형성하는 단계; (b) 상기 웰의 하부 영역에 고농도의 불순물 이온을 주입하여 고농도 도핑층을 형성하는 단계; (c) 상기 웰의 양측에 불순물 이온을 주입하여 깊은 깊이의 제1 도전형의 제1 소스/드레인 영역을 형성하는 단계; (d) 실리콘 기판 상에 게이트 산화막 및 게이트 폴리실리콘막 패턴을 형성하는 단계; (e) 상기 게이트 폴리실리콘막 패턴을 충분히 덮도록 상기 실리콘 기판의 전면에 질화막을 형성하는 단계; (f) 상기 질화막을 패터닝하여 상기 게이트 폴리실리콘막 패턴의 일측벽에 게이트 스페이서를 형성하고, 상기 실리콘 기판의 전면에 실리사이드 차단막을 증착하고 패터닝하여 상기 게이트 산화막과 제2 도전형의 제2 소스/드레인이 형성될 부분의 실리사이드 차단막을 제거하는 단계; (g) 상기 실리사이드 차단막을 마스크로 하는 이온주입 공정을 통하여 상기 제1 소스/드레인에 상기 제2 소스/드레인을 형성하는 단계; 및 (h) 상기 실리사이드 차단막을 마스크로 이용하여 상기 제2 소스/드레인 및 상기 게이트 폴리실리콘막 패턴의 상부면에 실리사이드막을 증착하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method for manufacturing a DMOS device, comprising: (a) implanting a low concentration of impurity ions into an entire surface of a silicon substrate to form a well; (b) forming a highly doped layer by implanting a high concentration of impurity ions into the lower region of the well; (c) implanting impurity ions into both sides of the well to form a first source / drain region of a first conductivity type having a deep depth; (d) forming a gate oxide film and a gate polysilicon film pattern on the silicon substrate; (e) forming a nitride film over the entire surface of the silicon substrate to sufficiently cover the gate polysilicon film pattern; (f) patterning the nitride film to form a gate spacer on one side wall of the gate polysilicon film pattern, and depositing and patterning a silicide blocking film on the entire surface of the silicon substrate to form the gate oxide film and the second source / second conductivity type. Removing the silicide blocking layer of the portion where the drain is to be formed; (g) forming the second source / drain in the first source / drain through an ion implantation process using the silicide blocking layer as a mask; And (h) depositing a silicide layer on an upper surface of the second source / drain and the gate polysilicon layer pattern using the silicide blocking layer as a mask.

이하, 본 발명의 실시예를 첨부된 도면들을 참조하여 상세히 설명한다. 또한, 본 발명을 설명함에 있어, 관련된 공지 구성 또는 기능에 대한 구체적인 설명이 본 발명의 요지를 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명은 생략한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

본 발명의 실시예에서는 디이모스 트랜지스터의 제조 방법을 설명한다. DENMOS 및 DEPMOS는 도전형만 반대로서 구조는 동일하므로, 상세한 설명에서는 DENMOS에 대해서만 설명한다.In the embodiment of the present invention, a method for manufacturing a DMOS transistor will be described. Since DENMOS and DEPMOS have the same structure except the conductivity type, only the DENMOS will be described in the detailed description.

도 2a 내지 도 2g는 본 발명의 실시예에 따른 디이모스 소자의 제조 방법을 나타낸 공정 단면도이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a DIM device according to an exemplary embodiment of the present invention.

도 2a를 참조하면, 실리콘 기판(200) 상에 버퍼 산화막(202)을 형성하고, 버퍼 산화막(202)이 형성된 실리콘 기판(200)의 전면에 저농도의 P형 불순물을 주입하여 P웰(204)을 형성한다.Referring to FIG. 2A, a P well 204 is formed by forming a buffer oxide film 202 on a silicon substrate 200, and implanting a low concentration of P-type impurities into the entire surface of the silicon substrate 200 on which the buffer oxide film 202 is formed. To form.

도 2b를 참조하면, P웰(204)의 하부 영역에 고농도의 P형 불순물을 주입하여 고농도 P형 도핑층(204a)을 형성한다. 여기서, 이온주입 공정 시 보론(B) 등의 P형 불순물을 사용하며, 1 Mev 이상의 이온주입 에너지로 실시함이 바람직하다. 또한, 이온주입 공정 시 이온주입 에너지 레벨을 나누어 여러 차례 이온주입 공정을 실시함으로써, 다수의 P형 도핑층을 생성할 수 있고, 이로 인해 P형 도핑층의 저항을 더 낮게 만들 수 있다.Referring to FIG. 2B, a high concentration P-type doping layer 204a is formed by implanting a high concentration of P-type impurities into the lower region of the P well 204. Here, in the ion implantation process, P-type impurities such as boron (B) are used, and the ion implantation energy of 1 Mev or more is preferable. In addition, by performing the ion implantation process by dividing the ion implantation energy level in the ion implantation process several times, it is possible to generate a plurality of P-type doping layer, thereby making the resistance of the P-type doping layer lower.

도 2c를 참조하면, 실리콘 기판(200)의 P웰(204)의 양측에 N형 불순물을 주입하여 묽고 깊은 깊이의 N-형 소스/드레인 영역(208)을 형성한다. 이어서, 버퍼 산화막(202)를 제거한 후 실리콘 기판(200)의 전면에 게이트 산화막(202a)을 형성한다.Referring to FIG. 2C, N-type impurities are implanted into both sides of the P well 204 of the silicon substrate 200 to form a thin and deep N-type source / drain region 208. Subsequently, after the buffer oxide film 202 is removed, the gate oxide film 202a is formed on the entire surface of the silicon substrate 200.

도 2d 및 도 2e를 참조하면, 게이트 산화막(202a) 상에 게이트 폴리실리콘막(206)을 형성하고, 게이트 폴리실리콘막(206)을 패터닝하여 게이트 폴리실리콘막 패턴(206a)을 형성한다. 이어서, 게이트 폴리실리콘막 패턴(206a)의 양측벽에 게이트 스페이서(210)를 형성한다.2D and 2E, the gate polysilicon film 206 is formed on the gate oxide film 202a, and the gate polysilicon film 206 is patterned to form the gate polysilicon film pattern 206a. Subsequently, gate spacers 210 are formed on both sidewalls of the gate polysilicon layer pattern 206a.

도 2f를 참조하면, 반도체 기판(200)의 전면에 실리사이드 차단막(212)을 증착하고, 사진/에칭 공정을 통하여 게이트 산화막(202a)과 N+형 소스/드레인 영역(214)이 형성될 부분의 실리사이드 차단막(212)을 제거한다.Referring to FIG. 2F, the silicide blocking layer 212 is deposited on the entire surface of the semiconductor substrate 200, and the silicide of the portion where the gate oxide layer 202a and the N + type source / drain region 214 are to be formed through a photo / etching process. The blocking film 212 is removed.

도 2g를 참조하면, 실리사이드 차단막(212)을 마스크로 하는 이온주입 공정을 통하여 N-형 소스/드레인 영역(208)에 고농도 불순물 이온을 주입하고, N+형 소스/드레인 영역(214)을 형성한다. 이후, 실리사이드 차단막(212)을 마스크로 이용하여 N+형 소스/드레인 영역(214) 및 게이트 폴리실리콘막 패턴(206a)의 상부면에 실리사이드막(216)을 증착한다.Referring to FIG. 2G, a high concentration of impurity ions are implanted into the N-type source / drain region 208 through an ion implantation process using the silicide blocking layer 212 as a mask to form an N + type source / drain region 214. . Thereafter, the silicide layer 216 is deposited on the top surfaces of the N + type source / drain regions 214 and the gate polysilicon layer pattern 206a using the silicide blocking layer 212 as a mask.

이상의 설명은 본 발명의 기술 사상을 예시적으로 설명한 것에 불과한 것으로서, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자라면 본 발명의 본질적인 특성에서 벗어나지 않는 범위에서 다양한 수정 및 변형이 가능할 것이다. 따라서, 본 발명에 개시된 실시예들은 본 발명의 기술 사상을 한정하기 위한 것이 아니라 설명하기 위한 것이고, 이러한 실시예에 의하여 본 발명의 기술 사상의 범위가 한정되는 것은 아니다. 본 발명의 보호 범위는 아래의 청구범위에 의하여 해석되어야 하며, 그와 동등한 범위 내에 있는 모든 기술 사상은 본 발명의 권리범위에 포함되는 것으로 해석되어야 할 것이다.The above description is merely illustrative of the technical idea of the present invention, and those skilled in the art to which the present invention pertains may make various modifications and changes without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the present invention.

이상에서 설명한 바와 같이 본 발명에 의하면, 디이모스 소자의 제조 시 웰 영역 아래에 고농도의 도핑층을 형성함으로써, 고전압 웰 영역의 저항을 낮추고, 이로 인해 웰 영역에 만들어지는 중전압 모스 소자 및 고전압 모스 소자의 소냅백 특성을 개선하고, 웰 영역의 저항 감소로 인해 래치업 특성도 함께 개선하는 효과가 있다.As described above, according to the present invention, a high concentration doping layer is formed under a well region during fabrication of a DIMOS device, thereby lowering the resistance of the high voltage well region, thereby making the medium voltage MOS device and the high voltage MOS formed in the well region. This improves the snoopback characteristics of the device and also improves the latchup characteristics due to the reduced resistance of the well region.

Claims (3)

디이모스 소자의 제조 방법에 있어서,In the method for manufacturing a dimos device, (a) 실리콘 기판의 전면에 저농도의 불순물 이온을 주입하여 웰을 형성하는 단계;(a) implanting a low concentration of impurity ions into the entire surface of the silicon substrate to form a well; (b) 상기 웰의 하부 영역에 고농도의 불순물 이온을 주입하여 고농도 도핑층을 형성하는 단계;(b) forming a highly doped layer by implanting a high concentration of impurity ions into the lower region of the well; (c) 상기 웰의 양측에 불순물 이온을 주입하여 깊은 깊이의 제1 도전형의 제1 소스/드레인 영역을 형성하는 단계;(c) implanting impurity ions into both sides of the well to form a first source / drain region of a first conductivity type having a deep depth; (d) 실리콘 기판 상에 게이트 산화막 및 게이트 폴리실리콘막 패턴을 형성하는 단계;(d) forming a gate oxide film and a gate polysilicon film pattern on the silicon substrate; (e) 상기 게이트 폴리실리콘막 패턴을 충분히 덮도록 상기 실리콘 기판의 전면에 질화막을 형성하는 단계;(e) forming a nitride film over the entire surface of the silicon substrate to sufficiently cover the gate polysilicon film pattern; (f) 상기 질화막을 패터닝하여 상기 게이트 폴리실리콘막 패턴의 일측벽에 게이트 스페이서를 형성하고, 상기 실리콘 기판의 전면에 실리사이드 차단막을 증착하고 패터닝하여 상기 게이트 산화막과 제2 도전형의 제2 소스/드레인이 형성될 부분의 실리사이드 차단막을 제거하는 단계;(f) patterning the nitride film to form a gate spacer on one side wall of the gate polysilicon film pattern, and depositing and patterning a silicide blocking film on the entire surface of the silicon substrate to form the gate oxide film and the second source / second conductivity type. Removing the silicide blocking layer of the portion where the drain is to be formed; (g) 상기 실리사이드 차단막을 마스크로 하는 이온주입 공정을 통하여 상기 제1 소스/드레인에 상기 제2 소스/드레인을 형성하는 단계; 및(g) forming the second source / drain in the first source / drain through an ion implantation process using the silicide blocking layer as a mask; And (h) 상기 실리사이드 차단막을 마스크로 이용하여 상기 제2 소스/드레인 및 상기 게이트 폴리실리콘막 패턴의 상부면에 실리사이드막을 증착하는 단계(h) depositing a silicide layer on an upper surface of the second source / drain and the gate polysilicon layer pattern using the silicide blocking layer as a mask 를 포함하는 것을 특징으로 하는 디이모스 소자의 제조 방법.Method for manufacturing a Dimos device, characterized in that it comprises a. 제1항에서, 상기 단계 (b)에서,In claim 1, in step (b), 상기 고농도의 불순물 이온은 보론(B)을 포함하는 P형 불순물을 이용하는 것을 특징으로 하는 디이모스 소자의 제조 방법.The impurity ion of high concentration uses a P-type impurity containing boron (B). 제1항에서, 상기 단계 (b)에서,In claim 1, in step (b), 이온주입 공정 시 이온주입 에너지 레벨을 나누어 여러 차례 이온주입 공정을 실시함으로써, 다수의 P형 도핑층을 생성할 수 있는 것을 특징으로 하는 디이모스 소자의 제조 방법.A plurality of P-type doping layers can be produced by dividing the ion implantation energy level in the ion implantation process and performing the ion implantation process several times.
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CN107086246A (en) * 2017-02-28 2017-08-22 中国电子科技集团公司第五十五研究所 A kind of thin grid structure of radio frequency LDMOS and preparation method thereof
CN107123672A (en) * 2017-02-28 2017-09-01 中国电子科技集团公司第五十五研究所 Radio frequency LDMOS thin grid structures of PolySi and preparation method thereof
CN113013101A (en) * 2020-06-12 2021-06-22 上海积塔半导体有限公司 Method for manufacturing semiconductor device and semiconductor device

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JPH08213484A (en) * 1994-11-24 1996-08-20 Nippondenso Co Ltd Semiconductor device and its production
KR100415191B1 (en) * 1997-06-25 2004-03-26 삼성전자주식회사 Method for fabricating asymmetric cmos transistor
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Publication number Priority date Publication date Assignee Title
CN107086246A (en) * 2017-02-28 2017-08-22 中国电子科技集团公司第五十五研究所 A kind of thin grid structure of radio frequency LDMOS and preparation method thereof
CN107123672A (en) * 2017-02-28 2017-09-01 中国电子科技集团公司第五十五研究所 Radio frequency LDMOS thin grid structures of PolySi and preparation method thereof
CN107086246B (en) * 2017-02-28 2020-05-22 中国电子科技集团公司第五十五研究所 Radio frequency LDMOS thin gate structure and preparation method thereof
CN113013101A (en) * 2020-06-12 2021-06-22 上海积塔半导体有限公司 Method for manufacturing semiconductor device and semiconductor device

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