KR20080020134A - Method for forming isolation layer of semiconductor device - Google Patents

Abstract

A method for forming an isolation layer of a semiconductor device is provided to prevent an HEIP(Hot Electron Induced Punchthrough) effect by removing a part of a linear nitride layer of a peripheral circuit region. A cell region(C) and a peripheral circuit region(P) of a semiconductor substrate(11) are etched to form trenches(T). A linear nitride layer(14) and a linear oxide layer are formed on the entire surface of the semiconductor substrate including the trenches. A first insulating layer having uniform thickness is formed on the linear oxide layer by performing a deposition process of an HDP(High Density Plasma) method. The nitride layer is partially removed from a sidewall of the trench of the peripheral region by performing an etch process of the HDP method. A second insulating layer is formed to bury the trenches. The linear nitride layer formed at a top end of the sidewall of the trench of the peripheral circuit region is rapidly etched according to an etching difference due to the pattern density.

Description

METHODS FOR FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE

1A to 1E are cross-sectional views illustrating processes of forming a device isolation film of a semiconductor device in accordance with an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings

C: Cell area P: Peripheral circuit area

11 semiconductor substrate 12 pad oxide film

13 pad nitride film 14 linear nitride film

15: oxide film 16: SOD film

17: device isolation film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a device isolation layer of a semiconductor device, and is capable of preventing a Hot Electron Induced Punchthrough (HEIP) phenomenon caused by a PMOS transistor structure in a peripheral circuit region due to a linear nitride layer during a shallow trench isolation (STI) process. A device isolation film formation method of a device is provided.

With the advance of semiconductor technology, the speed and the high integration of semiconductor devices are progressing rapidly, and with this, the demand for the refinement | miniaturization of a pattern and the high precision of a pattern dimension is increasing. This requirement applies not only to patterns formed in device regions, but also to device isolation films that occupy a relatively large area.

Here, a conventional device isolation film has been formed by a LOCOS process, and the device isolation film according to the LOCOS process generates a bird's-beak having a beak shape at an upper corner thereof. It has the disadvantage of increasing the area of, and thus has a limitation in its use.

Accordingly, most of the semiconductor devices are forming the device isolation layer by using a shallow trench isolation (STI) process that can be formed in a small width without the occurrence of buzz-big to implement high integration.

Hereinafter, a conventional method of forming an isolation layer using an STI process will be described.

First, a pad oxide film and a pad nitride film are sequentially formed on a semiconductor substrate, and then the pad nitride film, the pad oxide film, and the substrate are sequentially etched to form trenches.

Next, after the sidewall oxide film is formed on the trench surface, a linear nitride film is formed on the entire surface of the substrate including the sidewall oxide film, and then an insulating film is deposited to fill the trench on the linear nitride film.

Subsequently, the insulating film and the linear nitride film are chemical mechanical polished (CMP) until the pad nitride film is exposed, and then the exposed pad nitride film and the pad oxide film are sequentially removed to form a device isolation film.

However, according to the method of forming a device isolation film using the conventional STI process as described above, there is a problem that the linear nitride film causes the HEIP phenomenon in the PMOS transistor structure of the peripheral circuit region. That is, the linear nitride film is formed to relieve stress of the device and to prevent the diffusion of doping elements such as boron to improve refresh characteristics. There is a problem that the HEIP phenomenon is caused.

Meanwhile, in order to solve the above problem, a method of selectively removing the linear nitride film portion of the peripheral circuit region exposed by the mask pattern by forming a mask pattern selectively exposing the peripheral circuit region has been proposed. In this case, there is a disadvantage that the entire process becomes complicated.

Accordingly, the present invention has been made to solve the above-mentioned problems, and the method of forming a device isolation layer of a semiconductor device capable of preventing the HEIP phenomenon caused in the PMOS transistor structure of the peripheral circuit region due to the linear nitride film during the STI process. The purpose is to provide.

A method of forming a device isolation film of a semiconductor device according to the present invention for achieving the above object includes forming trenches by etching respective regions of a semiconductor substrate partitioned into a cell region and a peripheral circuit region; Sequentially forming a linear nitride film and a linear oxide film on the entire surface of the substrate including the trench; Forming a first insulating film with a uniform thickness by performing the deposition process in an HDP method in which deposition and etching are repeatedly performed on the linear oxide film; Performing an etching process in the HDP method to remove a portion of the linear nitride layer formed at an upper end of the trench sidewall in the peripheral circuit region; And forming a second insulating layer to completely fill the trench, wherein the linear nitride layer is formed at an upper end portion of the trench sidewall of the peripheral circuit region by an etching amount difference depending on a pattern density during the etching process in the HDP method. It is characterized by faster etching.

Here, the first insulating film is formed to a thickness of 200 ~ 300 200.

The etching process for removing the linear nitride film portion formed at the upper end portion of the trench sidewall in the peripheral circuit region is performed for 10 to 15 seconds.

The second insulating layer may be formed of an SOD layer.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be briefly described. According to the present invention, after depositing a sidewall oxide film and a linear nitride film in a trench, high density plasma (HDP) is repeatedly performed on the front surface of the substrate on which the linear nitride film is formed. ) To form an oxide film with a uniform thickness by performing only a deposition process, and then etching time is adjusted to selectively remove only the portion of the linear nitride film formed at the upper end of the trench sidewall of the peripheral circuit region with respect to the oxide film. Do this.

In this case, the oxide layer and the linear nitride layer of the peripheral circuit region are preferentially etched due to the pattern density difference between the cell region and the peripheral circuit region, and thus, due to the linear nitride layer in the PMOS transistor structure of the peripheral circuit region without the complexity of the process. HEIP can be prevented.

1A to 1E are cross-sectional views illustrating processes for forming a device isolation film of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1A, a pad oxide film 12 and a pad nitride film 13 are sequentially formed on a semiconductor substrate 11 having a cell region C and a peripheral circuit region P and having an active region and an isolation region. After deposition, a mask pattern (not shown) is formed on the pad nitride layer 13 to expose the device isolation region of the substrate 11.

Subsequently, portions of the pad nitride layer 13 and the pad oxide layer 12 exposed by the mask pattern are etched, the mask pattern is removed, and the etched pad nitride layer 13 and the pad oxide layer 12 are etched. A trench T is formed by etching the device isolation region of the substrate 11 using the. At this time, the trench (T) is formed to a depth of about 2500 ~ 3000Å.

Referring to FIG. 1B, after the sidewall oxide film (not shown) is formed on the surface of the substrate 11 in the trench T, the linear nitride film 14 and the linear oxide film are formed on the resultant of the substrate 11 including the sidewall oxide film. (Not shown) are formed in sequence. Here, the linear nitride layer 14 is formed to reduce the stress of the device and to prevent the diffusion of doping elements such as boron to improve refresh characteristics.

Referring to FIG. 1C, an oxide film 15 is deposited to a uniform thickness on the linear oxide film. Here, the oxide film 15 is formed by performing only the first deposition process of the HDP method consisting of the deposition / etching / deposition / etching / deposition step of performing the deposition and etching process repeatedly, about 200 ~ 300Å It is formed to the thickness of.

Referring to FIG. 1D, a first etching process of the HDP method is performed on the resultant of the substrate 11 having the oxide film 15 formed thereon such that the linear nitride film 14 is removed from the upper end portion of the sidewall of the trench T by about 500 to 1000 Å. .

In this case, the etching process is performed using a sputtering method, and the linear nitride layer formed on the upper sidewall of the trench T sidewall of the peripheral circuit region P by using a difference in the pattern density between the cell region C and the peripheral circuit region P. (14) The etching time is adjusted so that the part is removed, preferably, 10 to 15 seconds. That is, since a difference in pattern density exists in the cell region C and the peripheral circuit region P, the peripheral circuit region P having a lower pattern density than the cell region C even when the etching process is performed for the same time. The oxide film 15, the linear oxide film, and the linear nitride film 14 formed on the substrate may be preferentially etched.

As a result, the loss of the linear nitride layer 14 does not occur in the cell region C during the etching process, but in the peripheral circuit region P having a lower pattern density than the cell region C, an upper end portion of the sidewall of the trench T is formed. In this case, the loss of the linear nitride film 14 occurs. Therefore, in the PMOS transistor structure of the peripheral circuit region P, the HEIP phenomenon caused by the trapped electron charge trapped between the interface between the sidewall oxide film and the linear nitride film 14 can be prevented, and at the same time, The refresh characteristic in the cell region C can be improved.

Referring to FIG. 1E, a SOD (Spin-On Dielectric) layer 16 is deposited on the oxide layer 15 on which the etching process is performed to completely fill the trench T, and then the SOD layer is exposed to expose the pad nitride layer. The film 16 and the oxide film 15 are subjected to chemical mechanical polishing (CMP). Subsequently, the pad nitride layer and the pad oxide layer are removed to form the device isolation layer 17 defining the active region of the substrate 11.

Subsequently, although not shown, a series of subsequent known processes are sequentially performed to complete the semiconductor device.

In the present invention, after depositing an oxide film by performing only a deposition process in the HDP method, the etching process is performed by adjusting the etching time performed on the oxide film in consideration of the pattern density difference between the cell region and the peripheral circuit region. The linear nitride film formed on the substrate remains as it is, improving the refresh characteristics of the device, and selectively removing the linear nitride film formed on the trench of the peripheral circuit region to prevent the HEIP phenomenon caused by the PMOS transistor structure of the peripheral circuit region. have.

In addition, since it is not necessary to perform an additional mask process to selectively remove the linear nitride layer of the peripheral circuit region, a simple process can prevent the HEIP phenomenon caused in the PMOS transistor structure of the peripheral circuit region.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, according to the present invention, the oxide film is deposited by performing only a deposition process of the HDP method in the trench, and then a portion of the linear nitride film of the peripheral circuit region is controlled by controlling the etching time by using the difference in the pattern density between the cell region and the peripheral circuit region. By eliminating, it is possible to prevent the HEIP phenomenon caused in the PMOS transistor structure of the peripheral circuit region.

Claims (4)

Etching each region of the semiconductor substrate divided into a cell region and a peripheral circuit region to form trenches; Sequentially forming a linear nitride film and a linear oxide film on the entire surface of the substrate including the trench; Forming a first insulating film with a uniform thickness by performing the deposition process in an HDP method in which deposition and etching are repeatedly performed on the linear oxide film; Performing an etching process in the HDP method to remove a portion of the linear nitride layer formed at an upper end of the trench sidewall in the peripheral circuit region; And Forming a second insulating film to completely fill the trench; And forming a portion of the linear nitride layer formed at the upper end of the trench sidewall of the peripheral circuit region by the difference in the etching amount according to the pattern density during the etching process in the HDP method. The method of claim 1, And the first insulating film is formed to a thickness of 200 to 300 Å. The method of claim 1, The etching process for removing the linear nitride film portion formed in the upper end portion of the trench sidewall in the peripheral circuit region is performed for 10 to 15 seconds. The method of claim 1, And the second insulating layer is formed of an SOD layer.

Images