KR20080014173A - Method of manufacturing a non-volatile memory device - Google Patents

Abstract

A method for manufacturing a non-volatile memory device is provided to increase an active effective width by forming an active trench in an active region, thereby sufficiently generating an F-N tunneling. A method for manufacturing a non-volatile memory device comprises the steps of: forming a device isolating pattern in a semiconductor substrate(100); partially etching the surface of the substrate defined by the device isolating pattern, and forming an active region having an active trench; forming a tunnel oxidation film on the surface of the active region, continually; forming a preliminary floating gate pattern(106) filling in the active trench(110) on the tunnel oxidation film; forming a dielectric film on the preliminary floating gate pattern; forming a conductive film for a control gate on the dielectric film; and forming a control gate pattern, a dielectric pattern, and a floating gate pattern by etching the conductive film for a control gate, the dielectric film, and the preliminary floating gate pattern, successively.

Description

 Method of manufacturing a non-volatile memory device

1 to 9 are cross-sectional views and perspective views illustrating a method of forming a nonvolatile memory device in accordance with an embodiment of the present invention.

 Explanation of symbols on main parts of drawing

100 semiconductor substrate 108 spacer

110: active trench 112: tunnel oxide film

114a: Floating gate pattern 116: Dielectric film

118: control gate pattern

The present invention relates to a method of manufacturing a nonvolatile memory device. More particularly, the present invention relates to a method of manufacturing a nonvolatile memory device having an active trench.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are volatile and fast data input / output that loses data over time, and data is input once. It can maintain its status, but it can be divided into ROM (read only memory) products with slow data input and output.

In a nonvolatile memory device such as the flash memory device, from a circuit point of view, n cell transistors are connected in series to form a unit string, and the unit strings are connected in parallel between a bit line and a ground line. The NAND type connected to each other and the NOR type each cell transistor connected in parallel between the bit line and the ground line may be classified. The NOR type is advantageous for high speed operation, while the NAND type is advantageous for high integration.

The flash memory unit cell includes a vertical stacked gate structure having a floating gate. In detail, the gate of the flash memory cell has a structure in which a floating gate, a dielectric layer, and a control gate are stacked on the tunnel oxide layer.

Typically, the floating gate electrode at the gate of a NAND type flash memory cell is provided on a line type active region. The floating gate electrode must be formed in a predetermined size or more on the active region to maintain a cell current and a coupling ratio. That is, in order to increase the operating speed of the flash memory device by increasing the cell current, it is desirable to increase the width of the active while reducing the channel length.

However, as the design-rules of memory cells become smaller and smaller, the width of the active region continues to decrease. This prevents sufficient F-N tunneling effect from occurring. In addition, the cell current is reduced during operation, the operation speed is decreased, and the scattering characteristics of the cell current are deteriorated, thereby causing defects such as over erase.

An object of the present invention for solving the above problems is to provide a method of manufacturing a nonvolatile memory device that can sufficiently generate F-N tunneling.

According to an aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, which includes forming a device isolation pattern on a semiconductor substrate and partially etching the substrate surface defined by the device isolation pattern. An active region having a trench is formed, and a tunnel oxide film is continuously formed on the surface of the active region. Subsequently, a preliminary floating gate pattern is formed on the tunnel oxide layer to fill the active trench, a dielectric layer is formed on the preliminary floating gate pattern, and a control gate conductive layer is formed on the dielectric layer. The conductive film, the dielectric film, and the preliminary floating gate pattern are sequentially etched to form a control gate pattern, a dielectric film pattern, and a floating gate pattern.

According to one embodiment of the present invention, the forming of the device isolation layer pattern,

Forming a mask pattern for selectively exposing the semiconductor substrate, forming a trench for device isolation using the mask pattern as an etch mask, and forming an insulation layer for device isolation filling the trench for device isolation, and then forming the mask pattern And forming a preliminary device isolation layer pattern by planarizing the isolation layer to expose the device isolation layer, and removing the mask pattern to form a device isolation layer pattern protruding above the substrate surface.

According to an embodiment of the present invention, the forming of the active region may include forming a spacer on sidewalls of the device isolation layer pattern portion protruding onto the substrate, and using the spacer and the device isolation layer pattern as an etching mask. Selectively etching a surface portion of the substrate.

The forming of the preliminary floating gate pattern may include depositing a conductive layer on the tunnel oxide layer to fill a gap between an active trench of the active region and the device isolation layer pattern. Planarizing the conductive layer to expose the top surface of the device isolation layer pattern to form a preliminary conductive layer pattern, and partially removing the device isolation layer pattern to expose the upper sidewall of the preliminary conductive layer pattern.

According to an embodiment of the present invention, after forming the active region, the method may further include oxidizing the active region to round the corner portion formed by the active trench.

According to an embodiment of the present invention, the oxidation treatment may include radical oxidation.

According to an embodiment of the present invention, after the oxidation treatment, the method may further include cleaning the inside of the active trench.

Since the active trench is included in the active region, the effective width of the active region is increased. Accordingly, in the nonvolatile memory device, F-N tunneling may be sufficiently generated as the contact area between the floating gate pattern and the active region is increased. As a result, the operating characteristics of the nonvolatile memory device can be improved.

In addition, the gate effective width of the gate of the transistor formed on the active region having the increased effective width is increased. Therefore, it is possible to increase the current at the time of transistor operation, thereby increasing the operation speed of the semiconductor device.

Hereinafter, a method of manufacturing a nonvolatile memory device in accordance with a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, and the general knowledge in the art. Those skilled in the art can implement the present invention in various other forms without departing from the technical spirit of the present invention. In the accompanying drawings, the dimensions of the substrates, layers (films), regions, pads, patterns or structures are shown in greater detail than actual for clarity of the invention. In the present invention, each layer (film), region, pad, pattern or structures is formed to be "on", "top" or "bottom" of the substrate, each layer (film), region, pad or patterns. When mentioned, each layer (film), region, pad, pattern or structure is meant to be directly formed over or below the substrate, each layer (film), region, pad or patterns, or other layers (film), Other regions, different pads, different patterns or other structures may be additionally formed on the substrate. Further, where each layer (film), region, pad, pattern or structure is referred to as "first", "second" and / or "third", it is not intended to limit these members but only each layer (film ), Areas, pads, patterns or structures. Thus, "first", "second" and / or "third" may be used selectively or interchangeably for each layer (film), region, pad, pattern or structures, respectively.

1 to 9 are cross-sectional views and perspective views illustrating a method of forming a nonvolatile memory device in accordance with an embodiment of the present invention.

Referring to FIG. 1, a buffer oxide layer (not shown) is formed on a semiconductor substrate 100, and a first hard mask pattern 102 is formed on the buffer oxide layer to selectively mask an active region. The first hard mask pattern 102 is provided as an etching mask for forming a trench for device isolation. The first hard mask pattern 102 may be formed using silicon nitride. The first hard mask pattern 102 has a line shape extending in a first direction.

The first hard mask layer pattern 102 defines a gap region for forming a floating gate electrode in a subsequent process.

By selectively etching the exposed buffer oxide layer and the substrate 100 by using the first hard mask layer pattern 102 as an etch mask, a trench 104 for device isolation is formed.

Referring to FIG. 2, a trench inner wall oxide film (not shown) is formed in the device isolation trench 104 to cure etch damage.

An isolation layer (not shown) is deposited on the trench inner wall oxide layer and the first hard mask pattern 102 to completely fill the inside of the isolation trench 104. The device isolation insulating film may be formed by depositing an oxide such as TEOS, USG, SOG, or HDP-CVD.

Next, the device isolation layer is planarized to expose the first hard mask pattern 102 by a chemical mechanical polishing process, thereby forming a preliminary device isolation layer pattern 106.

The surface of the substrate 100 is exposed by removing the exposed first hard mask pattern 102 and the buffer oxide layer. By removing the first hard mask pattern 102, a gap is formed between the preliminary device isolation layer patterns 106. The process of removing the first hard mask pattern 102 may be accomplished by a wet etching process using phosphoric acid.

Referring to FIG. 3, an insulating layer for spacers (not shown) are continuously formed on the top surface and sidewalls of the preliminary isolation layer pattern 106 and the exposed substrate. In other words, the spacer insulating film should not completely fill the gap between the preliminary device isolation layer patterns 106. To this end, the spacer insulating film may be formed to a thickness thinner than 1/2 of the width of the exposed substrate. The spacer insulating layer may be formed by depositing silicon nitride.

The insulating film for the spacer is converted into a spacer in a subsequent process to serve as a mask for etching the substrate. Therefore, it is desirable to have a thickness in a suitable range that can be used as a mask for etching the substrate. If the thickness of the spacer insulating film is too low, it is difficult to perform a function as a mask. If the thickness of the spacer insulating film is too thick, the spacer insulating film completely fills the gap between the preliminary device isolation layers.

The spacer insulating film may be formed to a thickness of about 100 to about 500 microseconds, depending on the width of the gap portion. Preferably, the spacer insulating film may be formed to a thickness of about 200 to 400 kPa.

Next, the spacer insulation layer may be formed on the exposed sidewall of the preliminary isolation layer pattern 106 by anisotropically etching the spacer insulation layer to expose the substrate surface. The spacer 108 formed by the above process is then provided as an etch mask pattern for etching the center portion of the substrate.

The spacer 108 preferably has a height in a suitable range that can be used as a mask for etching the substrate. If the height of the spacer 108 is low, the spacers 108 may be exhausted during the anisotropic etching, and thus the spacer 108 may not function as a mask. The spacer 108 may vary depending on the etching depth of the substrate, but may be formed to have a height of at least 500 μs.

The thickness of the preliminary device isolation layer pattern 106 is substantially similar to the thickness of the first hard mask pattern 102. However, since the first hard mask pattern 102 has a height of at least 500 GPa, the upper sidewall of the preliminary device isolation layer pattern 106 may be at least 500 GPa or more. Therefore, the spacer 108 may be formed to have a height of 500 kV or more, which is a height sufficient to provide an etching mask pattern.

Referring to FIG. 4, the active region is completed by forming the active trench 110 in the center portion of the substrate by etching the exposed portion of the substrate using the spacer 108 as an etching mask. The active region may be formed such that an edge portion adjacent to the preliminary device isolation layer pattern 106 is protruded more than a center portion where the active trench 110 is formed.

Since the active trench 110 is formed in the active region formed by the method of the present invention, the active effective width is increased as compared with the conventional active region having a flat top surface.

Referring to FIG. 5, the active trench 110 is oxidized to round the lower edge of the active trench 110.

The oxidation treatment includes radical oxidation using radicals (O *), dry oxidation using oxygen (O ₂ ), clean oxidation using hydrogen chloride (HCl) in the dry oxidation, and water vapor. Wet oxidation using (H ₂ O) or an annealing (anneal) method of NO and N ₂ O atmosphere.

The oxidation process according to an embodiment of the present invention may use a radical oxidation process that proceeds at a temperature lower than that of conventional wet oxidation or dry oxidation.

Specifically, the radical oxidation process includes introducing a reaction gas containing oxygen and hydrogen and exciting the reaction gas in a plasma state. In addition, in order to excite the reaction gas into a plasma state, a power of about 1,000 W to about 5,000 W is applied under a pressure of about 1 mTorr to 10 Torr. The radical oxidation process uses oxygen radicals having a higher kinetic energy than gaseous oxygen and a relatively low activation energy, and a temperature lower than that of conventional wet oxidation or dry oxidation at about 800 ° C. Phosphorus reaction can be induced at about 350 to 650 ° C.

After performing the oxidation treatment, a process of cleaning the inside of the active trench 110 may be performed. The cleaning liquid used in the cleaning process may be a fluorine (HF) aqueous solution or SC1, and a portion of the film made of an oxide may be removed by the cleaning.

An active trench 110a having a rounded lower edge is formed by the oxidation process, and a profile of an edge of the floating gate (FIGS. 7 and 114) formed in a subsequent process on the active trench is formed in a round shape. Therefore, concentration of the electric field which has occurred conventionally can be alleviated.

Referring to FIG. 6, the entire surface of the active region is exposed by selectively removing the spacer 108. The process of removing the spacer 108 may be performed through a wet etching process using phosphoric acid.

When the spacer 108 is removed, a gap portion for forming a floating gate pattern is completed between the preliminary isolation layers.

Optionally, a process of partially removing sidewalls of the preliminary isolation layer pattern 106 exposed as the spacer 108 is removed may be further performed. As a result, it is possible to suppress the occurrence of voids or seams in the first conductive film embedded in the gap.

In addition, a process of partially etching the preliminary device isolation layer pattern 106 may be further performed to lower the height of the preliminary device isolation layer pattern 106. Specifically, the preliminary device isolation layer pattern 106 may be etched through a wet etching process using a hydrofluoric acid (HF) diluent.

Referring to FIG. 7, a tunnel oxide layer 112 is formed on the exposed active region. The tunnel oxide layer 112 may be formed by performing a thermal oxidation process. The thickness of the tunnel oxide film 112 varies depending on the characteristics of the transistor to be formed, but may generally be formed in a range of 50 to 200 kV.

Next, a first conductive film (not shown) is formed on the preliminary device isolation layer pattern 106 while completely filling the gap between the preliminary device isolation layer patterns 106. The first conductive layer may be formed using a polysilicon material doped with impurities.

The preliminary floating gate pattern 114 is formed by planarizing the first conductive layer to expose the top surface of the preliminary isolation layer pattern 106 by a chemical mechanical polishing process.

Referring to FIG. 8, the device isolation layer pattern 106a is completed by partially etching the preliminary device isolation layer pattern 106 to partially expose the upper sidewall of the preliminary floating gate pattern 114.

9, a dielectric film (not shown) is formed on the preliminary floating gate pattern 114.

The dielectric film may be formed by stacking silicon oxide / silicon nitride / silicon oxide.

Alternatively, the dielectric film may be formed by stacking a metal oxide having a high dielectric constant. Examples of metal oxides that can be used include HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , Y ₂ O ₃ , Nb ₂ O ₅ , Al ₂ O ₃ , TiO ₂ , CeO ₂ , In ₂ O ₃ , RuO ₂ , MgO, SrO , B ₂ O ₃ , SnO ₂ , PbO, PbO ₂ , Pb ₃ O ₄ , V ₂ O ₃ , La ₂ O ₃ , Pr ₂ O ₃ , Sb ₂ O ₃ , Sb ₂ O ₅ , CaO and the like. . It is preferable to use these independently, and if necessary, you may laminate | stack two or more.

For example, the dielectric film may be formed by sequentially stacking a thin film made of a silicon oxide film, a silicon nitride film, and a material having a high dielectric constant.

A second conductive film (not shown) is formed on the dielectric film. The second conductive layer may be formed by depositing a doped polysilicon or metal material. A second hard mask layer pattern 120 is formed on the second conductive layer to pattern the control gate. The second hard mask pattern has a line shape extending in a second direction perpendicular to the first direction.

Subsequently, the second conductive layer, the dielectric layer, and the preliminary floating gate pattern 114 are sequentially etched using the second hard mask layer pattern 120 as an etching mask, thereby forming the floating gate pattern 114a and the dielectric layer pattern ( 116 and the control gate pattern 118 are formed. The floating gate pattern 114a has an isolated shape on the active region, and the control gate pattern 118 has a line shape perpendicular to the active region.

As described above, according to the present invention, it is possible to manufacture a nonvolatile memory device capable of increasing the effective area of the active region to improve operating characteristics.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (7)

Forming an isolation pattern on the semiconductor substrate; Forming an active region having an active trench by partially etching the substrate surface defined by the device isolation pattern; Continuously forming a tunnel oxide film on the surface of the active region; Forming a preliminary floating gate pattern filling the active trench on the tunnel oxide layer; Forming a dielectric layer on the preliminary floating gate pattern; Forming a conductive film for a control gate on the dielectric film; And And sequentially etching the control gate conductive layer, the dielectric layer, and the preliminary floating gate pattern to form the control gate pattern, the dielectric layer pattern, and the floating gate pattern. The method of claim 1, wherein forming the device isolation layer pattern comprises: Forming a mask pattern to selectively expose the semiconductor substrate; Forming a trench for device isolation using the mask pattern as an etch mask; Forming a device isolation insulating film filling an inside of the device isolation trench; Forming a preliminary isolation layer pattern by planarizing the isolation layer for exposing the device to expose the mask pattern; And And removing the mask pattern to form a device isolation pattern that protrudes above the surface of the substrate. The method of claim 2, wherein the forming of the active region comprises: Forming a spacer on sidewalls of the device isolation layer pattern portion protruding onto the substrate; And And selectively etching a surface portion of the substrate using the spacer and the device isolation layer pattern as an etching mask. The method of claim 1, wherein the forming of the preliminary floating gate pattern comprises: Depositing a conductive film on the tunnel oxide film to fill a gap between an active trench of the active region and the device isolation pattern; Forming a preliminary conductive layer pattern by planarizing the conductive layer to expose an upper surface of the device isolation layer pattern; And And partially removing the device isolation layer pattern such that an upper sidewall of the preliminary conductive layer pattern is exposed. The method of claim 1, wherein after forming the active region, And oxidizing the active region to round the corner portion formed by the active trench. The method of manufacturing a nonvolatile memory device according to claim 5, wherein the oxidation treatment includes radical oxidation. 6. The method of claim 5, further comprising removing the oxidized surface portion of the active trench by the oxidation treatment.

Images