KR20080008546A - Semiconductor device having fuses and fuse cutting method thereof - Google Patents

Abstract

A semiconductor device having a fuse and a method for cutting the fuse of the semiconductor device are provided to reduce the manufacturing time of the semiconductor device by reducing laser radiation time required for the cutting of the fuse. A semiconductor device having a fuse is prepared. The fuse includes a first line pattern, an insulation film(120), and a second line pattern. The first line pattern used as low fuses(130') is formed on a substrate(100). The insulation film is formed on the substrate having the first line pattern. The second line pattern used as upper fuses(160') is formed on the insulation film. By radiating laser beams on the upper fuses, the upper and lower fuses are sequentially cut off.

Description

Semiconductor device having fuses and a method for cutting fuses thereof {ofSemiconductor Device having Fuses and Fuse Cutting Method Thereof}

1 to 3 are plan views showing fuses of a conventional semiconductor device;

4 is an SEM plane photograph showing a disconnection failure of a fuse when the energy of the irradiated laser is low;

5 to 10 are cross-sectional views for explaining a step of preparing a semiconductor device having a fuse according to an embodiment of the present invention;

11 and 12 are conceptual views illustrating sequentially cutting the upper fuse and the lower fuse by irradiating a laser beam onto the upper fuse.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device having a fuse and a method of cutting the fuse thereof.

In the semiconductor device, a repair process refers to a process of replacing a function of a unit cell in which a preliminarily prepared circuit is operated when a unit cell does not operate normally due to a defect generated in a memory cell during a process. . For example, in the case of electrical short-circuit between particles by in-line, this repair process is essential because it is very difficult to eliminate 100% of the causes, which directly affects the yield in the wafer. do.

The repair method is an electric fuse method that melts and blows a fuse by overcurrent, and burns the fuse with a laser beam. Among these methods, a method of disconnecting a fuse using a laser is frequently used due to its simple, efficient and easy layout. .

 In the repair process, which is performed by irradiating a laser and disconnecting a part of a predetermined wire, a wire disconnected is called a fuse. Since a blown fuse blocks current, low conductivity (for example, non-conductivity) is prevented. The state is switched.

1 shows a fuse part 10 having a plurality of fuses 2, 4, 6, 8. The plurality of fuses 2, 4, 6, 8 are in a non-disconnected state, that is, in a conductive state.

2, the fuse 4 is disconnected by irradiating a laser to block a current flowing through the fuse 4. The blown fuse 4 and adjacent fuses 2, 6 are located very close by the wavelength and spot size of a given laser beam. As a result, adjacent fuses 2 and 6 are inadvertently disconnected or cut off during the fuse 4 disconnection process, resulting in a defect in the semiconductor device, a link with an adjacent region, or at least an adjacent fuse 2, 6. ) May cause serious physical damage. In addition, cracks 11 due to stress caused by laser energy may be generated from the fuses 4 and cause damage to adjacent fuses 2 and 6.

Accordingly, a number of methods have been proposed for protecting fuses so as not to affect adjacent fuses upon fuse break. Initially, this problem is solved by maintaining a sufficient distance between fuses in order to prevent damage to adjacent circuit elements or other fuses that occur during disconnection. However, as semiconductor devices become increasingly integrated, the tight pitch between fuses is required, and this method is reaching its limit.

In addition, there may be a method by an additional structure as another method for protecting the fuse so as not to affect the adjacent fuse at the time of fuse break. 3 shows a fuse part 20 composed of a plurality of fuses 12, 14, and 16. The additional structures 23 and 25 are disposed between the fuses in the fuse part 20. The additional structures 23 and 25 are typically made of a barrier material such as tungsten (W) or molybdenum (Mo) to act as crack stops when the fuse 14 is disconnected by a laser. Thus, the cracks 21 generate from the fuse 14 and are prevented in the additional structures 23 and 25.

However, this method basically has a problem of increasing the chip area due to the increase in the pitch interval due to the addition of the crack blocking structure. And crack-blocking structures introduced between fuses are not applied at tight pitches. The reason is that the crack blocking structure itself is sputtered by the laser, causing damage to the adjacent fuses or subsequent circuit elements.

Figure 4 is a photograph showing the disconnection of the fuse when the energy of the laser irradiated is low. That is, the narrower the pitch size of the fuses 41 and 42, the lower the energy of the irradiated laser can be used to reduce the influence on the adjacent fuses. However, in this case, the fuses 41 and 42 are not completely disconnected, so the fuse Residues 41 'and 42' may remain.

Therefore, when irradiating a laser beam to disconnect a selected fuse in a semiconductor device having a high density of components per unit area, it is necessary to efficiently arrange fuses without damaging adjacent fuses.

In addition, in a semiconductor device having a high density of components per unit area, the density in which fuses are arranged is increased. For example, in order to disconnect two fuses, a laser beam must be irradiated to each fuse. When there are thousands of tens of thousands of fuses on a wafer for manufacturing a semiconductor device, it may take a long time to irradiate a laser beam, which may be a great burden for the semiconductor device manufacturing process. Therefore, there is a need for a fuse cutting method that shortens the time for irradiating a laser beam for disconnection of fuses.

The technical problem to be achieved by the present invention is a semiconductor device having a fuse for efficiently placing fuses without damaging adjacent fuses when irradiating a laser to disconnect the selected fuse in a semiconductor device having a high density of components per unit area. To provide.

Another object of the present invention is to provide a fuse cutting method of a semiconductor device having the fuse, which can shorten the laser irradiation time for disconnection of the fuse.

In order to achieve the above technical problem, a fuse cutting method of a semiconductor device having a fuse according to an embodiment of the present invention includes: a first wiring pattern to be used as lower fuses on a substrate; An insulating film formed on the substrate including the first wiring pattern; And preparing a semiconductor device including a fuse on the insulating layer, the fuse including a second wiring pattern to be used as upper fuses. And sequentially cutting the upper fuse and the lower fuse by irradiating a laser beam on the upper fuse.

In the fuse cutting method of a semiconductor device with a fuse of the present invention, the step of sequentially cutting is preferably to cut the upper fuse and the lower fuse sequentially by irradiating the laser beam on the upper fuse once. Do.

In the semiconductor device with a fuse of the present invention for achieving the another technical problem, a first wiring pattern to be used as the lower fuses on the substrate; An insulating film formed on the substrate including the first wiring pattern; And a second wiring pattern to be used as upper fuses on the insulating layer, wherein the upper fuses have a structure in which an upper surface thereof is directly exposed to the atmosphere.

In the semiconductor device with a fuse of the present invention, each of the lower fuses, when viewed on the substrate, while being positioned to be positioned directly under each of the upper fuses or not directly below, It is preferable that the upper fuses are arranged side by side.

In the semiconductor device having a fuse of the present invention, the first wiring pattern is preferably a word line or a bit line, and the second wiring pattern is preferably a metal wiring.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. Throughout the specification, when referring to one component, such as a film, region, or substrate, being "on" another component, the component is in direct contact with or intervening with another component. It can be interpreted that elements may exist.

5 to 10 are cross-sectional views illustrating a step of preparing a semiconductor device having a fuse according to an embodiment of the present invention.

Referring to FIG. 5, an interlayer insulating film 120 is formed on a substrate 100 to insulate the substrate 100 and a structure to be formed thereon. For example, after the device isolation layer 110 is formed on the substrate 100, the gate electrode 111, the source 112, and the drain 113 region of the transistor are formed, and the interlayer insulating layer 120 is formed on the substrate ( 100) can be formed on the front surface. The interlayer insulating layer 120 may include at least one single layer selected from boron phosphorous silicate glass (BPSG), phosphorous silicate glass (PSG), spin on glass (SOG), tetra ethyl ortho silicate (TEOS), and undoped silicate glass (USG). Or these composite films. Of course, it may be formed by depositing an insulator such as silicon nitride.

Next, referring to FIG. 6, after forming the contact hole exposing the drain region by etching the first interlayer insulating layer 120, a conductive material such as polycrystalline silicon, metal silicide, metal or polycrystalline silicon and metal doped with impurities The contact layer 135 and the first wiring pattern 130 are formed by depositing and patterning a layer of silicide.

That is, the first wiring pattern 130 to be used as the lower fuses 130 ′ is formed on the interlayer insulating layer 120. For example, some of the first wiring patterns 130 may be bit lines 130 ″. In other words, some of the first wiring patterns 130 may be formed on the bit lines 130 ″ in the semiconductor device. The other part of the first wiring pattern 130 may serve as the lower fuses 130 ′. In this case, the first wiring pattern 130 may be formed of polycrystalline silicon, metal (ex, tungsten or molybdenum, etc.), conductive metal nitride (ex, titanium nitride or tantalum nitride, etc.) and metal silicide (ex, tungsten silicide, cobalt silicide, etc.). It can be formed including at least one single film or a composite film thereof selected from among. In addition, a barrier metal layer may be formed under the formed material layer. In this case, the deposition of the material film may be performed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The lower fuse 130 may be formed while forming the bit line 130 ″, which is a part of the first wiring pattern 130, and at the same time, the lower fuse 130 ′, which is another part of the first wiring pattern 130, may be formed on the interlayer insulating layer. The materials forming ') may be the same as the materials forming bitline 130 ″.

Although not shown in the drawing, the first wiring pattern may be a word line, and according to design intention, the lower fuses may be formed on the interlayer insulating layer while forming the word line. Also in this case, the first wiring pattern is selected from polycrystalline silicon, metal (ex, tungsten or molybdenum, etc.), conductive metal nitride (ex, titanium nitride or tantalum nitride, etc.) and metal silicide (ex, tungsten silicide, cobalt silicide, etc.). At least one single film or a composite film thereof may be included, and a barrier metal layer may be formed under the formed material film. The deposition of the material film may be performed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Since the lower fuses may be formed on the interlayer insulating layer while forming the word line, the materials forming the lower fuses may be the same as the materials forming the word line.

Of course, the wiring pattern to be used as the fuse may be implemented in various types of patterns instead of line types according to design intention.

Referring to FIG. 7, after forming the first wiring pattern, the insulating layer 140 is formed on the substrate 100 including the first wiring pattern. The insulating layer 140 may include at least one single layer selected from boron phosphorous silicate glass (BPSG), phosphorous silicate glass (PSG), spin on glass (SOG), tetra ethyl ortho silicate (TEOS), and undoped silicate glass (USG) film. These composite films can be formed. Of course, the insulating layer 140 may be formed of a plurality of layers selected from the group consisting of the above combinations, rather than a single layer. For example, when the insulating film 140 ′ is deposited after the bit line 130 ″ is formed, the insulating film 140 ′ may be formed of a plurality of layers including a BPSG film layer and a TEOS film layer. In the case of forming the 157, an insulating film 140 ″ having a height equal to or higher than the level of the capacitor 157 may be further formed. Referring to the formation of the capacitor 157 in detail, first, a contact hole exposing the source region 112 is formed by etching the insulating layer 140 ′. A conductive material such as polycrystalline silicon doped with impurities is deposited in the contact hole to form a contact plug, and then a capacitor lower electrode 150 is formed thereon. Although the lower electrode 150 is illustrated in a simple stack form in the drawing, it may be formed in various shapes such as a cylindrical shape and a fin shape, and hemispherical grains may be formed on the surface thereof. The dielectric layer 153 is formed over the lower electrode 150, and a conductive material such as polycrystalline silicon doped with impurities is deposited thereon to form an upper electrode layer. Subsequently, the upper electrode layer is patterned to form the upper electrode 155. For ease of understanding, while the bit line 130 " and the lower electrode contact 136 are shown simultaneously in cross section, the lower electrode contact 136 is on a different plane than the bit line 130 " I don't meet

Referring to FIG. 8, a second wiring pattern 160 to be used as the upper fuses 160 ′ is formed on the insulating layer 140. That is, some of the second wiring patterns 160 may serve as the metal wiring 160 ″, and another portion of the second wiring patterns 160 may serve as the upper fuse 160 ′. The upper fuses 160 ′ may be formed on the insulating layer 140 while the wiring 160 ″ is formed. In this case, the second wiring pattern 160 may include any one of aluminum and copper, and a barrier metal layer may be formed under the second wiring pattern 160. In this case, the deposition of the material film may be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or electroplating.

As described above, the prior art has a limitation in fuse arrangement in a high density semiconductor device in which the fuse pitch for the repair process is composed of only one layer, so that the fuse pitch size becomes small. However, according to the semiconductor device having a fuse and a method of manufacturing the same according to the present invention, since the fuses are arranged in a plurality of layers, the ratio of the area of the fuses to the total area of the given semiconductor device can be lowered. It is possible to effectively manufacture high-density semiconductor devices.

Meanwhile, referring to FIG. 8, when viewed on the substrate 100, each of the lower fuses 130 ′ is positioned directly under each of the upper fuses 160 ′, and the upper fuses 160 ′. ) Can be arranged side by side. Meanwhile, according to the design intention of the semiconductor device, as shown in FIG. 9, when viewed on the substrate 100, each of the lower fuses 130 ′ is positioned directly below each of the upper fuses 160 ′. It may be arranged side by side with the upper fuses 160 ′ while being offset from each other.

Referring back to FIG. 8, after forming the second wiring pattern 160, an inter-wire insulating layer 170 may be formed on the substrate 100 including the second wiring pattern 160. Subsequently, a passivation layer 180 is formed on the entire surface of the substrate 100 including the second wiring pattern 160 and the interwire insulating layer 170. The step of forming the passivation film 180 is a final process of chip fabrication, which uses a dielectric and buffer coating to prevent the chip from scratching or moisture penetration. The passivation film 180 is preferably made of a silicon nitride film, a silicon oxide film, or a composite film having good moisture resistance. This film quality serves to protect the internal semiconductor devices by absorbing mechanical, electrical or chemical shocks to the underlying structure in the subsequent assembly or packaging process.

Depending on the semiconductor device, the second wiring pattern 160, which will also be used as the upper fuses 160 ′, may be located deep from the top of the semiconductor device. If there is a thick film (eg, insulating film 170 or passivation film 180) on the upper fuse 160 ', a large portion of the energy of the laser irradiated to cut the fuse is absorbed by the film itself. As a result, the laser must be irradiated in large quantities for a long time in order to break the fuse, which may have an undesirable effect on the adjacent fuse.

Accordingly, as illustrated in FIG. 10, it is preferable to form the fuse opening 190 to etch the passivation layer 180 and / or the interlayer insulating layer 170 to expose the top surface of the upper fuses 160 ′ to the atmosphere. Meanwhile, some of the second wiring patterns 160, which are also used as the upper fuses 160 ′, serve as the metal wires 160 ″, and may be formed of, for example, aluminum. Used as the metal wires 160 ″. The aluminum film is usually a thickness of 2000 ~ 6000 는데 This thickness is not preferable because it is thick for the upper fuse (160 '). That is, since the laser must be irradiated in a large amount for a long time in order to disconnect the thick upper fuse 160 ′, it may have an undesirable effect on the adjacent fuse. Therefore, after the fuse opening 190 is formed, the fuse may be etched from an upper surface of the upper fuse 160 ′ to lower the overall thickness of the upper fuse 160 ′ or to form a groove. The depth of the groove may be adjusted and formed as necessary. In some cases, the groove may be formed to penetrate the upper fuse 160 ′. In order to etch from the upper surface of the upper fuse 160 ′, wet etching may be used. However, in the case of forming a highly integrated semiconductor device, it is preferable to use anisotropic dry etching to further control the etching degree. The etching gas is mainly a mixture of oxygen, argon and the like in a gas containing chlorine (Cl), fluorine (F), etc. according to the etching purpose, and may be used by forming a plasma to increase the activity.

A first wiring pattern to be used as lower fuses on a substrate so far; An insulating film formed on the substrate including the first wiring pattern; And preparing a semiconductor device including a fuse including a second wiring pattern to be used as upper fuses on the insulating film. Subsequently, a laser beam is irradiated onto the upper fuse to form the upper fuse and the lower fuse. A step of sequentially cutting the fuse will be described.

In the prior art, since the fuses are composed of one layer, for example, the disconnection of two fuses requires irradiation of the laser beam twice. In contrast, according to the present invention, the upper fuse 160 'and the lower fuse 130' are arranged in two layers, and the upper fuse 160 'and the lower fuse (by irradiating a laser beam on the upper fuse only once) 130 ') can be cut sequentially, it can be expected to reduce the laser irradiation time, thereby reducing the time required to manufacture semiconductor elements. In other words, when there are thousands to tens of thousands of fuses on a wafer for manufacturing a semiconductor device, shortening the laser irradiation time is effective in the semiconductor device manufacturing process.

FIG. 11 is a conceptual diagram illustrating sequentially cutting the upper fuse and the lower fuse by irradiating a laser beam onto the upper fuse.

Referring to FIG. 11, each of the lower fuses 130 ′ is positioned directly below each of the upper fuses 160 ′ and arranged in parallel with the upper fuses 160 ′, and the laser beam 200 ) Is irradiated onto the upper fuse to sequentially cut the upper fuse and the lower fuse in the area indicated by the dotted line formed by the diameter of the spot of the laser beam.

In fact, each of the lower fuses 130 ′ is positioned directly below each of the upper fuses 160 ′ and arranged in parallel with the upper fuses 160 ′ and irradiated with a laser beam once. After the experiment to confirm the cutting of the upper fuse and the lower fuse was confirmed that not only the upper fuse but also the lower fuse in a specific energy range, it was confirmed that there is no undesirable effect on the fuse adjacent to the fuse to be disconnected. Could.

12 is a conceptual diagram illustrating sequentially cutting the upper fuse and the lower fuse by irradiating a laser beam onto the upper fuse. Referring to FIG. 13, each of the lower fuses 130 ′ is arranged side by side with the upper fuses 160 ′ while being offset from each other without being located directly below each of the upper fuses 160 ′. The laser beam 200 is irradiated onto the upper fuse 160 ′ to sequentially cut the upper fuse and the lower fuse in the area indicated by the dotted line formed by the diameter of the spot of the laser beam.

In fact, each of the lower fuses 130 ′ is not located directly below each of the upper fuses 160 ′, but is disposed to be parallel to the upper fuses 160 ′ while being offset to each other. After examining once and confirming whether the upper fuse and the lower fuse in the experiment it was confirmed that not only the upper fuse but also the lower fuse in a specific energy range.

The foregoing description of specific embodiments of the invention has been presented for purposes of illustration and description. Therefore, the present invention is not limited to the above embodiments, and various modifications and changes are possible in the technical spirit of the present invention by combining the above embodiments by those skilled in the art. It is obvious.

According to the semiconductor device with a fuse according to the present invention, it is possible to lower the ratio of the area occupied by the fuses in the total area of a given semiconductor device, thereby making it possible to manufacture a high-density semiconductor device more effectively. In addition, the upper surface of the upper fuse has a structure that is directly exposed to the atmosphere it is possible to cut the upper fuse and the lower fuse by a low energy laser beam.

In addition, according to the fuse cutting method according to the present invention, it is possible to shorten the laser irradiation time for disconnection of the fuse, thereby reducing the time required to manufacture the semiconductor device.

Claims (14)

A first wiring pattern to be used as lower fuses on the substrate; An insulating film formed on the substrate including the first wiring pattern; And preparing a semiconductor device including a fuse on the insulating layer, the fuse including a second wiring pattern to be used as upper fuses. And And a step of sequentially cutting the upper fuse and the lower fuse by irradiating a laser beam onto the upper fuse. The semiconductor device according to claim 1, wherein each of the lower fuses is disposed in parallel with the upper fuses while being positioned directly under each of the upper fuses when viewed on the substrate. Fuse cutting method of device. The fuse of claim 1, wherein each of the lower fuses is arranged side by side with the upper fuses while being offset from each other, instead of being located directly below each of the upper fuses when viewed on the substrate. Fuse cutting method of a semiconductor device provided with. The fuse of claim 1, wherein the sequentially cutting comprises sequentially cutting the upper fuse and the lower fuse by irradiating the laser beam onto the upper fuse once. Cutting method. The fuse cutting method of claim 1, wherein a portion of the first wiring pattern is a bit line or a word line. The fuse cutting method of claim 1, wherein some of the second wiring patterns are metal wirings. The fuse cutting method of claim 1, wherein the upper fuses have a structure in which an upper surface thereof is not directly covered by a passivation layer and is directly exposed to the atmosphere. The semiconductor device of claim 5, wherein the first wiring pattern comprises at least one single film selected from polycrystalline silicon, metal, conductive metal nitride, and metal silicide or a composite film thereof. How to cut fuse. The fuse cutting method of claim 6, wherein the second wiring pattern comprises any one of aluminum and copper. A first wiring pattern to be used as lower fuses on the substrate; An insulating film formed on the substrate including the first wiring pattern; And A second wiring pattern to be used as upper fuses on the insulating film, The upper fuses of the semiconductor device having a fuse, characterized in that the upper surface is directly exposed to the atmosphere. The semiconductor of claim 10, wherein each of the lower fuses is disposed in parallel with the upper fuses while being positioned directly below each of the upper fuses when viewed on the substrate. device. The fuse of claim 10, wherein each of the lower fuses is arranged side by side with the upper fuses while being offset from each other and not positioned directly below each of the upper fuses when viewed on the substrate. Semiconductor device provided with. The semiconductor device of claim 10, wherein a portion of the first wiring pattern is a bit line or a word line. The semiconductor device of claim 10, wherein some of the second wiring patterns are metal wirings.

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