KR20080002539A - Method for fabricating poly-silicon thin film transistors array substrate and method for fabricating liquid crystal display device by applying said - Google Patents

Abstract

A method for manufacturing a polysilicon TFT(Thin Film Transistor) and a method for manufacturing an LCD(Liquid Crystal Display) device by using the same are provided to enable a metal layer to perform simultaneously a mask role for etching an amorphous silicon layer and a catalyst role for crystallizing the amorphous silicon layer in forming the metal layer in a predetermined of the upper part of the amorphous silicon layer, thereby simplifying the process. A method for manufacturing a polysilicon TFT comprises the following steps of: forming an amorphous silicon layer on a substrate(111); forming a first self alignment layer in a predetermined portion of the upper part of the amorphous silicon layer; forming a first metal layer on the amorphous silicon layer exposed between the first self alignment layer; removing the first self alignment layer; etching the amorphous silicon layer by using the first metal layer as a mask and forming a semiconductor layer(114a); crystallizing the amorphous silicon layer by using the first metal layer as a catalyst; forming separately source and drain electrodes(115a,115b) in both sides of the polysilicon layer; forming a gate insulating layer(113) in the front of the substrate including the source and drain electrodes; and forming a gate electrode(112a) on the gate insulating layer between the source and drain electrodes.

Description

Method for manufacturing polysilicon thin film transistor and method for manufacturing liquid crystal display device using the same {Method For Fabricating Poly-Silicon Thin Film Transistors Array Substrate And Method For Fabricating Liquid Crystal Display Device By Applying Said}

1 is a process cross-sectional view of a polysilicon thin film transistor array substrate according to the prior art.

Figure 2a to 2m is a process cross-sectional view of a polysilicon thin film transistor according to the present invention.

3A to 3K are cross-sectional views of a polysilicon thin film transistor array substrate according to the present invention.

* Explanation of symbols on the main parts of the drawings

111 substrate 112a gate electrode

113: gate insulating film 114: amorphous silicon layer

114a: semiconductor layer 115a: source electrode

115p: drain electrode 116: protective film

141: first metal layer 142: second metal layer

150, 153: Elastic Template Stamp

151, 152: first and second self-aligned layers

The present invention relates to a poly-silicon thin film transistor (Poly-Silicon Transistor) and a liquid crystal display device (LCD), in particular, to manufacture a polysilicon thin film transistor to simplify the process by minimizing the number of times the exposure mask is used. A method and a method of manufacturing a liquid crystal display device using the same.

Due to features such as low voltage driving, full color implementation, and light and small size, the active matrix liquid crystal display (AM-LCD) as a flat panel display device widely used in notebooks, personal digital assistants, TVs, aviation monitors, etc. is used as a switching element. Thin Film Transistor (TFT) is mainly used. The thin film transistor is composed of a polycrystalline silicon having a crystalline phase and a semiconductor film made of amorphous silicon (amorphous silicon: a-Si) depending on which silicon is used as the semiconductor layer. It can be classified into using a semiconductor film. As polycrystalline silicon, polysilicon (poly-Si) or microcrystalline silicon (μc-Si) is mainly known.

A semiconductor made of polycrystalline silicon has a feature that carrier mobility is about 10 to 100 times larger than a semiconductor made of amorphous silicon, and has excellent characteristics as a constituent material of a switching element.

In addition, since a thin film transistor using polycrystalline silicon as an active layer is capable of high speed operation, in recent years, various logic circuits such as complementary metal oxide semiconductor TFT (CMOS-TFT), erasable and programmable read only memory (EPROM), and EEPROM ( It is applied to Electrically Erasable and Programmable Read Only Memory (RAM), Random Access Memory (RAM), or as a switching device constituting a driving circuit such as a liquid crystal display device and an electroluminescent display device.

The liquid crystal display device includes a thin film transistor (TFT) for selectively applying a signal to the pixel electrode and a thin film having storage to maintain a state of charge until the unit pixel region is next addressed. A transistor array substrate, a color filter layer array substrate having a color filter layer for realizing color, a liquid crystal layer enclosed between the two substrates, and a driving circuit for driving the thin film transistor array substrate by various external signals. Display an image.

Hereinafter, a manufacturing method of a liquid crystal display device including a polysilicon thin film transistor according to the prior art will be described with reference to the accompanying drawings. Hereinafter, a method of manufacturing a thin film transistor array substrate of a liquid crystal display device will be described.

1 is a process cross-sectional view of a polysilicon thin film transistor array substrate according to the prior art.

First, as shown in FIG. 1A, a buffer layer 12 made of silicon oxide (SiO ₂ ) is formed on the entire surface of the insulating substrate 11 by a plasma enhanced chemical vapor deposition (PECVD) method. do.

Here, PECVD is a principle in which electrons excited by plasma collide with gaseous compounds introduced into a neutral state to decompose gaseous compounds, recombine with the help of the formed gas ions and thermal energy provided by glass to form a thin film. Will be used.

Thereafter, the polysilicon layer 22 is formed on the entire surface including the buffer layer 12 using plasma enhanced chemical vapor deposition.

Subsequently, as shown in FIG. 1B, the polysilicon layer 22 is patterned by a photoetch process using a first mask to form a semiconductor layer 13, and the inorganic material is formed on the entire surface of the semiconductor layer 13. SiO ₂ is deposited to form a gate insulating film 14.

Next, a low resistance metal layer is deposited on the gate insulating layer 14 and patterned by a photolithography process using a second mask to form a gate wiring having the gate electrode 15a in one direction.

The gate electrode 15a may be formed of a single metal layer such as aluminum or copper, or may be formed by stacking a metal such as molybdenum (Mo), tungsten (W), chromium (Cr), or platinum (Pt) on the aluminum layer. The metal layer is formed to overlap a predetermined portion of the semiconductor layer 13.

Next, as shown in FIG. 1C, source / drain regions 13a and 13b are formed by doping impurity ions into the semiconductor layer 13 using the gate electrode 15a as a mask. At this time, the semiconductor layer between the source region 1a and the drain region 13b where the impurity ions are not doped by the gate electrode 15a becomes the channel layer 13b.

Thereafter, as shown in FIG. 1D, an inorganic material SiO ₂ is deposited on the entire surface including the gate electrode 15a by chemical vapor deposition to form an interlayer insulating film 16.

In addition, the gate insulating layer 14 and the interlayer insulating layer 16 are etched to expose the source / drain regions 13a and 13b by a photolithography process using a third mask to form first contact holes 20a and 20b. do. In order to etch the gate insulating layer 14 and the interlayer insulating layer 16, dry etching is generally performed.

Thereafter, as shown in FIG. 1E, a low resistance metal layer is deposited on the interlayer insulating layer 16 and patterned by a photoetch process using a fourth mask to contact the source / drain regions 13a and 13b, respectively. The data line having the drain electrodes 17a and 17b is formed perpendicular to the gate line.

Here, the source / drain electrodes 17a and 17b may be formed of a single metal layer such as aluminum or copper, or a metal such as molybdenum (Mo), uranium (W), chromium (Cr), or platinum (Pt) on the aluminum layer. It is formed of a laminated double metal layer.

This completes the polysilicon thin film transistor composed of the active semiconductor layer 13, the gate electrode 15a, and the source / drain electrodes 17a and 17b using polysilicon.

Subsequently, the protective layer 18 is selectively removed to form the second contact hole 40 so that the drain electrode 17b is exposed by a photoetch process using a fifth mask, and the second contact hole 40 is formed. The pixel electrode 37 is formed in the pixel region so as to contact the drain electrode 17b through the pixel electrode 37. The pixel electrode is formed by depositing a transparent conductive material on the entire surface of the substrate and patterning the photoconductive process using a sixth mask.

However, the method of manufacturing a polysilicon thin film transistor array substrate according to the related art as described above includes at least six exposures in order to form a semiconductor layer, a gate wiring layer, a first contact hole, a data wiring layer, a second contact hole, and a pixel electrode. As a mask is used, as the number of times of use of the exposure mask increases, the process is complicated and the process time and process cost are high, so the process efficiency is greatly reduced.

In particular, since the exposure equipment is expensive equipment, researches to omit the process of using the exposure equipment have been continued in recent years.

The present invention has been made to solve the above problems, and after selectively depositing a metal by a self-aligned layer, patterning an amorphous silicon layer using the selectively deposited metal as a mask and using the metal at the same time It is an object of the present invention to provide a method of manufacturing a polysilicon thin film transistor to reduce the number of times of use of the exposure mask and simplify the process by crystallizing the amorphous silicon layer and a method of manufacturing a liquid crystal display device using the same.

Method of manufacturing a polysilicon thin film transistor of the present invention for achieving the above object comprises the steps of forming an amorphous silicon layer on a substrate, forming a first self-aligned layer on a predetermined portion of the amorphous silicon layer and Forming a first metal layer on the amorphous silicon layer exposed between the first self-aligned layer, removing the first self-aligned layer, and using the first metal layer as a mask to form the amorphous silicon layer. Etching to form a semiconductor layer, crystallizing the amorphous silicon layer using the first metal layer as a catalyst, forming source / drain electrodes on both sides of the polysilicon layer, and the source / drain electrodes Forming a gate insulating film on the entire surface including a gate electrode and a gate electrode on the gate insulating film between the source electrode and the drain electrode; Characterized in that it comprises a step of forming.

In this case, the first metal layer serves as a mask for etching the amorphous silicon layer and at the same time serves as a catalyst metal for crystallizing the amorphous silicon layer. Therefore, the first metal layer can be deposited by a CVD method, which is a low temperature process, and at the same time selects and uses a material that can be used as a catalyst metal when crystallizing the amorphous silicon layer. It is preferable to use metal materials such as copper, aluminum, and nickel. something to do.

The photolithography process may be used to form the gate electrode, but the gate electrode may be formed using a self-aligned layer to reduce the frequency of use of the exposure mask. In this case, since the gate electrode is not used as a catalyst metal for crystallizing the amorphous silicon layer, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), and chromium (Cr) are commonly used as wiring materials. , At least one of titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW) may be selected and formed.

Conventionally, in order to form a polysilicon thin film transistor, a total of four mask processes were performed to form a semiconductor layer, a gate electrode, a source / drain electrode, and a contact hole for contacting the semiconductor layer and the source / drain electrode. In the present invention, since the mask process only needs to be performed to form the source / drain electrodes, the number of mask processes can be greatly reduced.

On the other hand, the manufacturing method of the liquid crystal display device of the present invention for achieving the above object comprises the steps of forming an amorphous silicon layer on the substrate, forming a self-aligned layer on the upper portion of the amorphous silicon layer; Forming a metal layer on the amorphous silicon layer exposed between the self-aligning layers, removing the self-aligning layer, and etching the amorphous silicon layer using the metal layer as a mask to form a semiconductor layer; Crystallizing the amorphous silicon layer using the metal layer as a catalyst, forming source / drain electrodes on both sides of the polysilicon layer, and forming a gate insulating film on the entire surface including the source / drain electrodes; Forming a gate electrode on the gate insulating layer between the source electrode and the drain electrode; And forming a protective film on the entire surface including the pole, and forming a pixel electrode on the protective film and in contact with the drain electrode.

Here, a data line is formed simultaneously with the source / drain electrode, and a gate line defining a sub-pixel is formed to cross the data line simultaneously with the gate electrode.

In this case, the metal layer serves as a mask for etching the amorphous silicon layer and at the same time serves as a catalyst metal for crystallizing the amorphous silicon layer. Therefore, the metal layer can be deposited by a CVD method, which is a low temperature process, and at the same time selects and uses a material that can be used as a catalyst metal when crystallizing the amorphous silicon layer, and metal materials such as copper, aluminum, and nickel may be preferably used. .

The photolithography process may be used to form the gate electrode and the gate wiring, but the gate electrode may be formed using a self-aligned layer to reduce the frequency of use of the exposure mask. In this case, since the gate electrode and the gate wiring are not used as a catalyst metal for crystallizing the amorphous silicon layer, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), and chromium are commonly used as wiring materials. At least one of (Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW) may be selected and formed.

Conventionally, in order to construct a polysilicon thin film transistor array substrate of a liquid crystal display device, a semiconductor layer, a gate electrode, a source / drain electrode, a first contact hole, a pixel electrode, and the drain electrode for contacting the semiconductor layer and a source / drain electrode In order to form a second contact hole for contacting the pixel electrode, a total of six mask processes were performed. In the present invention, a contact hole for contacting the source electrode and the drain electrode, the pixel electrode, the drain electrode, and the pixel electrode is formed. In order to do this, only a total of three mask processes need to be performed, thereby greatly reducing the number of mask processes.

Hereinafter, a method of manufacturing a polysilicon thin film transistor and a method of manufacturing a liquid crystal display device using the same according to the present invention will be described in detail with reference to the accompanying drawings.

Method of manufacturing polysilicon thin film transistor

First, as shown in FIG. 2A, an amorphous silicon layer 114 is formed by depositing amorphous silicon on the entire surface of the substrate 111 by chemical vapor deposition or the like.

Specifically, the substrate 111 is introduced into a chemical vapor deposition (CVD) apparatus, and the amorphous silicon layer 114 is formed by depositing amorphous silicon (a-Si) to a thin thickness of about several tens of microseconds by chemical vapor deposition (CVD). Form. In this case, silane gas (SiH ₄ ) is used as the deposition gas, and argon gas (Ar) is used as the carrier gas, and the process is performed at an RF power of 100 to 500 W and a temperature of 430 to 500 ° C. . In order to deposit the amorphous silicon layer 114 to a thickness of 3000 Å, it is required to deposit for 800 seconds, so that the deposition time is appropriately adjusted according to the desired thickness.

At this time, a silicon oxide (SiO ₂ ) may be deposited between the substrate 111 and the amorphous silicon layer 114 by chemical vapor deposition to form a buffer layer (not shown). This buffer layer prevents mobile charge from infiltrating the amorphous silicon layer from the substrate in a subsequent process, protects the substrate from high temperatures during the crystallization of the amorphous silicon layer, and improves the contact characteristics of the semiconductor layer to the substrate. It plays a role.

Next, the elastic template stamp 150 on which the first self-aligned layer 151 is deposited is stamped on the amorphous silicon layer 114, and as shown in FIG. 2B, a predetermined portion on the amorphous silicon layer 114 is formed. The first self-aligned layer 151 is formed.

In this case, the first self-aligned layer 151 is formed of a self-assembling mono-molecular layer (Self Assembling mono-molecular layer), such as Thiol-series (Octadecyl Trichloro Silane) OTS, the elastic template stamp 150 PDMS (poly dimethyl silane-based) stamp can be used.

Specifically, the method for forming the first self-aligned layer is mixed with a self-assembled monomolecular substance such as thiol series or OTS in a solvent such as hexane or toluene, and then buried it in an elastic template stamp under a humidity of 40 to 60%. . The elastic template stamp is embossed with a predetermined portion. When the elastic template stamp is contacted and stamped on the substrate, a self-assembled monomolecular material that is buried on the surface of the embossed portion of the elastic template stamp is printed on the substrate.

Thereafter, as illustrated in FIG. 2C, a first metal is deposited by CVD to form a first metal layer 141 on the amorphous silicon layer 114 exposed between the first self-aligned layers 151. In the CVD method, a low pressure chemical vapor deposition method (LPCVD method) to be deposited at a high temperature of 550 ° C. or higher, and a plasma deposited using a SiF ₄ / SiH ₄ / H ₂ mixed gas at 400 ° C. or lower Plasma Enhanced Chemical Vapor Deposition (PECVD) and the like, but low temperature PECVD method is more preferable because no damage due to high temperature is required on the underlying amorphous silicon during the first metal deposition.

In this case, since the surface of the first self-aligned layer 151 has a hydrophobic characteristic, a first metal layer easily attached to a hydrophilic material is formed only on the amorphous silicon layer exposed between the first self-aligned layers and the first self-aligned layer. It is not formed on the layer.

Subsequently, as shown in FIG. 2D, any one of UV cleaning, hydrogen plasma surface treatment, or argon ion surface treatment is applied to remove the first self-aligned layer 151.

Accordingly, only the amorphous silicon layer 114 formed on the entire surface and the first metal layer 141 limited to a predetermined portion are provided on the substrate. Here, the first self-aligned layer is a pattern introduced to form the first metal layer pattern without applying a photo etching process.

Thereafter, as shown in FIG. 2E, the amorphous silicon layer 114 is etched and patterned using the first metal layer 141 as a mask.

Subsequently, as shown in FIG. 2F, a MILC method (Metal Induced Lateral Crystallization) inducing crystallization of an amorphous silicon layer using the first metal layer 141 on the amorphous silicon layer 114 as a catalyst metal ). The MILC method has the advantages of fast crystallization rate, low cost, and application to large area glass substrates.

That is, heat treatment is performed at a temperature of 500 ° C. or lower with a constant voltage applied to the substrate on which the amorphous silicon layer is formed, so that the first metal layer 141 is seeded to grow crystal grains. As a result, the amorphous silicon layer becomes a polysilicon layer having crystal grains, and the semiconductor layer 114a is completed.

As such, the first metal layer serves as a mask for etching the amorphous silicon layer and at the same time serves as a catalyst metal for crystallizing the amorphous silicon layer. Therefore, the first metal layer can be deposited by a CVD method, which is a low temperature process, and at the same time selects and uses a material that can be used as a catalyst metal when crystallizing the amorphous silicon layer. It is preferable to use metal materials such as copper, aluminum, and nickel. something to do.

Next, as shown in FIG. 2G, source / drain electrodes 115a and 115b are formed on both sides of the crystallized semiconductor layer 114a, respectively. That is, a low-resistance metal layer having a low specific resistance to prevent signal delay on the entire surface including the semiconductor layer, for example, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr) , Titanium (Ti), tantalum (Ta), molybdenum-tungsten (MoW) and the like are deposited and patterned by photolithography to form source / drain electrodes.

Thereafter, as shown in FIG. 2H, an inorganic material, silicon oxide (SiOx) or silicon nitride (SiNx) is deposited on the entire surface including the source / drain electrodes 115a and 115b to form a gate insulating layer 114.

Next, a gate electrode is formed on the semiconductor layer between the source electrode and the drain electrode. A photoetch process may be applied to form the gate electrode, but a self-aligned layer is used to reduce the number of times of use of the exposure mask. The embodiment will be described as a method of forming a gate electrode.

That is, as shown in FIG. 2I, an elastic template stamp 153 with a self-aligned layer material is stamped on the source / drain electrodes 115a and 115b, and as shown in FIG. 2J, the source / drain The second self-aligned layer 152 is formed on the electrodes 115a and 115b. The material of the second self-aligned layer and the method of forming the same are the same as or similar to the material and the method of the first self-aligned layer.

In this case, as the elastic template stamp, as shown in FIG. 2I, a flat contact surface with the substrate may be used, or only a portion where the gate electrode is to be formed is engraved. Since the second self-aligned layer is formed only on the source electrode and the drain electrode due to the step difference between the portion where the source / drain electrode is formed and the portion that is not formed, it is not formed on the portion where the gate electrode is formed. It is also possible to use a one-sided elastic template stamp.

Thereafter, as shown in FIG. 2K, a second metal is deposited by CVD to form a gate electrode 112a on the gate insulating layer 113 exposed between the second self-aligned layers 152. Examples of the CVD method include LPCVD method and PECVD method. Unlike the first metal layer, the second metal layer is not used as a catalyst metal of the crystallization method, and thus, for example, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), and chromium (Al). At least one of Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW) may be selected and used.

In this case, since the surface of the second self-alignment layer 152 has a hydrophobic characteristic, a second metal layer easily attached to a hydrophilic material is formed only on the gate insulating layer exposed between the second self-alignment layers and the second self-alignment layer It is not formed on the phase.

Subsequently, as shown in FIG. 2L, the second self-alignment layer 152 is removed by applying any one of UV cleaning, hydrogen plasma surface treatment, or argon ion surface treatment.

Accordingly, the polysilicon semiconductor layer 114a, the source / drain electrodes 115a and 115b formed on both sides of the semiconductor layer, and the gate electrode 112a insulated from the semiconductor layer and the source / drain electrodes by a gate insulating film. A polysilicon thin film transistor consisting of is completed.

Lastly, as shown in FIG. 2M, in order to prevent the gate electrode 112a from being exposed to the outside and being oxidized, a protective film is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx), which is an inorganic material, on the entire surface including the gate electrode. 116 can be further formed.

As described above, the polysilicon thin film transistor according to the present invention only needs to perform a mask process when forming a source / drain electrode and a gate electrode, thereby greatly reducing the number of mask processes. In this case, since the gate electrode may be formed by a process using a self-aligned layer, the number of mask processes may be further reduced once.

Manufacturing method of liquid crystal display device

First, as shown in FIG. 3A, an amorphous silicon layer 514 is formed by depositing amorphous silicon on the entire surface of the substrate 511 by chemical vapor deposition or the like.

Specifically, the substrate 511 is introduced into a CVD (Chemical Vapor Deposition) device by depositing amorphous silicon (a-Si) to a thin thickness of about several tens of micrometers by chemical vapor deposition (CVD) to form an amorphous silicon layer 514. To form. In this case, silane gas (SiH ₄ ) is used as the deposition gas, and argon gas (Ar) is used as the carrier gas, and the process is performed at an RF power of 100 to 500 W and a temperature of 430 to 500 ° C. .

At this time, a silicon oxide (SiO ₂ ) may be deposited between the substrate 511 and the amorphous silicon layer 514 by chemical vapor deposition to form a buffer layer (not shown).

Next, an elastic template stamp 550 embedded with the first self-aligned layer 551 is stamped onto the amorphous silicon layer 514 to cover a predetermined portion of the amorphous silicon layer 514 as shown in FIG. 3B. The self-aligned layer 551 is formed. The region where the self-aligned layer is not formed becomes a region where the semiconductor layer is formed by a subsequent process.

In this case, the self-aligning layer 551 is formed of a self-assembling mono-molecular layer (Self Assembling mono-molecular layer), such as Thiol-series (Octadecyl Trichloro Silane) OTS, the elastic template stamp 550 is PDMS (poly dimethyl silane) stamps and the like can be used.

Thereafter, as illustrated in FIG. 3C, metal is deposited by CVD to form a metal layer 541 on the amorphous silicon layer 514 exposed between the self-aligned layers 551. The CVD method may include LPCVD, PECVD, and the like, and it may be preferable to apply a PECVD method known as a low temperature process in order to prevent thermal damage to amorphous silicon under the metal deposition.

At this time, since the surface of the self-aligned layer 551 has a hydrophobic characteristic, a metal layer easily attached to a hydrophilic material is formed only on the amorphous silicon layer exposed between the self-aligned layers and not on the self-aligned layer.

Subsequently, as shown in FIG. 3D, any one of UV cleaning, hydrogen plasma surface treatment, or argon ion surface treatment is applied to remove the self-aligned layer 551.

Therefore, only the amorphous silicon layer 514 formed on the front surface and the metal layer 541 limited to a predetermined portion are provided on the substrate. Here, it can be seen that the self-aligned layer is a pattern introduced to form the metal layer pattern without applying a photo etching process.

Thereafter, as shown in FIG. 3E, the amorphous silicon layer 514 is etched and patterned using the metal layer 541 as a mask.

Next, as shown in FIG. 3F, a metal induced lateral crystallization (MILC) method is performed to induce crystallization of the amorphous silicon layer using the metal layer 541 on the amorphous silicon layer 514 as a catalyst metal.

That is, by heat treatment at a predetermined temperature or less while applying a constant voltage to the substrate on which the amorphous silicon layer is formed, the metal layer 541 is seeded to cause the growth of crystal grains. As a result, the amorphous silicon layer becomes a polysilicon layer having crystal grains, and the semiconductor layer 514a is completed.

As described above, the metal layer serves as a mask for etching the amorphous silicon layer and at the same time serves as a catalyst metal for crystallizing the amorphous silicon layer. Therefore, the metal layer can be deposited by a CVD method, which is a low temperature process, and at the same time selects and uses a material that can be used as a catalyst metal when crystallizing the amorphous silicon layer, and metal materials such as copper, aluminum, and nickel may be preferably used. .

Next, as shown in FIG. 3G, source / drain electrodes 515a and 515b are formed on both sides of the crystallized semiconductor layer 514a, respectively. That is, a low-resistance metal layer having a low specific resistance to prevent signal delay on the entire surface including the semiconductor layer, for example, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr) , Titanium (Ti), tantalum (Ta), molybdenum-tungsten (MoW), etc. are deposited and patterned by photolithography to form source / drain electrodes 515a and 515b on both sides of the semiconductor layer, respectively. The data lines DL and 515 are integrally connected.

3H, an inorganic material, silicon oxide (SiOx) or silicon nitride (SiNx) is deposited on the entire surface including the source / drain electrodes 515a and 115b to form a gate insulating layer 514.

Next, as a low-resistance metal layer on the entire surface including the gate insulating layer, for example, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) , Molybdenum-tungsten (MoW) and the like is deposited and patterned by a photolithography process, as shown in FIG. 3I, the gate electrode 512a is formed on the semiconductor layer between the source electrode 515a and the drain electrode 515b. And gate lines GL and 512 which are integrally connected to the gate electrode and vertically cross the data line to define a plurality of unit-pixels.

In this case, a photo-etching process may be applied to form the gate wiring and the gate electrode. However, the gate wiring and the gate electrode may be formed using a self-aligned layer to reduce the frequency of use of the exposure mask.

That is, when the self-aligned layer material is buried in the elastic template stamp fabricated so that the portion where the gate wiring and the gate electrode are formed is engraved and printed on the gate insulating film, the self-aligning layer is not formed in the portion where the gate wiring and the gate electrode are formed. In the subsequent process, the metal is deposited in a region where the self-alignment layer is not formed to complete the gate wiring and the gate electrode pattern. As such, when the gate wiring and the gate electrode are formed by using the self-aligning layer, the mask process is reduced by one time, which makes the process simpler.

As a result, the polysilicon thin film transistor stacked with the polysilicon semiconductor layer 514a, the source / drain electrodes 515a and 515b, the gate insulating film 513 and the gate electrode 512 is completed. The polysilicon thin film transistor is formed at the intersection of the gate line and the data line.

Thereafter, as illustrated in FIG. 3J, silicon oxide (SiOx) or silicon nitride (SiNx), which is an inorganic material, is deposited on the entire surface including the gate wiring 512 and the gate electrode 512, or BCB (Benzocyclobutene) which is an organic material. ), An acrylic resin is applied to form a protective film 116.

Thereafter, as shown in FIG. 3K, the gate insulation layer 513 and the passivation layer 516 over the drain electrode 515b are removed to form a contact hole through which the drain electrode is exposed.

Finally, indium tin oxide (ITO) or indium zinc oxide (IZO), etc. are deposited and patterned on the entire surface including the passivation layer to form the pixel electrode 517 contacting the drain electrode 515b through the contact hole.

Thus, the polysilicon thin film transistor array substrate is completed.

Next, although not illustrated, a black matrix for preventing light leakage, a color filter layer of red, green, and blue (R, G, B) for color implementation, and a common field for forming an electric field together with the pixel electrode to control the liquid crystal A color filter layer array substrate having an electrode is prepared.

Finally, a sealant of an epoxy resin serving as an adhesive is formed on the polysilicon thin film transistor array substrate, and evenly formed spacers are formed on the inner surface of the color filter layer array substrate. When the liquid crystal is injected into a space of several micrometers in between to seal the liquid crystal injection hole, a liquid crystal display device including a polysilicon thin film transistor is completed.

As described above, the polysilicon thin film transistor array substrate of the liquid crystal display device according to the present invention provides a source / drain electrode (including data wiring), a gate electrode (including gate wiring), a pixel electrode, contacting the drain electrode and the pixel electrode. Since only a total of four mask processes need to be performed to form a contact hole, the number of mask processes can be greatly reduced. In this case, the gate electrode or the pixel electrode may be formed by a process using a self-aligned layer, thereby reducing the number of mask processes once more.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

The method of manufacturing a polysilicon thin film transistor and the method of manufacturing a liquid crystal display device using the same according to the present invention as described above have the following effects.

First, a metal layer is formed on a predetermined portion of an amorphous silicon layer. The metal layer serves as a mask for etching the amorphous silicon layer and simultaneously serves as a catalyst metal for crystallizing the amorphous silicon layer, thereby simplifying the process. Can be.

Second, in order to pattern the metal layer, since the self-aligned layer can be used without performing a photoetch process, the number of times of use of the exposure mask can be reduced.

Third, in order to form the gate electrode or the gate wiring, since the self-aligned layer can be used without performing the photo etching process, the number of times of use of the exposure mask can be further reduced.

Fourth, in order to construct a polysilicon thin film transistor, a total of four mask processes for forming a semiconductor layer, a gate electrode, a source / drain electrode, and a contact hole are performed. However, the present invention masks only a process for forming a source / drain electrode. The number of mask processes can be significantly reduced by performing the process.

Fifth, in order to construct a polysilicon thin film transistor array substrate of a liquid crystal display device, a first contact hole, a pixel electrode, and the first contact hole for contacting the semiconductor layer and the source / drain electrode Although a total of six mask processes are performed to form a second contact hole for contacting the drain electrode and the pixel electrode, the present invention forms a source / drain electrode, a pixel electrode, and a contact hole for contacting the drain electrode and the pixel electrode. Since only three mask processes need to be performed, the number of mask processes can be greatly reduced.

Claims (32)

Forming an amorphous silicon layer on the substrate, Forming a first self-aligned layer on a predetermined portion of the amorphous silicon layer; Forming a first metal layer on the amorphous silicon layer exposed between the first self-aligned layers; Removing the first self-aligned layer; Etching the amorphous silicon layer using the first metal layer as a mask to form a semiconductor layer; Crystallizing the amorphous silicon layer using the first metal layer as a catalyst; Forming source / drain electrodes on both sides of the polysilicon layer, Forming a gate insulating film on the entire surface including the source / drain electrodes; And forming a gate electrode on the gate insulating film between the source electrode and the drain electrode. The method of claim 1, The first self-aligned layer is a method for manufacturing a polysilicon thin film transistor, characterized in that the self-assembling mono-molecular layer (Self Assembling mono-molecular layer). The method of claim 2, The self-assembled monolayer is a method of manufacturing a polysilicon thin film transistor, characterized in that formed by any one of the thiol series (Thiol-series) or OTS (Octadecyl Trichloro Silane). The method of claim 1, The surface of the first self-aligned layer is a method of manufacturing a polysilicon thin film transistor, characterized in that hydrophobic. The method of claim 1, In the step of removing the first self-aligned layer, A method for producing a polysilicon thin film transistor, characterized in that any one of UV cleaning, hydrogen plasma surface treatment or argon ion surface treatment is applied. The method of claim 1, The first self-aligned layer is a polysilicon thin film transistor manufacturing method, characterized in that formed by stamping on the amorphous silicon layer elastic template stamped with a self-aligned layer material. The method of claim 6, The elastic template stamp is a polysilicon thin film transistor, characterized in that the PDMS (poly dimethyl silane) stamp. The method of claim 1, In the step of crystallizing the amorphous silicon layer, a method of manufacturing a polysilicon thin film transistor, characterized in that applying the MILC (Metal Induced Lateral Crystallization) method. The method of claim 1, The first metal layer is a method of manufacturing a polysilicon thin film transistor, characterized in that formed by CVD (Chemical Vapor Deposition) method. The method of claim 1, The first metal layer is a low-temperature CVD method can be deposited, and at the same time the polysilicon thin film transistor, characterized in that the amorphous silicon layer is formed of a material used as a catalyst metal when crystallization. The method of claim 10, The first metal layer is a method of manufacturing a polysilicon thin film transistor, characterized in that formed of any one of copper, aluminum, nickel. The method of claim 1, Forming the gate electrode, Forming a second self-aligned layer on the source / drain electrodes; Forming a second metal layer on the gate insulating film between the second self-aligned layers; Removing the second self-aligned layer; and manufacturing a polysilicon thin film transistor. The method of claim 12, And the second self-aligned layer is formed by stamping on the source / drain electrodes an elastic template stamp embedded with a self-aligned layer material. The method of claim 12, The second self-aligned layer is a method of manufacturing a polysilicon thin film transistor, characterized in that formed of a self-assembling mono-molecular layer (Thiol-series) or OTS (Octadecyl Trichloro Silane) self-assembly monolayer (Self Assembling mono-molecular layer). The method of claim 12, And the surface of the second self-aligned layer is hydrophobic. The method of claim 12, In removing the second self-aligned layer, A method for producing a polysilicon thin film transistor, characterized in that any one of UV cleaning, hydrogen plasma surface treatment or argon ion surface treatment is applied. The method of claim 12, The second metal layer is at least one of copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW). Method for producing a polysilicon thin film transistor, characterized in that formed in one. Forming an amorphous silicon layer on the substrate, Forming a self-aligned layer on a predetermined portion of the amorphous silicon layer; Forming a metal layer on the amorphous silicon layer exposed between the self-aligned layers; Removing the self-aligned layer; Etching the amorphous silicon layer using the metal layer as a mask to form a semiconductor layer; Crystallizing the amorphous silicon layer using the metal layer as a catalyst; Forming source / drain electrodes on both sides of the polysilicon layer, Forming a gate insulating film on the entire surface including the source / drain electrodes; Forming a gate electrode on the gate insulating film between the source electrode and the drain electrode; Forming a protective film on the entire surface including the gate electrode; And forming a pixel electrode in contact with the drain electrode on the passivation layer. The method of claim 18, Forming a data line simultaneously with the source / drain electrodes; And forming a gate line defining a sub-pixel crossing the data line at the same time as the gate electrode. The method of claim 19, The gate line and the gate electrode are patterned by applying a photolithography process. The method of claim 18, And the self-aligning layer is a self assembling mono-molecular layer. The method of claim 21, The self-assembled monolayer is a method of manufacturing a liquid crystal display device, characterized in that formed by one of thiol series (Thiol-series) or OTS (Octadecyl Trichloro Silane). The method of claim 18, And the surface of the self-aligning layer is hydrophobic. The method of claim 18, In the step of removing the self-aligned layer, A method for manufacturing a liquid crystal display device, characterized by applying any one of UV cleaning, hydrogen plasma surface treatment, or argon ion surface treatment. The method of claim 18, And the self-aligning layer is formed by stamping an elastic template stamp on which the self-aligning layer material is deposited on the amorphous silicon layer. The method of claim 25, The elastic template stamp is a manufacturing method of the liquid crystal display device, characterized in that the poly dimethyl silane (PDMS) stamp. The method of claim 18, In the step of crystallizing the amorphous silicon layer, the manufacturing method of the liquid crystal display device, characterized in that applying the MILC (Metal Induced Lateral Crystallization) method. The method of claim 18, The metal layer is formed by a CVD method. The method of claim 18, The metal layer can be deposited by a CVD method which is a low temperature process, and at the same time the method of manufacturing a liquid crystal display device characterized in that the amorphous silicon layer is formed of a material used as a catalyst metal when crystallization. The method of claim 29, And the first metal layer is formed of any one of copper, aluminum and nickel. The method of claim 19, Forming the gate wiring and the gate electrode, Forming a self-aligned layer in the remaining region except for the portion where the gate wiring and the gate electrode are formed; Forming a metal layer on the gate insulating film between the self-aligned layers; And removing the second self-aligned layer. The method of claim 31, wherein When the second self-aligned layer is formed, an elastic template stamp fabricated so as to engrave the portion where the gate wiring and the gate electrode are formed is used.

Images