KR20080002504A - Method for repair of semiconductor device - Google Patents

Method for repair of semiconductor device Download PDF

Info

Publication number
KR20080002504A
KR20080002504A KR1020060061372A KR20060061372A KR20080002504A KR 20080002504 A KR20080002504 A KR 20080002504A KR 1020060061372 A KR1020060061372 A KR 1020060061372A KR 20060061372 A KR20060061372 A KR 20060061372A KR 20080002504 A KR20080002504 A KR 20080002504A
Authority
KR
South Korea
Prior art keywords
fuse
semiconductor device
fuse line
film
lines
Prior art date
Application number
KR1020060061372A
Other languages
Korean (ko)
Inventor
심상옥
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020060061372A priority Critical patent/KR20080002504A/en
Publication of KR20080002504A publication Critical patent/KR20080002504A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A method for repairing a semiconductor device is provided to avoid a fail and malfunction of adjacent fuse lines caused by cracks by forming a nitride layer spacer at both sides of adjacent fuse lines. Fuse lines(36a,36b) are formed on a semiconductor substrate(31) in which a conductive pattern is connected to a power supply and a first interlayer dielectric is formed to cover the conductive pattern. The fuse lines are blown to perform a repair process. Passivation layers are formed at the blown portions of the fuse lines. The fuse line can be made of a stack layer of a TiN layer(34a,34b) and a polysilicon layer(35a,35b). The passivation layer can be formed as a spacer type at the lateral surface of the blown portion of the fuse line.

Description

반도체 소자의 리페어 방법{METHOD FOR REPAIR OF SEMICONDUCTOR DEVICE}Repair method of semiconductor device {METHOD FOR REPAIR OF SEMICONDUCTOR DEVICE}

도 1은 종래기술에 따른 반도체 소자의 퓨즈박스를 설명하기 위한 단면도.1 is a cross-sectional view for explaining a fuse box of a semiconductor device according to the prior art.

도 2는 종래의 문제점을 설명하기 위한 반도체 소자의 사진.2 is a photograph of a semiconductor device for explaining a conventional problem.

도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체 소자의 리페어 방법을 설명하기 위한 공정별 단면도.3A to 3E are cross-sectional views of processes for describing a method of repairing a semiconductor device, according to an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings

31 : 반도체 기판 32 : 도전패턴31 semiconductor substrate 32 conductive pattern

33 : 제1층간절연막 34,34a,34b : TiN막33: first interlayer insulating film 34, 34a, 34b: TiN film

35,35a,35b : 폴리실리콘막 36a : 제1퓨즈라인35, 35a, 35b: polysilicon film 36a: first fuse line

36b : 제2퓨즈라인 37 : 질화막 스페이서36b: second fuse line 37: nitride film spacer

38 : 제2층간절연막 39 : 플러그38: second interlayer insulating film 39: plug

40 : 금속배선40: metal wiring

본 발명은 반도체 소자의 리페어 방법에 관한 것으로, 보다 상세하게는, 크랙(Crack)으로 인해 유발되는 인접 퓨즈라인의 페일 및 오동작을 방지하여 반도체 소자의 신뢰성 및 제조 수율을 개선할 수 있는 반도체 소자의 리페어 방법에 관한 것이다.The present invention relates to a method of repairing a semiconductor device, and more particularly, to a semiconductor device capable of improving the reliability and manufacturing yield of a semiconductor device by preventing failure and malfunction of adjacent fuse lines caused by cracks. It is about a repair method.

반도체 장치는 주로 실리콘 재질의 기판 상에 설정된 회로 패턴을 반복적으로 형성하여 집적 회로를 갖는 셀들을 형성하는 패브리케이션(Fabrication : FAB) 공정과, 상기 셀들이 형성된 기판을 칩(Chip) 단위로 패키징(Packaging)하는 어셈블리(Assembly) 공정을 포함한다. 그리고, 상기 패브리케이션 공정과 어셈블리 공정 사이에는 상기 기판 상에 형성하는 셀들의 전기적 특성을 검사하기 위한 공정(Electrical Die Sorting : EDS)을 수행한다.A semiconductor device mainly includes a fabrication (FAB) process of repeatedly forming a circuit pattern set on a silicon substrate to form cells having an integrated circuit, and packaging the substrate on which the cells are formed in a chip unit (Chip). Packaging and assembly process. In addition, a process for inspecting electrical characteristics of cells formed on the substrate is performed between the fabrication process and the assembly process.

상기 검사 공정은 기판 상에 형성한 셀들이 전기적으로 양호한 상태 또는 불량한 상태를 갖는 가를 판별하는 공정이다. 이는, 상기 검사 공정을 통하여 불량한 상태를 갖는 셀들을 상기 어셈블리 공정을 수행하기 이전에 제거함으로서, 상기 어셈블리 공정에서 소모되는 노력 및 비용을 절감하기 위함이다. 그리고, 상기 불량한 상태를 갖는 셀들을 조기에 발견하고, 이를 리페어(Repair) 공정을 통하여 재생하기 위함이다.The inspection step is a step of determining whether the cells formed on the substrate have an electrically good state or a bad state. This is to reduce the effort and cost consumed in the assembly process by removing the cells having a bad state through the inspection process before performing the assembly process. In order to detect the cells having the defective state at an early stage and regenerate them through a repair process.

여기서, 상기 리페어 공정에 대해 좀더 자세히 설명하면 다음과 같다.Here, the repair process will be described in more detail as follows.

반도체 소자 제조 공정 중 결함이 발생할 경우 소자의 제조 수율을 향상시킬 목적으로 소자 설계시 결함이 있는 소자 또는 회로를 대체하기 위하여 여분(Redundancy)의 셀을 부가하며, 이러한 여분의 셀을 집적회로에 접속시키기 위해 퓨즈라인을 함께 설계하고 있는데, 상기 리페어 공정은 검사공정을 통해 불량으로 판명된 셀을 상기 퓨즈라인을 사용하여 칩 내에 내장된 여분의 셀과 연결시켜 재생 시키는 공정이다. 즉, 레이저를 이용해서 상기 퓨즈라인들 중 특정 퓨즈라인을 절단하는 퓨즈 블로윙(Blowing) 공정을 수행함으로써 리페어할 셀들의 위치 정보를 생성하는 것이다.Redundancy cells are added to replace defective devices or circuits in the design of devices for the purpose of improving the manufacturing yield of devices in the event of a defect during the semiconductor device manufacturing process, and connecting such redundant cells to the integrated circuit. In order to make the fuse line together, the repair process is a process in which a cell, which has been found to be defective through an inspection process, is connected to a spare cell embedded in the chip using the fuse line to be regenerated. That is, location information of cells to be repaired is generated by performing a fuse blowing process of cutting a specific fuse line among the fuse lines using a laser.

이하에서는, 도 1을 참조하여 종래기술에 따른 반도체 소자의 퓨즈를 설명하도록 한다.Hereinafter, a fuse of a semiconductor device according to the related art will be described with reference to FIG. 1.

도 1을 참조하면, 종래의 퓨즈는 반도체 기판(11) 퓨즈 영역 상에 형성되며 전원전압 공급부(도시안됨)와 연결되도록 형성된 도전패턴(12), 상기 반도체 기판(11) 상에 도전패턴(12)을 덮도록 형성된 제1층간절연막(13), 상기 제1층간절연막(13) 상에 상기 도전패턴(12)의 인접하는 측부와 각각 오버랩되도록 형성된 제1 및 제2퓨즈라인(16a,16b), 상기 제1 및 제2퓨즈라인(16a,16b) 상에 형성된 제2층간절연막(17), 상기 제2층간절연막(17)과 제1 및 제2퓨즈라인(16a,16b) 및 제1층간절연막(13) 내에 도전패턴(12)과 연결되게 형성된 플러그(18) 및 상기 제2층간절연막(17) 상에 플러그(18)와 콘택되도록 형성된 금속배선(19)으로 구성된다.Referring to FIG. 1, a conventional fuse is formed on a fuse region of a semiconductor substrate 11 and is formed to be connected to a power supply voltage supply unit (not shown), and a conductive pattern 12 is formed on the semiconductor substrate 11. ) And first and second fuse lines 16a and 16b formed on the first interlayer insulating layer 13 to overlap the adjacent portions of the conductive pattern 12 on the first interlayer insulating layer 13. And a second interlayer insulating film 17 formed on the first and second fuse lines 16a and 16b, the second interlayer insulating film 17, and the first and second fuse lines 16a and 16b and the first layer. The plug 18 is formed to be connected to the conductive pattern 12 in the insulating layer 13 and the metal wiring 19 formed to contact the plug 18 on the second interlayer insulating layer 17.

여기서, 상기 제1 및 제2퓨즈라인(16a,16b)은 TiN막(14a,14b)과 폴리실리콘막(15a,15b)의 적층막으로 이루어진다.The first and second fuse lines 16a and 16b may be formed of a laminated film of the TiN films 14a and 14b and the polysilicon films 15a and 15b.

이후, 도시하지는 않았으나, 레이저를 이용해서 상기 퓨즈라인들(16a,16b) 중 특정 퓨즈라인을 절단하는 퓨즈 블로윙(Blowing) 공정을 포함하는 공지의 검사 및 리페어 공정을 차례로 수행한다. 여기서, 상기 블로윙 공정시 블로윙된 곳을 통해 습기가 침투하여 블로윙된 퓨즈라인의 TiN막(14a,14b)이 산화되며 저항이 증가한다.Subsequently, although not illustrated, a known inspection and repair process including a fuse blowing process of cutting a specific fuse line among the fuse lines 16a and 16b using a laser is sequentially performed. Here, during the blowing process, moisture penetrates through the blown place and the TiN films 14a and 14b of the blown fuse line are oxidized to increase resistance.

그러나, 전술한 종래기술의 경우에는 상기 블로윙 공정시 산화된 TiN막(14a)의 부피가 팽창하여, 도 2에 도시된 바와 같이, 제1 및 제2층간절연막(13,17) 계면에 틈이 형성되는 크랙(Crack)이 발생하며, 상기 크랙으로 인해 블로윙되지 않은 인접 퓨즈라인(16b)의 TiN막(14b)이 산화되는 페일을 유발한다. 상기 블로윙되지 않은 퓨즈라인(16b)의 TiN막(14b)이 산화되면 저항이 증가하여 마치 블로윙된 것처럼 잘못 인식됨으로써 오동작이 유발되며, 이때문에, 반도체 소자의 신뢰성 및 제조 수율이 저하된다는 문제점이 있다.However, in the above-described prior art, the volume of the oxidized TiN film 14a is expanded during the blowing process, so that a gap is formed between the first and second interlayer insulating films 13 and 17 as shown in FIG. A crack is formed, which causes a failure in which the TiN film 14b of the adjacent fuse line 16b that is not blown oxidizes due to the crack. If the TiN film 14b of the non-blowed fuse line 16b is oxidized, the resistance is increased and misrecognized as if it is blown, thereby causing a malfunction. Thus, a problem that the reliability and manufacturing yield of the semiconductor device is degraded is caused. have.

따라서, 본 발명은 상기와 같은 목적을 달성하기 위해 안출된 것으로서, 크랙(Crack)으로 인해 유발되는 인접 퓨즈라인의 페일 및 오동작을 방지할 수 있는 반도체 소자의 리페어 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of repairing a semiconductor device capable of preventing the failure and malfunction of adjacent fuse lines caused by cracks.

또한, 본 발명은 상기 인접 퓨즈라인의 페일 및 오동작을 방지함으로써 반도체 소자의 신뢰성 및 제조 수율을 개선할 수 있는 반도체 소자의 리페어 방법을 제공함에 다른 목적이 있다.Another object of the present invention is to provide a method of repairing a semiconductor device, which can improve reliability and manufacturing yield of the semiconductor device by preventing failing and malfunction of the adjacent fuse line.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 리페어 방법은, 전원전압 공급부와 연결되게 도전패턴이 형성되고 상기 도전패턴을 덮도록 제1층간절연막이 형성된 반도체 기판 상에 퓨즈라인을 형성하는 단계; 리페어를 위하여 상기 퓨즈라인을 절단하는 단계; 및 상기 퓨즈라인의 절단부에 각각 보호막을 형성하는 단계;를 포함한다.In the repairing method of the semiconductor device of the present invention for achieving the above object, a fuse line is formed on a semiconductor substrate on which a conductive pattern is formed to be connected to a power supply voltage supply and a first interlayer insulating film is formed to cover the conductive pattern. step; Cutting the fuse line for repair; And forming a passivation layer on each cut portion of the fuse line.

여기서, 상기 퓨즈라인은 TiN막과 폴리실리콘막의 적층막으로 이루어진다.Here, the fuse line is formed of a laminated film of a TiN film and a polysilicon film.

상기 보호막은 상기 퓨즈라인의 절단부 측면에 스페이서 형태로 형성한다.The protective layer is formed in the form of a spacer on the side of the cut portion of the fuse line.

상기 보호막은 질화막으로 형성한다.The protective film is formed of a nitride film.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 간략하게 설명하면, 본 발명은 제1 및 제2퓨즈라인의 서로 인접하는 측면 상에 질화막 스페이서을 형성한다.First, the technical principle of the present invention will be briefly described. The present invention forms nitride film spacers on adjacent sides of the first and second fuse lines.

이렇게 하면, 상기 제1퓨즈라인이 블로윙시 산화된 TiN막으로 인해 크랙이 발생하여도 상기 제1 및 제2퓨즈라인 사이에 형성된 질화막 스페이서가 블로윙되지 않은 제2퓨즈라인의 TiN막이 산화되는 것을 방지하므로 상기 블로윙되지 않은 제2퓨즈라인의 페일 및 오동작을 방지할 수 있으다. 따라서, 반도체 소자의 신뢰성 및 제조 수율을 개선할 수 있다.This prevents oxidation of the TiN film of the second fuse line in which the nitride spacer formed between the first and second fuse lines is not blown even when a crack occurs due to the TiN film oxidized when the first fuse line is blown. Therefore, it is possible to prevent the failing and malfunction of the non-blowing second fuse line. Therefore, the reliability and manufacturing yield of the semiconductor device can be improved.

자세하게, 도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체 소자의 리페어 방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다.In detail, FIGS. 3A to 3E are cross-sectional views of processes for describing a repair method of a semiconductor device according to an exemplary embodiment of the present invention.

도 3a를 참조하면, 반도체 기판(31) 상에 전원전압 공급부(도시안됨)와 연결되도록 도전패턴(32)을 형성한 후, 상기 도전패턴(32)을 덮도록 상기 도전패턴(32)을 포함한 기판(31) 상에 제1층간절연막(33)을 형성한다. 그 다음, 상기 제1층간절연막(33) 상에 TiN막(34)과 폴리실리콘막(35)을 차례로 형성한다.Referring to FIG. 3A, after the conductive pattern 32 is formed on the semiconductor substrate 31 to be connected to a power voltage supply part (not shown), the conductive pattern 32 is included to cover the conductive pattern 32. A first interlayer insulating film 33 is formed on the substrate 31. Next, a TiN film 34 and a polysilicon film 35 are sequentially formed on the first interlayer insulating film 33.

도 3b를 참조하면, 상기 폴리실리콘막(35)과 TiN막(34)을 식각해서 이격 배 치되는 제1 및 제2퓨즈라인(36a,36b)을 형성한다. 여기서, 상기 제1 및 제2퓨즈라인(36a,36b)은 하나의 전원전압 공급부(도시안됨)를 공유하도록 형성되며, TiN막(34a,34b)과 폴리실리콘막(35a,35b)의 적층막 구조를 갖는다.Referring to FIG. 3B, the polysilicon layer 35 and the TiN layer 34 are etched to form first and second fuse lines 36a and 36b spaced apart from each other. Here, the first and second fuse lines 36a and 36b are formed to share one power supply voltage supply unit (not shown), and the stacked films of the TiN films 34a and 34b and the polysilicon films 35a and 35b. Has a structure.

도 3c를 참조하면, 상기 제1 및 제2퓨즈라인(36a,36b)이 형성된 기판(31) 전면 상에 스페이서용 질화막(도시안됨)을 증착한다. 이때, 상기 스페이서용 질화막은 저온, 바람직하게는, 200℃ 이하의 온도에서 증착된다.Referring to FIG. 3C, a nitride nitride film (not shown) is deposited on the entire surface of the substrate 31 on which the first and second fuse lines 36a and 36b are formed. In this case, the spacer nitride film is deposited at a low temperature, preferably at a temperature of 200 ° C. or less.

다음으로, 상기 스페이서용 질화막이 제1퓨즈라인(36a)과 제2퓨즈라인(36b)의 인접하는 측면 상에만 잔류하도록 식각 공정을 수행하여, 제1퓨즈라인(36a)과 제2퓨즈라인(36b)의 인접하는 측면 각각에 질화막 스페이서(37)를 형성한다.Next, an etching process is performed such that the spacer nitride layer remains only on adjacent sides of the first fuse line 36a and the second fuse line 36b, thereby forming the first fuse line 36a and the second fuse line ( A nitride film spacer 37 is formed on each of the adjacent side surfaces of 36b).

여기서, 상기 질화막 스페이서(37)는 제1퓨즈라인(36a)의 블로윙 공정시 침투된 수분으로 인해 제1퓨즈라인(36a)의 TiN막(34a)이 산화되고 부피가 팽창하여 크랙이 발생할 경우, 블로윙되지 않은 제1퓨즈라인(36b)의 TiN막(34b)이 산화되는 것을 방지하는 역할을 하며, 이를 통해, 상기 블로윙되지 않은 제1퓨즈라인(36b)의 페일 및 오동작을 방지할 수 있다. 따라서, 반도체 소자의 신뢰성 및 제조 수율을 효과적으로 개선할 수 있다.Here, when the nitride film spacer 37 is oxidized and the volume expands due to oxidation of the TiN film 34a of the first fuse line 36a due to moisture penetrated during the blowing process of the first fuse line 36a, It serves to prevent the TiN film 34b of the non-blowed first fuse line 36b from being oxidized, thereby preventing failing and malfunction of the non-blowed first fuse line 36b. Therefore, the reliability and manufacturing yield of a semiconductor element can be improved effectively.

도 3d를 참조하면, 상기 질화막 스페이서(37)와 제1 및 제2퓨즈라인(36a,36b)을 덮도록 제1층간절연막(33) 상에 제2층간절연막(38)을 형성한다.Referring to FIG. 3D, a second interlayer insulating layer 38 is formed on the first interlayer insulating layer 33 to cover the nitride spacer 37 and the first and second fuse lines 36a and 36b.

도 3e를 참조하면, 상기 제2층간절연막(38)과 제1 및 제2퓨즈라인(36a,36b) 및 제1층간절연막(33) 내에 상기 도전패턴(32)과 연결되게 플러그(39)들을 형성한 후, 상기 제2층간절연막(38) 상에 상기 플러그(39)들과 콘택되는 금속배선(40)을 형성한다.Referring to FIG. 3E, the plugs 39 may be connected to the conductive patterns 32 in the second interlayer insulating layer 38, the first and second fuse lines 36a and 36b, and the first interlayer insulating layer 33. After the formation, the metal interconnection 40 in contact with the plugs 39 is formed on the second interlayer insulating layer 38.

여기서, 본 발명은 제1퓨즈라인(36a)과 제2퓨즈라인(36b)의 서로 인접하는 측면 각각에 질화막 스페이서(37)를 형성함으로써, 상기 제1퓨즈라인(36a)의 블로윙(Blowing) 공정시 발생하는 크랙(Crack)으로 인해 유발되는 제2퓨즈라인(36b)의 페일 및 오동작을 방지할 수 있으며, 이를 통해, 반도체 소자의 신뢰성 및 제조 수율을 개선할 수 있다.Here, in the present invention, the nitride film spacers 37 are formed on the side surfaces of the first fuse line 36a and the second fuse line 36b that are adjacent to each other, thereby blowing the first fuse line 36a. Fail and malfunction of the second fuse line 36b caused by cracks generated at the time may be prevented, thereby improving reliability and manufacturing yield of the semiconductor device.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 퓨즈라인의 형성시 서로 인접하는 퓨즈라인의 양측에 질화막 스페이서를 형성함으로써, 크랙으로 인해 유발되는 인접 퓨즈라인의 페일 및 오동작을 방지할 수 있다.As described above, the present invention forms nitride spacers on both sides of the fuse line adjacent to each other when forming the fuse line, it is possible to prevent the failure and malfunction of the adjacent fuse line caused by the crack.

게다가, 본 발명은 상기 인접 퓨즈라인의 페일 및 오동작을 방지함으로써 반도체 소자의 신뢰성 및 제조 수율을 개선할 수 있다.In addition, the present invention can improve the reliability and manufacturing yield of the semiconductor device by preventing the failing and malfunction of the adjacent fuse line.

Claims (4)

전원전압 공급부와 연결되게 도전패턴이 형성되고 상기 도전패턴을 덮도록 제1층간절연막이 형성된 반도체 기판 상에 퓨즈라인을 형성하는 단계;Forming a fuse line on a semiconductor substrate on which a conductive pattern is formed to be connected to a power supply voltage supply and a first interlayer insulating film is formed to cover the conductive pattern; 리페어를 위하여 상기 퓨즈라인을 절단하는 단계; 및Cutting the fuse line for repair; And 상기 퓨즈라인의 절단부에 각각 보호막을 형성하는 단계;Forming protective films on the cut portions of the fuse lines; 를 포함하는 것을 특징으로 하는 반도체 소자의 리페어 방법.Repair method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 퓨즈라인은 TiN막과 폴리실리콘막의 적층막으로 이루어진 것을 특징으로 하는 반도체 소자의 리페어 방법.The fuse line is a repair method of a semiconductor device, characterized in that consisting of a laminated film of a TiN film and a polysilicon film. 제 1 항에 있어서,The method of claim 1, 상기 보호막은 상기 퓨즈라인의 절단부 측면에 스페이서 형태로 형성하는 것을 특징으로 하는 반도체 소자의 리페어 방법.The protective film is a repair method of a semiconductor device, characterized in that formed in the form of a spacer on the side of the cut portion of the fuse line. 제 1 항에 있어서,The method of claim 1, 상기 보호막은 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 리페어 방법.The protective film is formed of a nitride film repair method of a semiconductor device.
KR1020060061372A 2006-06-30 2006-06-30 Method for repair of semiconductor device KR20080002504A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020060061372A KR20080002504A (en) 2006-06-30 2006-06-30 Method for repair of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060061372A KR20080002504A (en) 2006-06-30 2006-06-30 Method for repair of semiconductor device

Publications (1)

Publication Number Publication Date
KR20080002504A true KR20080002504A (en) 2008-01-04

Family

ID=39214284

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060061372A KR20080002504A (en) 2006-06-30 2006-06-30 Method for repair of semiconductor device

Country Status (1)

Country Link
KR (1) KR20080002504A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101048794B1 (en) * 2009-07-03 2011-07-15 주식회사 하이닉스반도체 Fuse part of semiconductor device
US11268227B2 (en) 2018-08-29 2022-03-08 Lg Electronics Inc. Washing machine based on artificial intelligence and method of controlling the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101048794B1 (en) * 2009-07-03 2011-07-15 주식회사 하이닉스반도체 Fuse part of semiconductor device
US8399958B2 (en) 2009-07-03 2013-03-19 Hynix Semiconductor Inc. Fuse part for semiconductor device
US11268227B2 (en) 2018-08-29 2022-03-08 Lg Electronics Inc. Washing machine based on artificial intelligence and method of controlling the same

Similar Documents

Publication Publication Date Title
KR20080002504A (en) Method for repair of semiconductor device
KR100808593B1 (en) Fuse box of semiconductor device and method for forming the same
KR100728964B1 (en) Fuse of semiconductor device and method for forming the same
KR20120103982A (en) Fuse pattern and method for manufacturing the same
KR20080027078A (en) Fuse box of semiconductor device and method for forming the same
KR100871389B1 (en) Fuse of semiconductor device and method for forming the same
KR100762900B1 (en) Method for forming fuse box of semiconductor device
KR101096439B1 (en) Method for forming fuse box of semiconductor device
KR100929627B1 (en) Fuse box of semiconductor device and forming method thereof
KR20080020394A (en) Repairing method of semiconductor device
KR101052873B1 (en) Fuse box of semiconductor device and repair method using same
KR20070048404A (en) Fuse of semiconductor device
KR20080028543A (en) Fuse box of semiconductor device and method for forming the same
KR20070115518A (en) Fuse line of semiconductor device
KR100861305B1 (en) Method of manufacturing semiconductor device
KR101150554B1 (en) Semiconductor Device and Method for Manufacturing the same
KR20090103499A (en) Method for repair of semiconductor device
KR20070041111A (en) Method for forming fuse of semiconductor device
KR100950750B1 (en) Fuse box of semiconductor device
KR20080081551A (en) Method for repair of semiconductor device
KR20080005720A (en) Method for manufacturing fuse box a semiconductor device
KR20100036013A (en) Fuse box of semiconductor device and method for forming the same
KR20070100546A (en) Method for forming fuse box of semiconductor device
KR20080029704A (en) Method for forming fuse box of semiconductor device
KR100833588B1 (en) Method of manufacturing semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination