KR20080001528A - Method for fabricating the same of semiconductor device - Google Patents

Method for fabricating the same of semiconductor device Download PDF

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Publication number
KR20080001528A
KR20080001528A KR1020060060005A KR20060060005A KR20080001528A KR 20080001528 A KR20080001528 A KR 20080001528A KR 1020060060005 A KR1020060060005 A KR 1020060060005A KR 20060060005 A KR20060060005 A KR 20060060005A KR 20080001528 A KR20080001528 A KR 20080001528A
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South Korea
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photoresist
semiconductor device
photoresist pattern
pattern
manufacturing
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KR1020060060005A
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Korean (ko)
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이정석
임병혁
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주식회사 하이닉스반도체
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Priority to KR1020060060005A priority Critical patent/KR20080001528A/en
Publication of KR20080001528A publication Critical patent/KR20080001528A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H01L21/423—Bombardment with radiation with high-energy radiation
    • H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation

Abstract

A method for manufacturing a semiconductor substrate is provided to perform ion implantation partially by executing sequentially thermal treatment having different temperature from each other. Gate patterns(22) are formed on a semiconductor substrate(21). A photoresist pattern(23A) is formed by patterning a photoresist so as to open an ion implantation area between the patterns. A thermal treatment is executed on the photoresist pattern. The residues of the photoresist pattern remained around the patterns are removed. By executing sequentially thermal treatment having different temperature from each other, the photoresist pattern is reflowed.

Description

반도체 소자의 제조방법{METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE}

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 제조방법을 설명하기 위한 공정단면도,1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

도 2a 및 도 2b는 도 1a 및 도 1b의 TEM사진,Figure 2a and 2b is a TEM picture of Figures 1a and 1b,

도 3a 내지 도 3c는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정단면도,3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention;

도 4a 내지 도 4c는 도 3a 내지 도 3c의 TEM사진.4A to 4C are TEM photographs of FIGS. 3A to 3C.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 게이트패턴21 semiconductor substrate 22 gate pattern

23, 23a, 23b : 감광막패턴23, 23a, 23b: photoresist pattern

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 셀할로 이온주입을 위한 감광막패턴 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a photosensitive film pattern for implanting cell halo of semiconductor devices.

반도체 소자의 고집적화에 따라 소자의 리프레시(Refresh)개선을 위한 리세스 게이트(Recess Gate)를 적용하여 비트라인노드(Bit Line Node)와 스토리지노드콘택노드(Storage Node Contact Node)간의 채널의 길이를 증가시켜 리프레시타임과 같은 전기적특성을 향상시키고 있으나, 고집적 디바이스로 갈수록 채널 증가의 한계에 부딪치면서 부분적인 소자의 이온주입에 의한 전기적 특성 향상방법을 적용하고 있다.Increased channel length between bit line node and storage node contact node by applying recess gate to improve refresh of semiconductor device due to high integration of semiconductor device In order to improve the electrical characteristics such as refresh time, however, as the high integration devices encounter the limit of channel increase, the method of improving the electrical characteristics by partial ion implantation is applied.

통상 게이트형성 전 이온주입을 통하여 반도체 기판 하부에 정션(Junction)을 형성하기 위해, 비트라인노드와 스토리지노드콘택노드의 이온주입을 하여 각각의 정션을 분리한다. 그러나, 후속 실리콘 형성을 비롯한 여러 열 공정에 의하여 분리된 정션간의 경계가 모호해지면서 각각의 정션간에 전자의 이동이 활성화되어 분리되어 있어야할 비트라인노드와 스토리지노드콘택노드 정션간의 누설전류(Leakage)가 발생한다. 상기 누설전류의 발생을 해결하기 위해, 게이트형성 후 비트라인노드에만 부분적으로 보론이온을 주입하여 이온배리어를 형성함으로써 분리된 정션간의 경계를 명확하게 한다.In general, in order to form a junction under the semiconductor substrate through ion implantation prior to gate formation, ionization of the bit line node and the storage node contact node is performed to separate each junction. However, as the boundary between the junctions separated by various thermal processes including subsequent silicon formation becomes blurry, the leakage current between the bitline node and the storage node contact node junction that must be separated by the movement of electrons between each junction is activated. Occurs. In order to solve the occurrence of the leakage current, the boundary between the separated junctions is made clear by forming an ion barrier by partially injecting boron ions only to the bit line node after the gate formation.

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1a에 도시된 바와 같이, 비트라인콘택노드부(BLC)와 스토리지노드콘택노드부(SNC)가 정의된 반도체 기판(11)에 게이트전극(12a)과 게이트하드마스크(12b) 가 순차로 적층된게이트패턴(12)을 형성한다. As shown in FIG. 1A, the gate electrode 12a and the gate hard mask 12b are sequentially stacked on the semiconductor substrate 11 on which the bit line contact node BLC and the storage node contact node SNC are defined. The gate pattern 12 is formed.

이어서, 게이트패턴(12) 사이를 채울때까지 감광막을 형성하고, 노광 및 현상으로 이온주입예정지역을 오픈시키는 감광막패턴(13)을 형성한다. 이때, 노광 및 현상시 오정렬(Misalign)이 발생하여 이온주입예정지역의 게이트패턴(12) 측벽에 감광막이 잔류(100)하고, 노광에너지가 부족하여 게이트패턴(12) 사이 하부에 감광막이 잔류(200)한다. Subsequently, a photoresist film is formed until the gap between the gate patterns 12 is filled, and a photoresist pattern 13 is formed to open a region to be ion implanted by exposure and development. At this time, misalignment occurs during exposure and development, so that the photoresist film remains on the sidewalls of the gate pattern 12 in the region where the ion implantation is expected, and the photoresist film remains on the lower portion between the gate patterns 12 due to insufficient exposure energy. 200).

도 1b에 도시된 바와 같이, 잔류하는 감광막(100, 200)을 제거하기 위한 추가식각을 실시한다. 이때, 측벽 및 하부에 잔류하는 감광막(100, 200)의 두께만큼 식각시간을 증가시켜야 하며 식각시간을 증가시키는 경우, 감광막패턴(13)에 의해 막혀있는 스토리지노드콘택 노드부 및 페리부분의 감광막패턴(13)이 손실되어 국부적인 이온주입시 배리어역할을 할 수 없는 높이(300)의 감광막패턴만 잔류(13a)하는 문제점이 있다. 이로 인해, 이온주입 외 지역인 스토리지노드콘택 노드부에 원치않는 이온주입(400)이 되어 소자 결함을 유발하는 문제점이 있다.As shown in FIG. 1B, additional etching is performed to remove the remaining photoresist films 100 and 200. At this time, the etching time should be increased by the thickness of the photoresist films 100 and 200 remaining on the sidewalls and the lower part. When the etching time is increased, the photoresist pattern of the storage node contact node part and the ferry part blocked by the photoresist pattern 13 is increased. (13) is lost, and there is a problem that only the photoresist layer pattern having a height 300 that cannot serve as a barrier during local ion implantation remains (13a). As a result, unwanted ion implantation 400 occurs in the storage node contact node portion outside the ion implantation, causing device defects.

도 2a 및 도 2b는 도 1a 및 도 1b의 TEM사진이다.2A and 2B are TEM photographs of FIGS. 1A and 1B.

도 2a를 참조하면, 오정렬로 인해 게이트패턴(12) 사이에 감광막패턴(13)이 균일하게 도포되지 못한 것을 알 수 있다. 이 상태에서 디스컴(Descum)을 실시할 경우 도 2b에 도시된 바와 같이, 패턴사이에 감광막패턴(13a)이 부족해진다.Referring to FIG. 2A, it can be seen that the photoresist pattern 13 is not uniformly applied between the gate patterns 12 due to misalignment. When the Descum is performed in this state, as illustrated in FIG. 2B, the photosensitive film pattern 13a is insufficient between the patterns.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 이온 주입을 위한 감광막패턴 형성시 오정렬과 노광에너지의 부족으로 인해 게이트패턴의 측벽 및 하부에 감광막이 잔류하여 이온주입시 배리어역할 하는 것을 방지하기 위한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above-described problems of the prior art, and when the photoresist pattern is formed for ion implantation, the photoresist film remains on the sidewalls and the lower part of the gate pattern due to misalignment and lack of exposure energy, thereby acting as a barrier for ion implantation. It is an object of the present invention to provide a method for manufacturing a semiconductor device for preventing the same.

본 발명에 의한 반도체 소자의 제조방법은 반도체 기판 상에 패턴을 형성하는 단계, 상기 패턴 사이의 이온주입영역이 오픈되도록 감광막을 패터닝하여 감광막패턴을 형성하는 단계, 상기 감광막패턴에 열공정을 실시하는 단계, 상기 패턴사이에 잔류하는 감광막패턴의 잔류물을 제거하는 단계를 포함하는 것을 특징으로 한다.The method of manufacturing a semiconductor device according to the present invention includes the steps of forming a pattern on a semiconductor substrate, patterning a photoresist film so as to open an ion implantation region therebetween, and forming a photoresist pattern, and performing a thermal process on the photoresist pattern. And removing residues of the photoresist pattern remaining between the patterns.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도 3a 내지 도 3c는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이고, 도 4a 내지 도 4c는 도 3a 내지 도 3c의 TEM사진이다. 설명의 편의를 돕기위해 함께 설명하기로 한다.3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and FIGS. 4A to 4C are TEM photographs of FIGS. 3A to 3C. The description will be made together for the convenience of explanation.

도 3a 및 도 4a에 도시된 바와 같이, 반도체 기판(21) 상에 게이트패턴(22)을 형성한다. 여기서, 반도체 기판(21)은 비트라인콘택 노드부(Bit Line Contact Node:BLC NODE)와 스토리지노드콘택 노드부(Storage Node Contact Node:SNC NODE)가 정의되고, 소자분리막과 웰(Well)을 포함하고 있다. 또한, 게이트패턴(22)은 게 이트전극(22a)과 게이트하드마스크(22b)가 순차로 적층된 구조로 형성한다. As shown in FIGS. 3A and 4A, the gate pattern 22 is formed on the semiconductor substrate 21. The semiconductor substrate 21 includes a bit line contact node (BLC NODE) and a storage node contact node (SNC NODE), and includes a device isolation layer and a well. Doing. In addition, the gate pattern 22 is formed in a structure in which the gate electrode 22a and the gate hard mask 22b are sequentially stacked.

이어서, 게이트패턴(22) 사이를 채울때까지 감광막을 형성하고, 노광 및 현상으로 이온주입예정지역을 오픈시키는 감광막패턴(23)을 형성한다. 이때, 감광막패턴(23)은 국부적인 이온주입을 위한 이온주입마스크로 라인형 패턴 또는 홀(Hole)형 패턴으로 형성하고, 감광막의 단일 증착 또는 감광막과 반사방지막(Organic Bottom Anti Reflect Coating:OBARC)의 이중층으로 형성한다.Subsequently, a photoresist film is formed until the gap between the gate patterns 22 is filled, and a photoresist pattern 23 is formed to open an ion implantation scheduled region by exposure and development. At this time, the photoresist pattern 23 is formed as a line-type pattern or a hole pattern as an ion implantation mask for local ion implantation, and a single deposition of the photoresist layer or a photoresist film and an organic bottom anti reflect coating (OBARC) It is formed into a double layer of.

여기서, 이온주입예정지역은 비트라인콘택 노드부(BLC)를 말한다. 이는, 게이트 형성 후, 비트라인콘택 노드부에만 부분적으로 보론 이온을 주입하여 이온배리어를 형성함으로써 분리된 정션간의 경계를 명확하게 하여 누설전류의 발생을 억제하기 위한 것이다. 상기와 같은 이온주입 공정을 셀할로(C-HALO) 이온주입이라고 한다.Here, the ion implantation scheduled region refers to the bit line contact node portion BLC. This is to prevent the generation of leakage current by clarifying the boundary between the separated junctions by forming the ion barrier by partially injecting boron ions only to the bit line contact node portion after the gate formation. Such ion implantation process is referred to as C-HALO ion implantation.

그러나, 상기 감광막패턴(23)의 형성을 위한 감광막의 노광 및 현상시 오정렬(Misalign)로 인해 게이트패턴(22)의 일부 측벽에 감광막이 잔류(300)한다. 또한, 노광에너지가 소자의 집적화로 인해 게이트패턴(22)의 하부까지 오픈을 하지 못하기 때문에 게이트패턴(22) 사이 하부에도 감광막이 잔류(400)한다.However, due to misalignment during exposure and development of the photoresist layer for forming the photoresist pattern 23, the photoresist layer remains on some sidewalls of the gate pattern 22. In addition, since the exposure energy does not open to the lower portion of the gate pattern 22 due to the integration of the device, the photoresist layer remains 400 between the gate patterns 22.

상기 잔류하는 감광막(300, 400)을 제거하기 위해 식각챔버 내부에서 웨이퍼의 이동없이 장비내의 바텀파워를 각각 다르게 인가한 등방성식각과 비등방성식각의 두단계 식각단계를 실시한다. 이하, 도 3b 및 도 3c에서 자세히 설명하기로 한다.In order to remove the remaining photoresist layers 300 and 400, a two-step etching step of isotropic etching and anisotropic etching is performed by applying bottom power in the equipment differently without moving wafers in the etching chamber. Hereinafter, the detailed description will be made with reference to FIGS. 3B and 3C.

도 3b 및 도 4b에 도시된 바와 같이, 감광막패턴(23)을 리플로우시킨다. 여 기서, 리플로우는 감광막패턴(23)이 게이트패턴(22) 사이에 균일한 높이를 갖도록 하기 위한 것으로, 온도가 서로 다른 두번의 열공정으로 실시한다. 특히, 열공정은 저온과 고온으로 온도가 서로 다른 열공정을 실시하되, 저온은 50℃∼100℃, 고온은 120℃∼150℃의 온도로 실시한다. 또한, 열공정은 베이크(Bake) 또는 큐어링(Curing)공정으로 실시한다.As shown in FIGS. 3B and 4B, the photoresist pattern 23 is reflowed. In this case, the reflow is performed so that the photoresist pattern 23 has a uniform height between the gate patterns 22. The reflow is performed by two thermal processes having different temperatures. In particular, the thermal process is a low temperature and a high temperature to perform a different temperature process, but the low temperature is carried out at a temperature of 50 ℃ to 100 ℃, high temperature 120 ℃ to 150 ℃. In addition, a thermal process is performed by the baking or curing process.

상기 두번의 열공정이 완료되는 시점에서, 게이트패턴(22)의 측벽에 형성된 감광막패턴(500)은 리플로우(Reflow)를 통해 게이트패턴(22) 사이에 균일한 높이로 형성된다.At the time when the two thermal processes are completed, the photoresist pattern 500 formed on the sidewall of the gate pattern 22 is formed to have a uniform height between the gate patterns 22 through reflow.

특히, 상기 베이크 또는 큐어링공정으로 인해 감광막패턴(23a)의 압축(Compressor)특성 강화로 게이트 리닝(Gate Leaning)강화 및 감광막패턴(23a)의 리플로우(Reflow)로 인한 게이트패턴(22)의 탑 어깨부(Top Shoulder)에 보강이 가능하다. In particular, due to the baking or curing process, the gate pattern 22 may be increased due to the enhancement of the gate leakage and the reflow of the photoresist pattern 23a due to the enhancement of the compression characteristic of the photoresist pattern 23a. Reinforcement is possible on the Top Shoulder.

도 3c 및 도 4c에 도시된 바와 같이, 게이트패턴(22) 사이에 잔류하는 감광막패턴 잔류물(600a)을 제거한다. 이러한 공정을 디스컴(Descum)공정이라 하고, 산소플라즈마로 실시한다.As shown in FIGS. 3C and 4C, the photoresist pattern residue 600a remaining between the gate patterns 22 is removed. This process is called a Descum process and is performed by oxygen plasma.

상기 디스컴공정으로, 게이트패턴(22)의 하부에 잔류하는 감광막(600a)이 모두 제거된다. 또한, 감광막(600a)의 제거를 위한 디스컴 공정시 감광막패턴(23a)이 일부 소실되지만 이온주입배리어로 사용하기 충분한 높이가 잔류(23b)한다.In the discom process, all of the photoresist film 600a remaining under the gate pattern 22 is removed. In addition, part of the photosensitive film pattern 23a is lost during the discom process for removing the photosensitive film 600a, but the height sufficient to be used as the ion implantation barrier remains 23b.

상기한 본 발명은, 셀할로 이온주입을 위한 감광막패턴 형성시 오정렬과 노광에너지 부족으로 인해 게이트패턴의 측벽 및 게이트패턴 사이의 하부에 잔류하는 감광막을 베이크 또는 큐어링공정으로 온도가 서로 다른 두번의 열공정을 차례로 실시하여 감광막패턴의 리플로우를 통해 오정렬이 발생한 감광막패턴을 제거하면서 게이트 리닝현상을 극대화한 후, 디스컴공정을 실시하여 이온주입예정지역을 완전히 오픈시킬 수 있는 장점이 있다.According to the present invention, the photosensitive film remaining at the lower side between the sidewall of the gate pattern and the gate pattern due to misalignment and lack of exposure energy when forming the photosensitive film pattern for implanting cell halo ions is subjected to two times of different temperatures. The thermal process may be performed in order to maximize the gate lining phenomenon by removing the photoresist pattern in which misalignment occurs through the reflow of the photoresist pattern, and then perform a decom process to completely open the ion implantation scheduled region.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 베이크 또는 큐어링공정으로 온도가 서로 다른 두번의 열공정을 차례로 실시하여 감광막패턴의 리플로우를 통해 오정렬이 발생한 감광막패턴을 제거하면서 게이트 리닝현상을 극대화한 후, 디스컴공정을 실시하여 이온주입예정지역을 완전히 오픈시켜서, 안정적인 국부적 이온주입을 가능하게 하는 효과가 있다.The present invention described above maximizes the gate lining phenomenon while removing the photoresist pattern in which misalignment occurs through the reflow of the photoresist pattern by sequentially performing two thermal processes having different temperatures in a baking or curing process, and then performing a decom process. In this way, the ion implantation scheduled area is completely opened, thereby enabling stable local ion implantation.

Claims (7)

반도체 기판 상에 패턴을 형성하는 단계;Forming a pattern on the semiconductor substrate; 상기 패턴 사이의 이온주입영역이 오픈되도록 감광막을 패터닝하여 감광막패턴을 형성하는 단계;Forming a photoresist pattern by patterning the photoresist to open the ion implantation region between the patterns; 상기 감광막패턴에 열공정을 실시하는 단계; 및Performing a thermal process on the photoresist pattern; And 상기 패턴사이에 잔류하는 감광막패턴의 잔류물을 제거하는 단계Removing residues of the photoresist pattern remaining between the patterns 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 열공정은 온도가 서로 다른 두번의 열공정을 실시하여 상기 감광막패턴을 리플로우시키는 것을 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The thermal process is a method of manufacturing a semiconductor device, characterized in that to perform reflow of the photosensitive film pattern by performing two thermal processes having different temperatures. 제2항에 있어서,The method of claim 2, 상기 열공정은,The thermal process, 저온과 고온의 열공정을 차례로 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, characterized in that the low-temperature and high-temperature thermal process are performed in sequence. 제3항에 있어서,The method of claim 3, 상기 저온은 50℃∼100℃으로, 고온은 120℃∼150℃의 온도에서 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The low temperature is 50 ℃ to 100 ℃, the high temperature is carried out at a temperature of 120 ℃ to 150 ℃ manufacturing method of a semiconductor device. 제1항 내지 제4항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 4, 상기 열공정은,The thermal process, 베이크(Bake) 또는 큐어링(Curing)공정으로 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, characterized in that it is carried out by a baking or curing process. 제1항에 있어서,The method of claim 1, 상기 감광막패턴은 감광막 단일증착 또는 감광막과 반사방지막(OBARC)의 이중층으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The photoresist pattern is a method of manufacturing a semiconductor device, characterized in that the photoresist is formed by a single layer or a double layer of the photoresist and the anti-reflection film (OBARC). 제1항에 있어서,The method of claim 1, 상기 패턴사이에 잔류하는 감광막패턴의 잔류물을 제거하는 단계는,Removing residues of the photoresist pattern remaining between the patterns, 산소플라즈마로 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, characterized in that it is carried out by oxygen plasma.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9613811B2 (en) 2013-12-06 2017-04-04 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9613811B2 (en) 2013-12-06 2017-04-04 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices

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