CN101364544B - Light doping section, source/drain section forming method and membrane graphic method - Google Patents
Light doping section, source/drain section forming method and membrane graphic method Download PDFInfo
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- CN101364544B CN101364544B CN200710044803A CN200710044803A CN101364544B CN 101364544 B CN101364544 B CN 101364544B CN 200710044803 A CN200710044803 A CN 200710044803A CN 200710044803 A CN200710044803 A CN 200710044803A CN 101364544 B CN101364544 B CN 101364544B
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Abstract
A method for forming a lightly doped region comprises the following steps: forming a grid electrode on a semiconductor substrate; cleaning the semiconductor substrate, on which the grid electrode is formed; carrying out heat treatment to the cleaned semiconductor substrate; forming a patterned resist etchant layer on the semiconductor substrate which is subjected to heat treatment, wherein the patterned resist etchant layer covers a part of the semiconductor substrate to expose the surface of a lightly doped region of the semiconductor substrate; and carrying out an ion implantation operation with the patterned resist etchant layer and the grid electrode as a mask. The invention also provides a method for forming a source/drain region and a film patterning method, which both can optimize the patterning effect of the resist etchant layer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of light doping section, source/drain region formation method and membrane graphic method.
Background technology
Light doping section comprises the lightly doped drain injection, and (Lightly Doped Drain, LDD) district and pocket type (Pocket) ion implanted region, described light doping section are used to define the leakage expansion area, source of MOS device.LDD impurity is positioned at the grid below and is close to the channel region edge, and Pocket impurity is positioned at below, LDD district and is close to the channel region edge, is source-drain area the impurity concentration gradient is provided.
Usually use ion injection method and form described light doping section.It is the standard technique of the dopant material that changes conductance being introduced Semiconductor substrate that ion injects.In ion implant systems, needed dopant material is ionized in ion source, ion is accelerated into the surface that is drawn towards Semiconductor substrate behind the ion beam with predetermined energy, and the energetic ion in the ion beam is infiltrated semi-conducting material and is mounted among the lattice of semi-conducting material.
Current, the step that forms described light doping section comprises: as shown in Figure 1, form grid 20 on Semiconductor substrate 10; Cleaning forms the described Semiconductor substrate 10 behind the grid 20; As shown in Figure 2, form patterned resist layer 30 on the described Semiconductor substrate 20 after the cleaning, the described Semiconductor substrate 10 in described patterned resist layer 30 cover parts is to expose the light doping section surface of described Semiconductor substrate 10; As shown in Figure 3, be mask with described patterned resist layer and described grid, carry out the ion implant operation, to form described light doping section 40.
Obviously, answer the described semiconductor-based end of expose portion between patterned resist layer and the described grid,, form light doping section to carry out the ion implant operation at exposed region.Yet; actual production is found; size interval hour between resist layer and grid; the size of described exposed region is understood the off-design value usually,, has not removed deposit in the described exposed region that is; when serious; as shown in Figure 4, even between resist layer and grid, form bridge joint (bridge) defective 32, influence the carrying out of follow-up ion implant operation.
On April 27th, 2005, disclosed publication number provided a kind of method that removes resist layer after the metal level etching in the Chinese patent application of " CN1610079 ", by adding a plasma etching processing procedure after removing the resist layer processing procedure in traditional dry type, to quicken to remove deposit and the metal residue that is positioned on the metal sidewall, and then can reduce wet type and remove the processing procedure required time, and can reduce the generation of micro-lithography phenomenon.That is, described method is by increasing the deposit between plasma etching processing procedure removal metal layer image.Yet actual production finds that when utilizing said method to remove the deposit that forms bridge joint between resist layer and grid, removal effect is limited, and needs to increase by a plasma etching processing procedure, has both made process complications, easily causes the gate surface damage again.
Summary of the invention
The invention provides a kind of light doping section formation method, can optimize the graphical effect of resist layer.
A kind of light doping section formation method provided by the invention comprises:
On Semiconductor substrate, form grid;
Cleaning forms the described Semiconductor substrate behind the grid;
Described Semiconductor substrate after cleaning is carried out heat treatment operation;
Form patterned resist layer on the described Semiconductor substrate behind the experience heat treatment operation, the described Semiconductor substrate in described patterned resist layer cover part is to expose the light doping section surface of described Semiconductor substrate;
With described patterned resist layer and described grid is mask, carries out the ion implant operation.
Alternatively, the temperature range of described heat treatment operation is 100～400 degrees centigrade; Alternatively, the temperature range of described heat treatment operation is 150～180 degrees centigrade; Alternatively, the described heat treatment operation duration is 60～100 seconds.
One provenance provided by the invention/drain region formation method comprises:
On the semiconductor-based end, form grid;
Formation is around the side wall of described grid;
Cleaning forms the described semiconductor-based end behind the side wall;
To carrying out heat treatment operation in the described semiconductor-based end after cleaning;
On the described semiconductor-based end behind the experience heat treatment operation, form patterned resist layer, the described semiconductor-based end, described patterned resist layer cover part, inject the surface with the ion that exposes the described semiconductor-based end;
With described patterned resist layer, described grid and described side wall is mask, carries out the ion implant operation.
Alternatively, the temperature range of described heat treatment operation is 100～400 degrees centigrade; Alternatively, the temperature range of described heat treatment operation is 150～180 degrees centigrade; Alternatively, the described heat treatment operation duration is 60～100 seconds.
A kind of membrane graphic method provided by the invention comprises:
Semiconductor substrate is provided, and described semiconductor-based surface has rete;
Clean the described semiconductor-based end;
Semiconductor substrate after cleaning is carried out heat treatment operation;
On the semiconductor substrate after the heat treatment, form patterned photoresist layer;
With described patterned photoresist layer is mask, graphical described rete.
Alternatively, the temperature range of described heat treatment operation is 100～400 degrees centigrade; Alternatively, the temperature range of described heat treatment operation is 150～180 degrees centigrade; Alternatively, the described heat treatment operation duration is 60～100 seconds.
Compared with prior art, the present invention has the following advantages:
Light doping section formation method provided by the invention, by before forming patterned resist layer, increase heat treatment step, to remove the residual cleaning solution of aforementioned cleaning process, then strengthen the exposure effect of resist layer, and then make the graphical effect that improves resist layer become possibility;
Source/drain region provided by the invention formation method, by before forming patterned resist layer, increase heat treatment step, to remove the residual cleaning solution of aforementioned cleaning process, then strengthen the exposure effect of resist layer, and then make the graphical effect that improves resist layer become possibility;
Membrane graphic method provided by the invention, by before forming resist layer, increase heat treatment step, to remove the residual cleaning solution of aforementioned cleaning process, then strengthen the exposure effect of resist layer, and then make the graphical effect that improves resist layer become possibility.
Description of drawings
Fig. 1 is the structural representation after forming grid on the Semiconductor substrate in the explanation prior art;
Fig. 2 is the structural representation after forming patterned resist layer on the Semiconductor substrate in the explanation prior art;
Fig. 3 is for illustrating the structural representation behind the formation light doping section in the prior art;
Fig. 4 is for forming the structural representation of bridge defects in the explanation prior art;
Fig. 5 is the structural representation after forming grid on the Semiconductor substrate of the explanation embodiment of the invention;
Fig. 6 is the structural representation after forming patterned resist layer on the Semiconductor substrate of the explanation embodiment of the invention;
Fig. 7 forms structural representation after the Semiconductor substrate of grid thereon for the cleaning of the explanation embodiment of the invention;
Fig. 8 is the structural representation after the Semiconductor substrate to after cleaning of the explanation embodiment of the invention is carried out heat treatment operation;
Fig. 9 is the structural representation after forming patterned resist layer on the Semiconductor substrate of the explanation embodiment of the invention;
Figure 10 for the explanation embodiment of the invention the formation light doping section after structural representation.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work for those skilled in the art with advantage of the present invention.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Use method provided by the invention, the step that forms light doping section comprises: form grid on Semiconductor substrate; Cleaning forms the described Semiconductor substrate behind the grid; Described Semiconductor substrate after cleaning is carried out heat treatment operation; Form patterned resist layer on the described Semiconductor substrate behind the experience heat treatment operation, the described Semiconductor substrate in described patterned resist layer cover part is to expose the light doping section surface of described Semiconductor substrate; With described patterned resist layer and described grid is mask, carries out the ion implant operation.
In the presents, described light doping section comprises lightly doped drain injection region and pocket type ion implanted region.
As shown in Figure 5, use method provided by the invention, the concrete steps that form light doping section comprise:
Step 501: as shown in Figure 6, on Semiconductor substrate 100, form grid 120.
In the presents, described Semiconductor substrate 100 defined device active region and finished shallow trench isolation from.Described Semiconductor substrate 100 surfaces can have oxide layer, and described oxide layer is the separator of 100 of described grid 120 and described Semiconductor substrate, are again to carry out the injury-free protective layer of the described Semiconductor substrate of protection in the light doping section forming process 100.Described oxide layer can obtain via thermal oxidation technology.Described thermal oxidation technology can use high-temperature oxydation equipment or oxidation furnace carries out.Described oxide layer comprises silicon dioxide, hafnium doped silica or hafnium oxide (HfO
2).
Comprise in the step that forms grid 120 on the described Semiconductor substrate 100: deposition grid layer 120 on described Semiconductor substrate 100; Form patterned resist layer, described patterned resist layer has gate patterns; With described patterned resist layer is mask, and the described grid layer of etching is to form grid 120.Described grid layer comprises the polysilicon or the metal of polysilicon, doping.Described grid layer also can comprise metal silicide.Described metal silicide experiences annealing process then and obtains by depositing metal layers on polysilicon.Described metal silicide comprises tungsten silicide etc.
Step 502: as shown in Figure 7, cleaning forms the described Semiconductor substrate 100 behind the grid 120.
Usually, the cleaning solution that described cleaning operation is selected for use comprises SC1 (mixed solution of hydrogen peroxide, ammoniacal liquor and deionized water), or ST-250 etc.After cleaning operation was finished, described Semiconductor substrate 100 surfaces behind the formation grid 120 are the described cleaning solution 200 of residual fraction still.
Step 503: as shown in Figure 8, the described Semiconductor substrate after cleaning is carried out heat treatment operation.
The present inventor thinks after analyzing, above-mentioned dimensional discrepancy and bridge defects be because: after carrying out described cleaning operation, cleaning solution arranged in that described semiconductor substrate surface is residual, and described cleaning solution is generally alkaline solution, the acid ingredient that causes residual described cleaning solution will neutralize and comprise after the part resist layer exposure, cause the exposure figure in the resist layer to change, that is, have not removed resist layer between patterned resist layer and grid.
The present inventor thinks after analyzing that behind described cleaning operation, the removal effect that strengthens the residual cleaning solution of semiconductor substrate surface becomes the direction of optimizing the graphical effect of follow-up resist layer.
The present inventor's undergoing analysis proposes with the practice back, described Semiconductor substrate after cleaning is carried out heat treatment operation, can strengthen the effect of the cleaning solution of removing described Semiconductor substrate 102 surfaces and grid 122 remained on surface, and then can make the graphical effect of the follow-up resist layer of optimization become possibility.
The temperature range of described heat treatment operation is: 100～400 degrees centigrade, be preferably 150～180 degrees centigrade, and can strengthen the uniformity that described Semiconductor substrate is heated; The described heat treatment operation duration is: 60～100 seconds, can strengthen uniformity and stability that described Semiconductor substrate is heated.Described heat treatment operation can carry out under nitrogen or helium atmosphere.
By before forming patterned resist layer, increase heat treatment step, to remove the residual cleaning solution of aforementioned cleaning process, can strengthen the exposure effect of resist layer, and then make the graphical effect that improves resist layer become possibility.
Step 504: as shown in Figure 9, on the described Semiconductor substrate 102 behind the experience heat treatment operation, form patterned resist layer 140, the described Semiconductor substrate in described patterned resist layer cover part is to expose the light doping section surface of described Semiconductor substrate.
In the practice, the step that forms patterned resist layer comprises steps such as the coating of described resist layer, oven dry, photoetching, exposure and detection, related process can be used various traditional methods, the described resist layer of using can be selected any anticorrosive additive material that can be applicable in the manufacture of semiconductor for use, all repeats no more at this.
Step 505: with described patterned resist layer 140 and described grid 122 is mask, carries out the ion implant operation.The light doping section 160 that forms as shown in figure 10.
Especially, use method provided by the invention, also can form source/drain region, comprising: the semiconductor-based end is provided, has grid at described the semiconductor-based end; Formation is around the side wall of described grid; Cleaning forms the described semiconductor-based end behind the side wall; To carrying out heat treatment operation in the described semiconductor-based end after cleaning; On the described semiconductor-based end behind the experience heat treatment operation, form patterned resist layer, the described semiconductor-based end, described patterned resist layer cover part, inject the surface with the ion that exposes the described semiconductor-based end; With described patterned resist layer, described grid and described side wall is mask, carries out the ion implant operation.
On Semiconductor substrate, form grid, and form the described semiconductor-based end after forming light doping section then.Described side wall comprises silicon dioxide.
Usually, the cleaning solution selected for use of described cleaning operation comprises SC1 or ST-250 etc.
The temperature range of described heat treatment operation is: 100～400 degrees centigrade, be preferably 150～180 degrees centigrade, and can strengthen the uniformity that described Semiconductor substrate is heated; The described heat treatment operation duration is: 60～100 seconds, can strengthen uniformity and stability that described Semiconductor substrate is heated.Described heat treatment operation can carry out under nitrogen or helium atmosphere.
It should be noted that because integrated circuit is to finish specific function by the rete that piles up in a large number, the figure that different described retes pass through to form is to form the film stack structure within it.Usually, the step of formation figure comprises in rete: semiconductor substrate is provided, and described semiconductor-based surface has rete; Clean the described semiconductor-based end; On the semiconductor substrate after the cleaning, form patterned photoresist layer; With described patterned photoresist layer is mask, graphical described rete.
On the semiconductor-based end, form source region and drain region and then deposit first interlayer dielectric layer and (be before-metal medium layer, PMD), and after forming through hole (via) or groove (trench), form described semiconductor substrate.
In addition, after forming source region and drain region at semiconductor-based the end and then depositing first interlayer dielectric layer, continue to form ground floor through hole and groove; Then, deposit second interlayer dielectric layer, and after forming through hole or groove, still can form described semiconductor substrate.
Can expand ground, behind deposition N-1 interlayer dielectric layer, form N-1 layer through hole and groove, continue deposition N interlayer dielectric layer, and after forming through hole or groove, form described semiconductor substrate.
Obviously, the number N of the described interlayer dielectric layer that comprises in goods can be any natural number, and as 1,3,5,7 or 9 etc., the concrete number of the described interlayer dielectric layer that comprises in goods is determined according to product requirement.
Before deposition N interlayer dielectric layer, can comprise the step on the barrier layer that forms cover gate and side wall.Described rete promptly refers to above-mentioned dielectric layer.Usually, the cleaning solution selected for use of described cleaning operation comprises SC1 or ST-250 etc.
In the practice,, especially reduce to after 65 nanometers even the following technology, still may have deviation value between the graphical effect of described rete and the design load, in other words, produce the photoresist intoxicating phenomenon when critical dimension along with dwindling of critical dimension.
The present inventor thinks after analyzing, above-mentioned photoresist intoxicating phenomenon be still because: after carrying out described cleaning operation, at described semiconductor substrate remained on surface cleaning solution is arranged, described cleaning solution is generally alkalescence, the acid ingredient that residual described cleaning solution will neutralize and comprise after the part resist layer exposes, cause the exposure figure in the resist layer to change, that is, have not removed resist layer in the described exposed region.
The present inventor thinks after analyzing that behind described cleaning operation, the removal effect that strengthens the cleaning solution of described semiconductor substrate remained on surface becomes the direction of optimizing the graphical effect of follow-up resist layer.
The present inventor's undergoing analysis proposes with the practice back, described semiconductor substrate after cleaning is carried out heat treatment operation, can strengthen the effect of the cleaning solution of removing described semiconductor substrate remained on surface, and then can make the graphical effect of the follow-up resist layer of optimization become possibility.
Use method provided by the invention, the step that forms figure in rete comprises: semiconductor substrate is provided, and described semiconductor-based surface has rete; Clean the described semiconductor-based end; Semiconductor substrate after cleaning is carried out heat treatment operation; On the semiconductor substrate after the heat treatment, form patterned photoresist layer; With described patterned photoresist layer is mask, graphical described rete.
The temperature range of described heat treatment operation is: 100～400 degrees centigrade, be preferably 150～180 degrees centigrade, and can strengthen the uniformity that described Semiconductor substrate is heated; The described heat treatment operation duration is: 60～100 seconds, can strengthen uniformity and stability that described Semiconductor substrate is heated.Described heat treatment operation can carry out under nitrogen or helium atmosphere.
What need emphasize is that not elsewhere specified step all can use conventional methods acquisition, and concrete technological parameter is determined according to product requirement and process conditions.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (8)
1. a light doping section formation method is characterized in that, comprising:
On Semiconductor substrate, form grid;
Cleaning forms the described Semiconductor substrate behind the grid;
Described Semiconductor substrate after cleaning is carried out heat treatment operation;
Form patterned resist layer on the described Semiconductor substrate behind the experience heat treatment operation, the described Semiconductor substrate in described patterned resist layer cover part is to expose the light doping section surface of described Semiconductor substrate;
With described patterned resist layer and described grid is mask, carries out the ion implant operation.
2. light doping section formation method according to claim 1 is characterized in that: the temperature range of described heat treatment operation is 100～400 degrees centigrade.
3. light doping section formation method according to claim 1 is characterized in that: the temperature range of described heat treatment operation is 150～180 degrees centigrade.
4. light doping section formation method according to claim 1 is characterized in that: the described heat treatment operation duration is 60～100 seconds.
5. one provenance/drain region formation method is characterized in that, comprising:
On the semiconductor-based end, form grid;
Formation is around the side wall of described grid;
Cleaning forms the described semiconductor-based end behind the side wall;
To carrying out heat treatment operation in the described semiconductor-based end after cleaning;
On the described semiconductor-based end behind the experience heat treatment operation, form patterned resist layer, the described semiconductor-based end, described patterned resist layer cover part, inject the surface with the ion that exposes the described semiconductor-based end;
With described patterned resist layer, described grid and described side wall is mask, carries out the ion implant operation.
6. source/drain region according to claim 5 formation method is characterized in that: the temperature range of described heat treatment operation is 100～400 degrees centigrade.
7. source/drain region according to claim 5 formation method is characterized in that: the temperature range of described heat treatment operation is 150～180 degrees centigrade.
8. source/drain region according to claim 5 formation method is characterized in that: the described heat treatment operation duration is 60～100 seconds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710044803A CN101364544B (en) | 2007-08-09 | 2007-08-09 | Light doping section, source/drain section forming method and membrane graphic method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710044803A CN101364544B (en) | 2007-08-09 | 2007-08-09 | Light doping section, source/drain section forming method and membrane graphic method |
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| Publication Number | Publication Date |
|---|---|
| CN101364544A CN101364544A (en) | 2009-02-11 |
| CN101364544B true CN101364544B (en) | 2010-05-19 |
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| CN200710044803A Expired - Fee Related CN101364544B (en) | 2007-08-09 | 2007-08-09 | Light doping section, source/drain section forming method and membrane graphic method |
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|---|---|
| CN (1) | CN101364544B (en) |
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2007
- 2007-08-09 CN CN200710044803A patent/CN101364544B/en not_active Expired - Fee Related
Non-Patent Citations (2)
| Title |
|---|
| JP特开平2-10839A 1990.01.16 |
| JP特开昭62-147748A 1987.07.01 |
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