KR20080000978A - Gateline layout on the semiconductor device - Google Patents

Abstract

A gate line layout of a photo mask is provided to enhance the yield of a semiconductor device by securing uniformly a line width of a gate line having a narrow line width and interval due to an optical proximity effect in an exposure process. A plurality of gate lines(102) having a predetermined line width are arranged in a constant interval on a substrate including an isolation layer such as an STI layer for defining an active region(100) and an inactive region. Three or more dummy line patterns(108) are arranged in the inactive region corresponding to left and right edge regions of the gate lines. The dummy line patterns have the same line width and interval as the line width and interval of the gate lines. An insulating material is formed on sidewalls of the gate lines and the dummy line patterns. A source/drain region is formed within the active region exposed by the gate lines and a spacer.

Description

Gate line layout of photomask {Gateline layout on the semiconductor device}

1 is a plan view showing a gate line layout structure of a photomask according to the prior art.

FIG. 2 is a graph comparing line widths CD of gate lines cut by the line D-D ′ of FIG. 1.

3 is a plan view illustrating a layout structure in which a dummy pattern is added to a gate line of a photomask according to the prior art.

4 is a plan view illustrating a gate line layout structure of a photomask according to the present invention.

5A and 5B are plan views illustrating the gate line layout of the photomask according to the present invention, and graphs comparing line widths of the gate lines of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: active region 102: gate line

104: contact 108: dummy line pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a gate line layout of a photomask, which can greatly reduce the line width difference due to the fine line width (CD) of the gate line due to the high integration of the semiconductor device.

Photomasks for photolithography include geometrically shaped patterns corresponding to circuit components integrated onto a silicon wafer. The patterns used to create these photo masks are generated using computer-aided design (CAD) programs. Most CAD programs follow a set of predetermined design rules to create a functional mask. For example, design rules define space tolerances between circuit elements such as gates, capacitors, or wiring lines, such that the circuit elements or lines do not interact with each other in an undesirable manner.

By the way, in the photolithography process, the pattern of the photo mask should be faithfully reproduced on the wafer as it is. As the circuit size is reduced due to the high integration of semiconductor elements, the pattern density increases while the line width (CD) of the pattern is the resolution of the exposure apparatus. The limit is approaching.

Furthermore, due to the high integration of semiconductor elements, the diffraction of light due to the resolution of the exposure apparatus, the optical proximity effect, and the like, the line widths of the gate lines having close pattern intervals become uneven.

1 is a plan view showing a gate line layout structure of a photomask according to the prior art.

As shown in FIG. 1, the gate line of the photomask according to the related art pitches a predetermined gap on an upper portion of the substrate where the active region 10 and the inactive region are separated by an isolation layer such as shallow trench isolation (STI). ) And a plurality of gate lines 12 having a predetermined line width.

Although not shown, a spacer (not shown) made of an insulating material, for example, a silicon nitride film, is disposed on the sidewall of the gate line 12, and the active region 10 of the substrate exposed by the gate line 12 and the spacer is disposed. The source / drain regions (not shown) are disposed in the figure.

The contact electrodes 14 vertically connected to the source / drain regions are separated and disposed in an island form through the contact holes of the interlayer insulating layer (not shown) formed on the front surface of the substrate including the gate line 12 and the spacer. It is.

FIG. 2 is a graph comparing line widths CD of gate lines cut by the line D-D ′ of FIG. 1.

As shown in FIG. 2, when the exposure process is performed using the plurality of gate lines 12 (1 to 8) in the photo mask, the gate lines 3 to 6 inside the active region are caused by the optical proximity effect. Has a uniform line width (CD), but gate lines (1-2, 7-8) outside the active region have non-uniform line width (CD).

As a result, the line widths CD of the outer gate lines 1 to 2 and 7 to 8 are larger than the line widths CD of the inner gate lines 3 to 6.

Due to the optical proximity effect of the exposure process, the line width (CD) difference of the gate line which is non-uniformly patterned on the wafer can be improved through the Optical Proximity Correction (OPC) method, but the line width change for each line continues to exist. Done.

3 is a plan view illustrating a layout structure in which a dummy pattern is added to a gate line of a photomask according to the prior art.

As shown in FIG. 3, when the dummy pattern by the OPC method is applied to improve the line width non-uniformity of the gate line of the photo mask, the dummy line patterns 16 are respectively formed at the left and right edge regions of the plurality of gate lines. Was placed.

However, since the dummy line pattern 16 disposed on the gate line of the conventional photo mask is asymmetrically arranged to have different line widths (CD) and pitches on the left and right sides, the outside of the active region patterned on the wafer. The gate line also has asymmetrical line width (CD), which is why it is difficult to reduce the change of the line width (CD) of the gate line.

SUMMARY OF THE INVENTION An object of the present invention is to add a dummy line pattern equal to the gate line line width and spacing to the left and right edge regions of a plurality of gate lines on a photo mask, respectively, in order to solve the problems of the prior art. It is to provide a gate line layout of a photo mask that can keep the line widths of a plurality of gate lines uniform.

In order to achieve the above object, the present invention provides a photomask having a gate line, comprising: a plurality of gate lines and a plurality of inactive regions, each of which has a predetermined spacing and line width, respectively, on an upper portion of a substrate where an active region and an inactive region are separated; Dummy line patterns are disposed in the left and right edge regions of the gate lines to have the same line width and spacing as the gate line line width and spacing.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view illustrating a gate line layout structure of a photomask according to the present invention.

As shown in FIG. 4, the photo mask according to the present invention has a predetermined line width and a predetermined line width 101 on the substrate on which a device isolation film such as STI is formed to distinguish the active region 100 from the inactive region. A plurality of gate lines 102 with CD) are arranged.

The photomask of the present invention has the same line width as the gate line line width CD and the gap 101 which are disposed in the active region 100 in the inactive regions that are the left and right edge regions of the gate lines 102. And at least three dummy line patterns 108 having a CD) and a spacing 110.

Although not shown in the drawings, a spacer (not shown) is formed on the sidewall of the gate line 102 and the dummy line pattern 108 with an insulating material, for example, a silicon nitride film, and a plurality of gate lines 102 and the spacer Source / drain regions (not shown) are disposed in the active region 100 of the substrate exposed.

In addition, a contact electrode 106 vertically connected to a source / drain region is formed through a contact hole of an interlayer insulating layer (not shown) formed on the front surface of the substrate including the gate line 102, the dummy line pattern 108, and the spacer. The islands are separated and arranged.

Therefore, the gate lines of the photomask according to the present invention are dummy equal to the gate line line width CD and the spacing 101 of the active region 100 in the inactive regions that are the left and right edge regions of the gate lines 102. By arranging the line pattern 108 to have a line width CD and an interval 110, the outer portion of the gate line 102 and the inner portion of the gate line 102 having a fine line width and spacing due to the optical proximity effect during the exposure process. This prevents asymmetrical patterning with different linewidth sizes.

In the method of manufacturing a semiconductor device to which the present invention is applied, a device isolation film such as STI is formed on a silicon substrate to distinguish between the active region 100 and the inactive region of the device.

Then, a conductive material, for example, doped polysilicon is deposited on the semiconductor substrate on which the device isolation layer is formed, and the doped polysilicon is patterned by performing a photo (exposure, development) and etching process using a photomask according to the present invention. Left and right edges of the plurality of gate lines 102 are formed while forming a plurality of gate lines 102 having a predetermined distance 101 and having a predetermined line width CD on the active region 100. At least three dummy line patterns 108 having the same line width CD and the spacing 110 as the gate line line width CD and the spacing 101 of the active region 100 are formed in the non-active region.

A plurality of gate lines 102 are then formed on the sidewalls of the gate line 102 and the dummy line pattern 108 with an insulating material, for example, a silicon nitride film, and disposed in the active region 100. And source / drain regions (not shown) in the active region 100 of the substrate exposed by the spacers.

An interlayer insulating film (not shown) is formed on the entire surface of the substrate including the gate line 102, the dummy line pattern 108, and the spacers, and the contact electrode 106 is vertically connected to the source / drain regions through the contact hole of the interlayer insulating film. ).

5A and 5B are a plan view illustrating the gate line layout of the photomask according to the present invention and a line width of the gate line of the present invention, and FIG. 5B is a gate line cut by the line E-E ′ of FIG. 5. This is a graph comparing their line width (CD).

As shown in FIG. 5A, the photomask of the present invention has a plurality of gate lines 1 to 8 and dummy line patterns A, B, and C (A ', B', and C ') having the same line width and spacing. It is arranged to have.

As shown in FIG. 5B, when the photo (exposure) process using the photo mask of the present invention is performed, the gate lines 1 to 8 patterned in the active region of the wafer have a uniform line width (CD), but the inactive region. The outer dummy line patterns A, B, C (A ', B', C ') patterned in have a non-uniform line width CD compared to the gate lines 1-8 of the active region.

Thus, the dummy line patterns A, B, C (A ', B', C ') of the photomask have gate lines in the active region instead of having non-uniform line width CD by the optical proximity effect of the exposure process. All of (1-8) have a uniform line width (CD).

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

As described above, the present invention provides a plurality of gates disposed in the active region by adding at least three dummy line patterns having the same gate line line width and spacing, respectively, to the left and right edge regions of the plurality of gate lines of the photomask. The line widths of the lines can be kept uniform.

Therefore, the present invention can ensure the line width of the gate line having a narrow line width and spacing uniformly due to the optical proximity effect of the exposure process, thereby improving the yield of manufacturing a semiconductor device.

Claims (2)

In a photo mask having a gate line, A plurality of gate lines disposed on the substrate, each having an active region and an inactive region separated therefrom, with a predetermined spacing and line width; And And a dummy line pattern disposed at left and right edge regions of the plurality of gate lines of the non-active region, the dummy line patterns having the same line width and spacing as the gate line line width and spacing, respectively. The gate line layout of claim 1, wherein the dummy line pattern comprises at least three line patterns.

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