TWI521369B - Layout decomposition method and method for manufacturing semiconductor device applying the same - Google Patents

Layout decomposition method and method for manufacturing semiconductor device applying the same Download PDF

Info

Publication number
TWI521369B
TWI521369B TW101142464A TW101142464A TWI521369B TW I521369 B TWI521369 B TW I521369B TW 101142464 A TW101142464 A TW 101142464A TW 101142464 A TW101142464 A TW 101142464A TW I521369 B TWI521369 B TW I521369B
Authority
TW
Taiwan
Prior art keywords
regions
mask
substrate
dense
pattern
Prior art date
Application number
TW101142464A
Other languages
Chinese (zh)
Other versions
TW201419019A (en
Inventor
童宇誠
Original Assignee
聯華電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聯華電子股份有限公司 filed Critical 聯華電子股份有限公司
Priority to TW101142464A priority Critical patent/TWI521369B/en
Publication of TW201419019A publication Critical patent/TW201419019A/en
Application granted granted Critical
Publication of TWI521369B publication Critical patent/TWI521369B/en

Links

Description

佈局分割方法及應用其之半導體元件製造方法 Layout segmentation method and semiconductor component manufacturing method using same

本發明是有關於一種佈局分割方法及應用其之半導體元件製造方法,且特別是有關於一種包括識別具奇數特徵物和偶數特徵物之區域之佈局分割方法,以及應用此佈局分割方法於雙重曝光後可形成奇數特徵物和偶數特徵物之半導體元件製造方法。 The present invention relates to a layout segmentation method and a semiconductor device manufacturing method using the same, and more particularly to a layout segmentation method including identifying regions having odd and even features, and applying the layout segmentation method to double exposure A method of fabricating a semiconductor device in which an odd feature and an even feature are formed.

隨著持續縮小的電子裝置尺寸,其特徵物如電子裝置上的積體電路也隨著越做越小。特徵物的細微間距及其圖形必須要能滿足小尺寸電子裝置的要求。然而,特徵物日益縮小的間距及其圖形增加了元件製作的難度。因此,特徵物的尺寸也受限於傳統製程技術上的限制,如欲利用目前黃光製程技術要達到非常小的最小間距可能導致特徵物無法穩定地形成。一般來說,欲於基板上增加更小尺寸的特徵物,其係受限於黃光製程中用來曝光的光線波長和光學系統是否能準確地投射相關圖案之影像。一般當k1值(製程相關參數之無因次係數)低於0.35,其黃光製程產率逐漸下降成本也逐漸增加。當k1值低於0.28單次曝光已不可行,一般會使用雙重曝光來形成一應用半導體元件中較細微的特徵物和較大特徵物。 As the size of the electronic device continues to shrink, the features such as the integrated circuit on the electronic device become smaller and smaller. The fine pitch of the features and their graphics must meet the requirements of small-sized electronic devices. However, the ever-decreasing spacing of features and their graphics increases the difficulty of component fabrication. Therefore, the size of the feature is also limited by the limitations of the conventional process technology. To achieve a very small minimum pitch by using the current yellow light process technology, the feature may not be stably formed. In general, the desire to add smaller sized features to a substrate is limited by the wavelength of the light used to expose the yellow light process and whether the optical system accurately projects the image of the associated pattern. Generally, when the k1 value (the dimensionless coefficient of the process-related parameters) is lower than 0.35, the yellow light process yield gradually decreases and the cost also gradually increases. When a single exposure of k1 values below 0.28 is not feasible, double exposure is typically used to form finer features and larger features in an applied semiconductor component.

再者,其他技術如特徵物數倍增技術(pitch doubling technique)也被提出用來延伸黃光製程的能力,使黃光製程所能達到的最小間距更為縮小,如此可使半導體元件如 基板的一區域中所形成的特徵物數量加倍。然而,依照倍增技術所形成的特徵物數量為偶數,因此在製程上對於需要奇數特徵物的區域會有問題。 Furthermore, other techniques such as the pitch doubling technique have also been proposed to extend the ability of the yellow light process to minimize the minimum pitch that can be achieved by the yellow light process, thus enabling semiconductor components such as The number of features formed in a region of the substrate is doubled. However, the number of features formed according to the multiplication technique is an even number, so there is a problem in the process for areas requiring odd features.

本揭露係有關於一種佈局分割方法及應用其之半導體元件製造方法。本揭露之佈局分割方法包括了識別具奇數特徵物和偶數特徵物之區域之步驟。應用此佈局分割方法可簡單且順利地將奇數特徵物和偶數特徵物之圖案轉移至半導體元件。 The present disclosure relates to a layout dividing method and a semiconductor device manufacturing method using the same. The layout segmentation method of the present disclosure includes the steps of identifying regions having odd features and even features. Applying this layout division method can easily and smoothly transfer patterns of odd features and even features to semiconductor elements.

根據本揭露,係提出一種佈局分割方法(layout decomposition method),係由一電子運算系統之一邏輯處理器(logic processer)進行處理,該方法包括:邏輯處理器收到一設計佈局(design layout);邏輯處理器確定一設計規則(design rule)以佈局分割,包括:識別一基板上之複數個分散區(loose areas)和複數個密集區(dense areas);和識別基板上之具奇數特徵物之複數個第一區(first areas with odd-numbered features)和具偶數特徵物之複數個第二區(second areas with even-numbered features);和根據確定之設計規則,電子運算系統係相應地產生具有一第一圖案之一第一光罩和具有一第二圖案之一第二光罩。 According to the disclosure, a layout decomposition method is proposed, which is processed by a logic processer of an electronic computing system, the method comprising: receiving a design layout by a logical processor The logic processor determines a design rule to divide the layout, including: identifying a plurality of loose areas on a substrate and a plurality of dense areas; and identifying odd features on the substrate First areas with odd-numbered features and second areas with even-numbered features; and according to certain design rules, the electronic computing system is correspondingly generated A first mask having a first pattern and a second mask having a second pattern.

根據本揭露之一實施例,係提出一種半導體元件之製造方法,包括以一電子運算系統之一邏輯處理器進行一佈局分割,該製造方法包括:邏輯處理器收到和分析一設計佈局;邏輯處理器根據該設計佈局之分析結果,識別出一基板上之複數個分散區和複數個密集區,以及識別出基板上之具奇數特徵物之複數個第一區和具偶數特徵物之複數個第二區;藉由一第一光罩對該基板上一臨時層(temporary layer)進行第一次曝光,第一光罩具有一第一圖案實質上對應於基板之該些密集區;顯影該臨時層以形成複數個定位體(placeholders)於基板上;覆蓋一間隔材料(spacer material)於基板之該些定位體上,並圖案化間隔材料以至少於基板之密集區處形成複數個間隔物;移除該些定位體,以至少於基板之密集區的第二區處形成偶數特徵物;藉由一第二光罩對基板上分散區之間隔材料和密集區之間隔物進行第二次曝光,第二光罩具有一第二圖案至少對應於基板之分散區;和顯影間隔材料以至少形成分散區之複數個特徵物,其中密集區之第一區處之奇數特徵物可在第一次曝光顯影後、或第二次曝光顯影後而形成。 According to an embodiment of the present disclosure, a method of fabricating a semiconductor device includes performing a layout division by a logic processor of an electronic computing system, the manufacturing method comprising: receiving and analyzing a design layout by a logic processor; The processor identifies a plurality of discrete regions and a plurality of dense regions on a substrate according to the analysis result of the design layout, and identifies a plurality of first regions having an odd number of features on the substrate and a plurality of even features a second region; performing a first exposure on a temporary layer on the substrate by a first mask, the first mask having a first pattern substantially corresponding to the dense regions of the substrate; developing the Temporary layer to form a plurality of placeholders on the substrate; covering a spacer material on the positioning bodies of the substrate, and patterning the spacer material to form a plurality of spacers at least at a dense region of the substrate Removing the locating bodies to form an even number of features at least at a second region of the dense region of the substrate; and spacing the dispersion regions on the substrate by a second reticle a second exposure of the spacer and the spacer of the dense region, the second mask having a second pattern corresponding to at least the dispersion region of the substrate; and the development spacer material to form at least a plurality of features of the dispersion region, wherein the dense region is The odd features at one zone may be formed after the first exposure development or after the second exposure development.

為了對本發明之上述及其他方面有更佳的瞭解,下文 特舉實施例,並配合所附圖式,作詳細說明如下: In order to better understand the above and other aspects of the present invention, the following The specific embodiments, together with the drawings, are described in detail as follows:

本揭露係提出一種佈局分割方法(layout decomposition method),可應用於採用雙重曝光(double exposure)的半導體元件之製造方法,使半導體元件中作為轉移圖案之偶數特徵物和奇數特徵物能成功地,例如以特徵物數倍增之技術(pitch doubling technique),形成於元件上;例如是形成於一基板上或基板的沉積層上。以下係參照所附圖式詳細敘述本揭露之實施例。圖式中相同或類似的標號係用以標示相同或類似之部分。需注意的是,圖式係已簡化以利清楚說明實施例之內容,圖式上的尺寸比例並非按照實際產品等比例繪製,因此並非作為限縮本發明保護範圍之用。 The present disclosure proposes a layout decomposition method which can be applied to a manufacturing method of a semiconductor device using double exposure, so that even-numbered features and odd-numbered features in a semiconductor element can be successfully used as a transfer pattern. For example, a pitch doubling technique is formed on the element; for example, formed on a substrate or a deposited layer of the substrate. The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. The same or similar reference numerals are used to designate the same or similar parts. It is to be noted that the drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn to the scale of the actual products, and thus are not intended to limit the scope of the present invention.

第1圖係為本發明實施例之佈局分割方法之一般流程圖。實施例之佈局分割方法例如是由一電子運算系統(computing system)之一邏輯處理器(logic processer)進行處理。首先,如步驟S101所示,邏輯處理器收到一設計佈局(design layout)。接者,如步驟S102所示,邏輯處理器確認佈局分割的一設計規則(design rule)。在此實施例中,確認佈局分割的設計規則包括了:識別出基板上特徵物較為密集分佈之區域(dense areas),即密集區(dense areas),和特徵物較為疏鬆分佈之區域,即分散區(loose areas);也識別出具奇數特徵物和偶數特徵物之區域。之後,如步驟S103所示,根據識別之設計規則,電子運算 系統係相應地產生具有一第一圖案之一第一光罩和具有一第二圖案之一第二光罩。 FIG. 1 is a general flow chart of a layout dividing method according to an embodiment of the present invention. The layout dividing method of the embodiment is processed, for example, by a logic processer of an electronic computing system. First, as shown in step S101, the logical processor receives a design layout. Then, as shown in step S102, the logical processor confirms a design rule of the layout division. In this embodiment, the design rule for confirming the layout division includes: identifying dense areas of the features on the substrate, that is, dense areas, and areas where the features are loosely distributed, that is, dispersed. Loose areas; regions with odd and even features are also identified. After that, as shown in step S103, according to the design rule of identification, electronic operation The system accordingly produces a first reticle having a first pattern and a second reticle having a second pattern.

在應用此實施例時,密集區例如是元件之陣列區域(array region)所在,其通常具有密集分佈的導線和電子元件如電晶體和電容。而分散區例如是週邊區域(peripheral region),比起陣列區域,週邊區域通常具有較大或疏鬆分佈的元件。不過,「密集」區和「分散」區、或是「較大」(「較寬」)特徵和「較小」(「較窄」)特徵的決定,係視實際應用時不同形成圖案之製程情況而定,而並不特別限制在特定區域。再者,應用實施例時,可採用使用第一光罩之後使用第二光罩的雙重曝光方式,以製作出元件上較細窄和較寬大之特徵物,以及奇數特徵物和偶數特徵物。 In applying this embodiment, the dense regions are, for example, the array regions of the components, which typically have densely distributed wires and electronic components such as transistors and capacitors. Whereas the dispersion zone is, for example, a peripheral region, the peripheral region typically has larger or loosely distributed components than the array region. However, the "intensive" and "scattered" areas, or the "larger" ("wider") and "smaller" ("narrower") features are determined by the process of forming a pattern depending on the actual application. It depends on the situation and is not particularly limited to a specific area. Furthermore, in applying the embodiment, a double exposure method using a second mask after using the first mask can be employed to produce features that are narrower and wider on the element, as well as odd and even features.

此實施例中,如步驟S102所示之確認佈局分割的設計規則後,已識別出特徵物的最小間距(minimum pitch),以及具有奇數特徵物和偶數特徵物之各相關區域。一般而言,第一光罩之第一圖案係包括了最小間距之圖形。應用本揭露之實施例時,有幾種實施例之佈局分割方法的應用方式,可用以製作具偶數特徵物和奇數特徵物之半導體元件。以下係提出相關說明。 In this embodiment, after confirming the design rule of the layout division as shown in step S102, the minimum pitch of the feature and the relevant regions having the odd feature and the even feature have been identified. In general, the first pattern of the first mask includes a pattern of minimum spacing. In applying the embodiments of the present disclosure, there are several embodiments of the layout method of the layout method that can be used to fabricate semiconductor components having even features and odd features. The following is a description.

第2A-2D圖係部分地繪示依本發明實施例之一種製造元件中具有偶數特徵物之方法示意圖。在此實施例中,依實施例之佈局分割方法所產生之一第一光罩(未顯示)係具有一第一圖案,包括複數個窄條狀區域(fine-striped regions)對應於基板20處之密集區。而依實施例之佈局分割方法所產生之一第二光罩係具有一第二圖案對應於基 板20處之分散區,和對應密集區之裁剪區域(cutting regions)/遮蔽區域(shielding regions)。如第2A圖所示,在以第一光罩曝光顯影後係定義出複數個定位體(placeholders)21於基板20上。如第2B圖所示,一間隔材料(spacer material)22係沈積於基板20上並覆蓋定位體21。之後,例如非等向性蝕刻間隔材料22以於定位體21的兩側形成間隔物22’,如第2C圖所示;其中係自間隔材料22頂面水平地向下蝕刻至露出定位體21表面。接著,如第2D圖所示,移除定位體21,而留下其兩側的間隔物22’於基板20上。因此,間隔物22’的數目是定位體21數目的兩倍。之後,該些間隔物22’可作為一模板(mask)以將間隔物22’的圖案轉移至基板20(未繪示於圖中)。如第2D圖所示,形成偶數個特徵物(間隔物22’)於基板20之密集區處。 2A-2D is a partial schematic view showing a method of manufacturing an even number of features in an element according to an embodiment of the present invention. In this embodiment, one of the first masks (not shown) produced by the layout dividing method of the embodiment has a first pattern including a plurality of fine-striped regions corresponding to the substrate 20 Intensive area. According to the layout division method of the embodiment, one of the second masks has a second pattern corresponding to the base. The discrete regions at the plate 20, and the cutting regions/shielding regions of the corresponding dense regions. As shown in FIG. 2A, a plurality of placeholders 21 are defined on the substrate 20 after exposure and development by the first mask. As shown in FIG. 2B, a spacer material 22 is deposited on the substrate 20 and covers the positioning body 21. Thereafter, the spacer material 22 is etched, for example, to form a spacer 22' on both sides of the positioning body 21, as shown in FIG. 2C; wherein the top surface of the spacer material 22 is horizontally etched downward to expose the positioning body 21 surface. Next, as shown in Fig. 2D, the positioning body 21 is removed while leaving the spacers 22' on both sides thereof on the substrate 20. Therefore, the number of spacers 22' is twice the number of the positioning bodies 21. Thereafter, the spacers 22' can serve as a mask to transfer the pattern of spacers 22' to the substrate 20 (not shown). As shown in Fig. 2D, an even number of features (spacers 22') are formed at dense regions of the substrate 20.

第3A-3D圖係部分地繪示依本發明實施例之一種元件中密集區具有奇數特徵物之製造方法示意圖。在此實施例中,依實施例之佈局分割方法所產生之第一光罩(未顯示)係具有第一圖案對應於基板30處之密集區,此第一圖案例如是包括複數個窄條狀區域和複數個寬條狀區域(wide-striped regions)。而依據此實施例之佈局分割方法所產生之第二光罩係具有一第二圖案實質上對應於基板30處之分散區,第二圖案也可能根據設計所需而包括了對應密集區之裁剪區域/遮蔽區域。在此實施例中,第一光罩之窄條狀區域例如是對應於具奇數特徵物之密集區(Aodd),在以第一光罩曝光顯影後係定義出複數個窄定位 體(fine placeholder)31a於基板30上。再者,第一圖案中寬條狀區域其中之一係鄰近於對應密集區(Aodd)之窄條狀區域其中之一,以在基板30上定義出至少一寬定位體(wide placeholder)31b鄰設於窄定位體31a之一側,如第3A圖所示。 3A-3D is a partial view showing a manufacturing method of an odd-numbered feature in a dense region in an element according to an embodiment of the present invention. In this embodiment, the first mask (not shown) produced by the layout dividing method of the embodiment has a first pattern corresponding to a dense area at the substrate 30, and the first pattern includes, for example, a plurality of narrow strips. A region and a plurality of wide-striped regions. The second mask produced by the layout dividing method according to this embodiment has a second pattern substantially corresponding to the dispersed area at the substrate 30, and the second pattern may also include clipping of the corresponding dense area according to design requirements. Area/shadow area. In this embodiment, the narrow strip-shaped region of the first mask is, for example, corresponding to a dense region (Aodd) having an odd number of features, and defines a plurality of narrow positioning after exposure and development by the first mask. A fine placeholder 31a is on the substrate 30. Furthermore, one of the wide strip regions in the first pattern is adjacent to one of the narrow strip regions of the corresponding dense region (Aodd) to define at least one wide placeholder 31b adjacent to the substrate 30. It is provided on one side of the narrow positioning body 31a as shown in Fig. 3A.

之後,類似地,一間隔材料32係沈積於基板30上並覆蓋窄定位體31a和寬定位體31b,如第2B圖所示。例如非等向性蝕刻間隔材料32以於窄定位體31a和寬定位體31b的兩側形成間隔物32’,如第3C圖所示;其中,可自間隔材料32頂面水平地向下蝕刻至露出定位體31a和31b表面。第3C圖中寬定位體31b兩側之間隔物32’例如是但不限制地分屬不同區域,例如是如分屬具奇數特徵物之不同的兩個密集區(Aodd)。接著,如第3D圖所示,移除窄定位體31a和寬定位體31b,而留下其兩側的間隔物32’於基板30上。據此,奇數個間隔物32’係形成於具奇數特徵物之密集區(Aodd);而在具奇數特徵物之密集區之外的間隔物32’(如第3D圖左側)可以和其他區域的間隔物組合而構成該區域中的奇數或偶數個間隔物,或是視為虛擬間隔物(dummy spacer),其應用係視設計條件而定,本發明對此並不多做限制。之後,這些間隔物32’可作為一模板(mask),以將間隔物32’的圖案轉移至基板30(未繪示於圖中)。由於奇數個間隔物32’可由上述製程而形成,密集區處之奇數個特徵物將可順利地形成於基板30之密集區處。 Thereafter, similarly, a spacer material 32 is deposited on the substrate 30 and covers the narrow positioning body 31a and the wide positioning body 31b as shown in FIG. 2B. For example, the non-isotropic etching spacer material 32 forms spacers 32' on both sides of the narrow positioning body 31a and the wide positioning body 31b, as shown in FIG. 3C; wherein the top surface of the spacer material 32 can be horizontally etched downward The surface of the positioning bodies 31a and 31b is exposed. The spacers 32' on both sides of the wide positioning body 31b in Fig. 3C are, for example, but not limited to, belong to different regions, for example, two dense regions (Aodd) which are different from the odd-numbered features. Next, as shown in Fig. 3D, the narrow positioning body 31a and the wide positioning body 31b are removed while leaving the spacers 32' on both sides thereof on the substrate 30. Accordingly, an odd number of spacers 32' are formed in a dense region having an odd number of features (Aodd); and a spacer 32' (such as the left side of the 3D drawing) outside the dense region having odd features can be combined with other regions. The spacers are combined to form odd or even spacers in the region, or as dummy spacers, the application of which depends on design conditions, and the invention is not limited thereto. Thereafter, the spacers 32' can serve as a mask to transfer the pattern of spacers 32' to the substrate 30 (not shown). Since the odd spacers 32' can be formed by the above process, an odd number of features at the dense regions can be smoothly formed at the dense regions of the substrate 30.

第4A-4D圖係部分地繪示依本發明實施例之另一種 元件中密集區具有奇數特徵物之製造方法示意圖。第4A-4D圖中,基板40上定位體41、間隔材料42和間隔物42’的形成類似如上第2A-2D圖所述之形成定位體21、間隔材料22和間隔物22’的步驟請參照前述內容,在此不再贅述。在此實施例中,依實施例之佈局分割方法所產生之一第一光罩(未顯示)係具有一第一圖案,包括複數個窄條狀區域(fine-striped regions)對應於密集區;而所產生之一第二光罩係具有一第二圖案,包括複數個校正區域(correction regions)對應於密集區和複數個標準區域(normal regions)對應於分散區。在一實施例中,第二圖案的校正區域例如是包括複數個不透光區域(opaque regions)和複數個透光區域(transmissive regions),以分別部份地遮蔽和斷開形成於基板40上之間隔物(spacers)42’。如第4A圖所示,第一光罩上之窄條狀區域係定義出基板40上之複數個定位體41,且其中部份的定位體41係對應於具奇數特徵物之密集區(Aodd)。如第4C圖和第4D圖所示,偶數個間隔物42’係形成於基板40上。在後續圖案轉移之製程中,第二光罩之不透光區域如521可用以遮蔽奇數個間隔物42’(圖中以遮蔽3個間隔物42’示意),而留下奇數個間隔物42’(圖中以留下5個間隔物42’示意)作為一模板(mask)而進行圖案轉移。因此,圖案轉移後可順利地形成奇數特徵物於密集區(Aodd)。請同時參照第5圖,其繪示一第二光罩52上具有不透光區域521,應用於圖案轉移間隔物42’至基板40之製程。 4A-4D is a partial illustration of another embodiment in accordance with an embodiment of the present invention A schematic diagram of a manufacturing method in which a dense region in an element has an odd number of features. In FIGS. 4A-4D, the formation of the positioning body 41, the spacer material 42 and the spacer 42' on the substrate 40 is similar to the step of forming the positioning body 21, the spacer material 22 and the spacer 22' as described in the above 2A-2D. Referring to the foregoing, no further details are provided herein. In this embodiment, a first photomask (not shown) generated by the layout segmentation method of the embodiment has a first pattern, and includes a plurality of fine-striped regions corresponding to the dense regions; And the second mask produced has a second pattern including a plurality of correction regions corresponding to the dense regions and a plurality of normal regions corresponding to the dispersion regions. In an embodiment, the correction region of the second pattern includes, for example, a plurality of opaque regions and a plurality of transmissive regions to be partially shielded and disconnected from the substrate 40, respectively. Spacers 42'. As shown in FIG. 4A, the narrow strip-shaped region on the first mask defines a plurality of locating bodies 41 on the substrate 40, and a portion of the locating bodies 41 correspond to dense regions having odd features (Aodd). ). As shown in Figs. 4C and 4D, an even number of spacers 42' are formed on the substrate 40. In the subsequent pattern transfer process, the opaque regions of the second mask, such as 521, can be used to mask an odd number of spacers 42' (indicated by masking three spacers 42' in the figure), leaving an odd number of spacers 42. Pattern transfer (as indicated by leaving five spacers 42' in the figure) as a mask. Therefore, odd patterns can be smoothly formed in the dense area (Aodd) after the pattern transfer. Referring to FIG. 5 at the same time, a second reticle 52 having an opaque region 521 for applying the pattern transfer spacer 42' to the substrate 40 is illustrated.

第6A圖繪示另一第二光罩的簡示圖,其可應用於後 續轉移第4D圖中間隔物圖案之製程。第6圖中,除了不透光區域531,第二光罩53更包括了可裁切/斷開間隔物42’所形成之特徵物之圖案,如圖中至少一透光區域532。其不透光區域和/或透光區域的安排係視實際應用之佈局設計而定,圖示僅作舉例說明而非限制之用。第6B圖為間隔物圖案轉移後一圖案化基板60之上視圖。 FIG. 6A is a schematic view showing another second reticle, which can be applied to the rear The process of shifting the spacer pattern in the 4D drawing is continued. In Fig. 6, in addition to the opaque region 531, the second mask 53 further includes a pattern of features that can be cut/disconnected by the spacers 42', such as at least one of the light-transmissive regions 532. The arrangement of the opaque regions and/or the light transmissive regions depends on the layout design of the actual application, and the illustrations are for illustrative purposes only and not for limitation. Figure 6B is a top view of a patterned substrate 60 after spacer pattern transfer.

根據上述實施例,在確認佈局分割的設計規則之後,所產生的第一光罩其圖案(第一圖案)係對應於基板之密集區,所產生的第二光罩其圖案(第二圖案)係對應於基板之分散區和/或對應密集區之裁剪區域/遮蔽區域。第一光罩首先應用於製造具有細微間距(如對應最小間距)之間隔物圖案於基板之密集區處;然後,應用第二光罩製造分散區之相關圖案,並且,如設計規則需要,遮蔽(和/或裁切)密集區的部份間隔物,以在設計規則中所確認的相應區域處形成奇數特徵物和偶數特徵物。 According to the above embodiment, after confirming the design rule of the layout division, the pattern (first pattern) of the first mask produced corresponds to a dense area of the substrate, and the second mask produced by the pattern (second pattern) Corresponding to the discrete area of the substrate and/or the cropped area/masked area of the corresponding dense area. The first mask is first applied to fabricate a spacer pattern having a fine pitch (e.g., corresponding minimum spacing) at a dense region of the substrate; then, applying a second mask to create a pattern of the dispersion region, and, as required by design rules, masking Partial spacers in (and/or cropped) dense regions form odd and even features at corresponding regions identified in the design rules.

然而,本揭露並不僅止於上述之應用,圖案轉移之過程可依實際應用而做修飾與變化。例如,在另一實施例中,依實施例之佈局分割方法所產生之一第一光罩其第一圖案例如是包括複數個窄條狀區域,該些窄條狀區域例如是對應於密集區之一最小間距,再者,第一光罩上的第一圖案對應於基板之整體。而依實施例之佈局分割方法所產生之一第二光罩其第二圖案例如是對應分散區和對應密集區之裁剪區域/遮蔽區域。例如,第二光罩之第二圖案包括複數個第一校正區域(first correction regions)對應於密集區和複數個第二校正區域(second correction regions) 對應於分散區。首先應用第一光罩以於基板上全面地形成具有細微間距(如密集區所要求的最小間距)之間隔物,之後再應用第二光罩去移除分散區中密集分佈之多餘的間隔物,而第二光罩之圖案亦可達成,如設計規則需要,遮蔽(和/或裁切)密集區的部份間隔物,以在設計規則中所確認的相應區域處形成奇數特徵物和偶數特徵物。舉例來說,第二光罩之第一校正區域包括複數個第一不透光區域(first opaque regions)和/或複數個第一透光區域(first transmissive regions),以分別部份地遮蔽和/或斷開密集區之間隔物。第二光罩之第二校正區域例如是包括複數個第二不透光區域(second opaque regions)、複數個第二透光區域(second transmissive regions)或兩者之組合,以遮蔽和/或移除基板上分散區中不需要之多餘間隔物(undesired spacers)。 However, the disclosure does not stop at the above application, and the process of pattern transfer can be modified and changed according to practical applications. For example, in another embodiment, one of the first masks produced by the layout method according to the embodiment has a first pattern including, for example, a plurality of narrow strip regions, for example, corresponding to dense regions. One of the minimum spacings, further, the first pattern on the first reticle corresponds to the entirety of the substrate. According to the layout division method of the embodiment, the second mask has a second pattern, for example, a clipping area/shadow area corresponding to the dispersion area and the corresponding dense area. For example, the second pattern of the second mask includes a plurality of first correction regions corresponding to the dense region and a plurality of second correction regions. Corresponds to the dispersion area. First, the first mask is applied to form a spacer having fine pitch (such as the minimum spacing required for the dense region) on the substrate, and then the second mask is applied to remove the excess spacers densely distributed in the dispersion region. And the pattern of the second mask can also be achieved, as required by the design rules, to mask (and/or crop) portions of the spacers in the dense regions to form odd features and even numbers at corresponding regions identified in the design rules. Features. For example, the first correction region of the second reticle includes a plurality of first opaque regions and/or a plurality of first transmissive regions to partially shield and respectively / or disconnect the spacers in the dense area. The second correction region of the second mask includes, for example, a plurality of second opaque regions, a plurality of second transmissive regions, or a combination of the two to shield and/or move Except for undesired spacers in the dispersion area on the substrate.

在上述實施例中,定位體21、31a、31b和41可以是單或多層硬質遮罩層(hard mask layer),其材料例如是包括氮化矽、氧化矽、多晶矽、一有機材料例如是非晶碳材料(amorphous carbon material)、一高分子材料、一旋塗式介電材料(spin on dielectric material)如有機物抗反射塗層(ARC)、一介電抗反射塗層(DARC)如多矽之氮氧化矽(silicon-rich silicon oxynitride)、或是一無機材料。而實際應用時,定位體21、31a、31b、41之材料和間隔材料22、32、42的選擇,係可根據各種圖案化形成和轉移製程中相關的化學條件和步驟而作相應的選擇和調整。實施例中,定位體21、31a、31b、41之材料係可 相對於後續沈積之間隔材料22、32、42而作選擇性地蝕刻。另外,定位體21、31a、31b、41和間隔材料22、32、42和間隔物22’、32’、42’的厚度亦可視是否相容於應用製程中相關的化學條件和步驟而定,本揭露對此並不作限制。再者,雖然實施例中是以基板的圖案化製程配合圖示作說明,但本揭露並不僅限制於轉移圖案於基板上;實際應用時,其他膜層亦可形成於基板上,如果該些膜層具適當材質並搭配相關的化學條件和製程步驟,具特徵之圖案亦可轉移至該些膜層。 In the above embodiment, the positioning bodies 21, 31a, 31b, and 41 may be single or multiple layers of a hard mask layer, and the material thereof includes, for example, tantalum nitride, tantalum oxide, polycrystalline germanium, an organic material such as amorphous. A carbon material, a polymer material, a spin-on dielectric material such as an organic anti-reflective coating (ARC), a dielectric anti-reflective coating (DARC), such as a polysilicon Silicon-rich silicon oxynitride, or an inorganic material. In practical applications, the selection of the material of the positioning bodies 21, 31a, 31b, 41 and the spacing materials 22, 32, 42 can be selected according to the relevant chemical conditions and steps in the various patterning and transfer processes. Adjustment. In the embodiment, the materials of the positioning bodies 21, 31a, 31b, 41 are The etching is selectively etched with respect to the subsequently deposited spacer material 22, 32, 42. In addition, the thickness of the positioning bodies 21, 31a, 31b, 41 and the spacer materials 22, 32, 42 and the spacers 22', 32', 42' may also depend on whether they are compatible with the relevant chemical conditions and steps in the application process. This disclosure does not limit this. In addition, although the embodiment is illustrated by the patterning process of the substrate, the disclosure is not limited to the transfer pattern on the substrate; in practical applications, other film layers may be formed on the substrate, if The film layer is made of a suitable material and associated with the relevant chemical conditions and process steps, and the patterned pattern can also be transferred to the film layers.

根據上述實施例所揭露的佈局分割方法,可產生具有特殊圖形的光罩,使偶數特徵物和奇數特徵物不需額外或是複雜的製程步驟,即可簡單而順利地形成於元件上;例如是形成於一基板上或基板的沉積層上。再者,應用實施例之佈局分割方法而製造半導體元件,其製造方法亦可相容於現有之製程架構,因此十分適合量產而具有市場競爭力。 According to the layout segmentation method disclosed in the above embodiments, a mask having a special pattern can be generated, so that even features and odd features can be formed on the component simply and smoothly without additional or complicated process steps; for example; It is formed on a substrate or a deposited layer of a substrate. Furthermore, the semiconductor element is manufactured by applying the layout division method of the embodiment, and the manufacturing method thereof can be compatible with the existing process architecture, so that it is very suitable for mass production and has market competitiveness.

綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

20、30、40‧‧‧基板 20, 30, 40‧‧‧ substrates

21、31a、31b、41‧‧‧定位體 21, 31a, 31b, 41‧‧ ‧ positioning body

22、32、42‧‧‧間隔材料 22, 32, 42‧‧‧ spacer materials

22’、32’、42’‧‧‧間隔物 22', 32', 42' ‧ ‧ spacers

52、53‧‧‧第二光罩 52, 53‧‧‧second mask

521、531‧‧‧不透光區域 521, 531‧‧‧ opaque areas

532‧‧‧透光區域 532‧‧‧Lighting area

60‧‧‧圖案化基板 60‧‧‧ patterned substrate

Aodd‧‧‧具奇數特徵物之密集區 Aodd‧‧‧ dense area with odd features

S101-S103‧‧‧步驟 S101-S103‧‧‧Steps

第1圖係為本發明實施例之佈局分割方法之一般流程圖。 FIG. 1 is a general flow chart of a layout dividing method according to an embodiment of the present invention.

第2A-2D圖係部分地繪示依本發明實施例之一種製造元件中具有偶數特徵物之方法示意圖。 2A-2D is a partial schematic view showing a method of manufacturing an even number of features in an element according to an embodiment of the present invention.

第3A-3D圖係部分地繪示依本發明實施例之一種元件中密集區具有奇數特徵物之製造方法示意圖。 3A-3D is a partial view showing a manufacturing method of an odd-numbered feature in a dense region in an element according to an embodiment of the present invention.

第4A-4D圖係部分地繪示依本發明實施例之另一種元件中密集區具有奇數特徵物之製造方法示意圖。 4A-4D is a partial view showing a manufacturing method of an odd-numbered feature in a dense region in another component according to an embodiment of the present invention.

第5圖繪示一第二光罩的簡示圖,其可應用於圖案轉移間隔物至基板之製程。 FIG. 5 is a schematic view of a second photomask, which can be applied to the process of pattern transfer spacer to substrate.

第6A圖繪示另一第二光罩的簡示圖,其可應用於後續轉移第4D圖中間隔物圖案之製程。 FIG. 6A is a schematic view showing another second reticle, which can be applied to the process of subsequently transferring the spacer pattern in the 4D figure.

第6B圖為間隔物圖案轉移後一圖案化基板之上視圖。 Figure 6B is a top view of a patterned substrate after spacer pattern transfer.

Claims (20)

一種佈局分割方法(layout decomposition method),係由一電子運算系統之一邏輯處理器(logic processer)進行處理,該方法包括:該邏輯處理器收到一設計佈局(design layout);該邏輯處理器確定一設計規則(design rule)以佈局分割,包括:識別一基板上之複數個分散區(loose areas)和複數個密集區(dense areas);和識別該基板上之具奇數特徵物之複數個第一區(first areas with odd-numbered features)和具偶數特徵物之複數個第二區(second areas with even-numbered features);和根據確定之該設計規則,該電子運算系統係相應地產生具有一第一圖案之一第一光罩和具有一第二圖案之一第二光罩,該第一光罩和該第二光罩用以在該些密集區的該些第一區中形成奇數特徵物。 A layout decomposition method is processed by a logic processer of an electronic computing system, the method comprising: the logic processor receiving a design layout; the logical processor Determining a design rule to divide the layout includes: identifying a plurality of loose areas on a substrate and a plurality of dense areas; and identifying a plurality of odd features on the substrate First areas with odd-numbered features and second areas with even-numbered features; and according to the determined design rule, the electronic computing system is correspondingly generated a first mask and a second mask having a second pattern, the first mask and the second mask being used to form an odd number in the first regions of the dense regions Features. 如申請專利範圍第1項所述之佈局分割方法,其中該第一光罩之該第一圖案係對應於該些密集區。 The layout segmentation method of claim 1, wherein the first pattern of the first mask corresponds to the dense regions. 如申請專利範圍第2項所述之佈局分割方法,其中該第一光罩包括複數個窄條狀區域(fine-striped regions)和複數個寬條狀區域(wide-striped regions)以構成該第一圖案,而定義出該基板上之複數個定位體(placeholders)。 The layout dividing method according to claim 2, wherein the first mask comprises a plurality of fine-striped regions and a plurality of wide-striped regions to constitute the first A pattern defines a plurality of placeholders on the substrate. 如申請專利範圍第3項所述之佈局分割方法,其中該第一光罩之該第一圖案中該些寬條狀區域之一係鄰 近於對應該些密集區之該些窄條狀區域之一,以在該基板上定義出至少一寬定位體(wide placeholder)鄰設於複數個窄定位體(fine placeholder)之一側。 The method for dividing a layout according to claim 3, wherein one of the plurality of strip-shaped regions in the first pattern of the first mask is adjacent One of the narrow strip regions corresponding to the dense regions is defined to define at least one wide placeholder on the substrate adjacent to one of a plurality of fine placeholders. 如申請專利範圍第3項所述之佈局分割方法,其中該第二光罩之該第二圖案係實質上對應於該些分散區。 The layout dividing method according to claim 3, wherein the second pattern of the second mask substantially corresponds to the dispersed regions. 如申請專利範圍第1項所述之佈局分割方法,其中該第一光罩之該第一圖案包括複數個窄條狀區域(fine-striped regions)對應於該些密集區。 The layout segmentation method of claim 1, wherein the first pattern of the first mask comprises a plurality of fine-striped regions corresponding to the dense regions. 如申請專利範圍第6項所述之佈局分割方法,其中該第二光罩之該第二圖案包括複數個校正區域(correction regions)對應於該些密集區和複數個標準區域(normal regions)對應於該些分散區。 The layout segmentation method of claim 6, wherein the second pattern of the second mask comprises a plurality of correction regions corresponding to the dense regions and a plurality of normal regions. In these scattered areas. 如申請專利範圍第7項所述之佈局分割方法,其中該第二光罩之該些校正區域包括複數個不透光區域(opaque regions)和複數個透光區域(transmissive regions),以分別部份地遮蔽和斷開形成於該基板上之複數個間隔物(spacers)。 The layout dividing method according to claim 7, wherein the correction regions of the second mask comprise a plurality of opaque regions and a plurality of transmissive regions, respectively A plurality of spacers formed on the substrate are shielded and broken. 如申請專利範圍第1項所述之佈局分割方法,其中該第一光罩之該第一圖案係對應於該基板之整體,且該第一圖案包括複數個窄條狀區域對應於該些密集區之一最小間距(minimum pitch)。 The layout dividing method of claim 1, wherein the first pattern of the first mask corresponds to the entirety of the substrate, and the first pattern comprises a plurality of narrow strip regions corresponding to the dense portions. One of the minimum pitches of the zone. 如申請專利範圍第9項所述之佈局分割方法,其中該第二光罩之該第二圖案包括複數個第一校正區域(first correction regions)對應於該些密集區和複數個第二校正區域(second correction regions)對應於該些分散區。 The layout division method of claim 9, wherein the second pattern of the second mask comprises a plurality of first correction regions corresponding to the dense regions and a plurality of second correction regions. Second correction regions correspond to the dispersed regions. 如申請專利範圍第10項所述之佈局分割方法,其中該第二光罩之該些第一校正區域包括複數個第一不透光區域(first opaque regions)和複數個第一透光區域(first transmissive regions),以分別部份地遮蔽和斷開形成於該基板之該些密集區之複數個間隔物(spacers)。 The layout division method of claim 10, wherein the first correction regions of the second reticle comprise a plurality of first opaque regions and a plurality of first opaque regions ( First transmissive regions) to partially block and break a plurality of spacers formed in the dense regions of the substrate, respectively. 如申請專利範圍第10項所述之佈局分割方法,其中該第二光罩之該些第二校正區域包括複數個第二不透光區域(second opaque regions)、複數個第二透光區域(second transmissive regions)或兩者之組合,以遮蔽或移除該基板之該些分散區中多餘之間隔物(undesired spacers)。 The layout division method of claim 10, wherein the second correction regions of the second reticle comprise a plurality of second opaque regions and a plurality of second opaque regions ( Second transmissive regions) or a combination of the two to mask or remove the undesired spacers in the discrete regions of the substrate. 一種半導體元件之製造方法,包括以一電子運算系統之一邏輯處理器進行一佈局分割,該製造方法包括:該邏輯處理器收到和分析一設計佈局(design layout);該邏輯處理器根據該設計佈局之分析結果,識別出一基板上之複數個分散區(loose areas)和複數個密集區(dense areas),和識別出該基板上之具奇數特徵物(odd-numbered features)之複數個第一區和具偶數特徵物(even-numbered features)之複數個第二區;藉由一第一光罩對該基板上一臨時層(temporary layer)進行第一次曝光,該第一光罩具有一第一圖案實質上對應於該基板之該些密集區;顯影該臨時層以形成複數個定位體(placeholders)於該基板上; 覆蓋一間隔材料(spacer material)於該基板之該些定位體上,並圖案化該間隔材料以至少於該基板之該些密集區處形成複數個間隔物;移除該些定位體,以至少於該基板之該些密集區的該些第二區處形成該些偶數特徵物;藉由一第二光罩對該基板上該些分散區之該間隔材料和該些密集區之該些間隔物進行第二次曝光,該第二光罩具有一第二圖案至少對應於該基板之該些分散區;和顯影該間隔材料以至少形成該些分散區之複數個特徵物,其中該些密集區之該些第一區處之該些奇數特徵物係在第一次曝光顯影後或第二次曝光顯影後形成。 A method of fabricating a semiconductor device, comprising: performing a layout split by a logic processor of an electronic computing system, the manufacturing method comprising: the logic processor receiving and analyzing a design layout; the logic processor according to the The analysis result of the design layout identifies a plurality of loose areas and a plurality of dense areas on a substrate, and identifies a plurality of odd-numbered features on the substrate. a first region and a plurality of second regions having even-numbered features; first exposing a temporary layer on the substrate by a first mask, the first mask Having a first pattern substantially corresponding to the dense regions of the substrate; developing the temporary layer to form a plurality of placeholders on the substrate; Covering a spacer material on the locating bodies of the substrate, and patterning the spacer material to form a plurality of spacers at at least the dense regions of the substrate; removing the locating bodies to at least Forming the even-numbered features at the second regions of the dense regions of the substrate; the spacer material of the discrete regions on the substrate and the spacers of the dense regions by a second mask Performing a second exposure, the second mask having a second pattern corresponding to at least the dispersion regions of the substrate; and developing the spacer material to form at least a plurality of features of the dispersion regions, wherein the plurality of features are dense The odd features at the first zones of the zone are formed after the first exposure development or after the second exposure development. 如申請專利範圍第13項所述之製造方法,其中該第一光罩包括複數個窄條狀區域(fine-striped regions)和複數個寬條狀區域(wide-striped regions)以構成該第一圖案,且在利用該第一光罩進行第一次曝光顯影和移除該些定位體後,該些第一區處之該些奇數特徵物和該些第二區處之該些偶數特徵物係同時形成於該基板之該些密集區。 The manufacturing method of claim 13, wherein the first photomask comprises a plurality of fine-striped regions and a plurality of wide-striped regions to constitute the first a pattern, and after performing the first exposure development and removing the positioning bodies by using the first mask, the odd-numbered features at the first regions and the even-numbered features at the second regions They are simultaneously formed in the dense regions of the substrate. 如申請專利範圍第13項所述之製造方法,其中該第一光罩包括複數個窄條狀區域實質上對應該基板之該些密集區,在利用該第一光罩對該臨時層進行曝光顯影後,該些間隔物實質上形成於該些密集區。 The manufacturing method of claim 13, wherein the first mask comprises a plurality of narrow strip regions substantially corresponding to the dense regions of the substrate, and the temporary layer is exposed by using the first mask After development, the spacers are formed substantially in the dense regions. 如申請專利範圍第15項所述之製造方法,其中該第二光罩包括複數個校正區域(correction regions)對應於該些密集區和複數個標準區域(normal regions)對應於 該些分散區,且該些校正區域包括複數個不透光區域(opaque regions)和複數個透光區域(transmissive regions),以分別對應該些密集區之複數個裁剪區域(cutting regions)和遮蔽區域(shielding regions),在利用該第二光罩對該間隔材料和該些間隔物進行曝光顯影後,係形成該些第一區之該些奇數特徵物和該些分散區之該些特徵物。 The manufacturing method of claim 15, wherein the second reticle includes a plurality of correction regions corresponding to the dense regions and a plurality of normal regions corresponding to The plurality of discrete regions, and the correction regions include a plurality of opaque regions and a plurality of transmissive regions to respectively correspond to a plurality of cutting regions and shadows of the dense regions The shielding regions, after exposing and developing the spacer material and the spacers by using the second mask, forming the odd features of the first regions and the features of the dispersion regions . 如申請專利範圍第13項所述之製造方法,其中該第一光罩之該第一圖案係對應於該基板之整體,且該第一圖案包括複數個窄條狀區域對應於該些密集區,且在利用該第一光罩進行第一次曝光顯影和移除該些定位體後,至少形成該些偶數特徵物於該些密集區之該些第二區處。 The manufacturing method of claim 13, wherein the first pattern of the first mask corresponds to the entirety of the substrate, and the first pattern comprises a plurality of narrow strip regions corresponding to the dense regions. And after performing the first exposure development and removing the positioning bodies by using the first mask, at least the even features are formed at the second regions of the dense regions. 如申請專利範圍第17項所述之製造方法,其中該第二光罩之該第二圖案包括複數個第一校正區域(first correction regions)對應於該些密集區和複數個第二校正區域(second correction regions)對應於該些分散區,在利用該第二光罩對該些間隔物和該間隔材料進行曝光顯影後,係形成該些第一區之該些奇數特徵物和該些分散區之該些特徵物。 The manufacturing method of claim 17, wherein the second pattern of the second mask comprises a plurality of first correction regions corresponding to the dense regions and the plurality of second correction regions ( Corresponding to the plurality of dispersion regions, after the spacers and the spacer material are exposed and developed by the second mask, the odd-numbered features of the first regions and the dispersed regions are formed These features. 如申請專利範圍第18項所述之製造方法,其中該第二光罩之該些第一校正區域包括複數個第一不透光區域(first opaque regions)和複數個第一透光區域(first transmissive regions),以分別部份地遮蔽和斷開形成於該基板之該些密集區之該些間隔物。 The manufacturing method of claim 18, wherein the first correction regions of the second reticle comprise a plurality of first opaque regions and a plurality of first opaque regions (first Transmissive regions) to partially shield and break the spacers formed in the dense regions of the substrate, respectively. 如申請專利範圍第19項所述之製造方法,其中該第二光罩之該些第二校正區域包括複數個第二不透光區域(second opaque regions)、複數個第二透光區域(second transmissive regions)或兩者之組合,以遮蔽或移除該基板之該些分散區中該間隔材料之多餘部份,而形成該些分散區之該些特徵物。 The manufacturing method of claim 19, wherein the second correction regions of the second reticle comprise a plurality of second opaque regions and a plurality of second opaque regions (second Transmissive regions, or a combination of the two, to mask or remove excess portions of the spacer material in the discrete regions of the substrate to form the features of the discrete regions.
TW101142464A 2012-11-14 2012-11-14 Layout decomposition method and method for manufacturing semiconductor device applying the same TWI521369B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW101142464A TWI521369B (en) 2012-11-14 2012-11-14 Layout decomposition method and method for manufacturing semiconductor device applying the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW101142464A TWI521369B (en) 2012-11-14 2012-11-14 Layout decomposition method and method for manufacturing semiconductor device applying the same

Publications (2)

Publication Number Publication Date
TW201419019A TW201419019A (en) 2014-05-16
TWI521369B true TWI521369B (en) 2016-02-11

Family

ID=51294343

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101142464A TWI521369B (en) 2012-11-14 2012-11-14 Layout decomposition method and method for manufacturing semiconductor device applying the same

Country Status (1)

Country Link
TW (1) TWI521369B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102219460B1 (en) * 2014-09-04 2021-02-24 삼성전자주식회사 Method of decomposing layout of semiconductor device and method of manufacturing semiconductor device using the same

Also Published As

Publication number Publication date
TW201419019A (en) 2014-05-16

Similar Documents

Publication Publication Date Title
US8435884B2 (en) Method for forming an interconnect structure
TW201839914A (en) Feature size reduction
US9502306B2 (en) Pattern formation method that includes partially removing line and space pattern
JP2010239009A (en) Method for manufacturing semiconductor device, and method for forming template and pattern inspection data
JP2010087301A (en) Method for manufacturing semiconductor device
TWI701712B (en) Method for preparing a patterned target layer
US8148051B2 (en) Method and system for manufacturing openings on semiconductor devices
JP2004134574A (en) Manufacturing method of semiconductor device
TWI438824B (en) Manufacturing method of semiconductor device
US8930860B2 (en) Layout decomposition method and method for manufacturing semiconductor device applying the same
JP2001060003A (en) Photomask and method for forming fine pattern of semiconductor device using the same
JP2011119536A (en) Method of manufacturing semiconductor device
TWI521369B (en) Layout decomposition method and method for manufacturing semiconductor device applying the same
US9034766B2 (en) Pattern formation method
US9032340B2 (en) Layout decomposition method and method for manufacturing semiconductor device applying the same
US20190317393A1 (en) Mask and method of forming pattern
JP2007123342A (en) Manufacturing method of semiconductor device
US9329471B1 (en) Achieving a critical dimension target based on resist characteristics
US20080305635A1 (en) Method for fabricating a pattern
JP2004233803A (en) Semiconductor manufacturing mask, manufacturing method of semiconductor device and semiconductor manufacturing mask
TWI447886B (en) Multiple patterning method
US9606432B2 (en) Alternating space decomposition in circuit structure fabrication
CN104952705A (en) Double pattern and manufacture method of semiconductor device structure
KR100948480B1 (en) Method of forming micro pattern for semiconductor device
US20150044875A1 (en) Method of forming pattern