KR100642393B1 - Method of forming a pattern in semiconductor device - Google Patents

Abstract

The pattern forming method of the semiconductor device of the present invention is for forming a pattern having a relatively small first width in the first region and having a stripe shape in the second region, and having a relatively large second width in the second region. According to this method, a photoresist film is first formed on the target film to be patterned. An exposure and development process is then performed to form a photoresist film pattern exposing the portion to be removed of the target film quality. The exposure process may include a mask having a main pattern having a width corresponding to the first width in the first region and a second region, and at least one auxiliary pattern disposed adjacent to the main pattern in the second region. Do it. Next, an exposed portion of the target film quality is removed by an etching process using the photoresist film pattern as an etching mask to form a pattern.

HEIP, gate pattern, mask, main pattern, auxiliary pattern

Description

Method of forming a pattern in semiconductor device

1 is a layout diagram illustrating a gate pattern at a boundary between an isolation region and an active region.

FIG. 2 is a layout diagram illustrating a conventional mask used to form the gate pattern of FIG. 1.

3 is a layout diagram illustrating an example of a mask used in a method of forming a pattern of a semiconductor device according to the present invention.

4 is a cross-sectional view of the mask of FIG. 3 taken along line IV-IV '.

5 to 9 are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to the present invention using the mask of FIG. 3.

FIG. 10 is a plan view illustrating a gate pattern formed by a method of forming a semiconductor device in accordance with the present invention overlaid with the mask of FIG. 3.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a pattern of a semiconductor device using a photolithography process.

With the recent increase in the degree of integration of semiconductor devices, techniques for forming fine patterns using photolithography processes have also been greatly developed. In particular, the channel length of the transistor is also getting smaller by forming the gate pattern finely. However, as the channel length of the transistor is shortened, various unfavorable characteristics due to a short channel effect (SCE) have been problematic. Therefore, various methods for suppressing such short channel effects have been studied and proposed.

One of the causes of the short channel effect is Hot Electron Induced Punchthrough (HEIP). This HEIP phenomenon is particularly a phenomenon in which, in a p-channel type transistor, hot electrons are trapped in the gate insulating film near the drain region, and an inversion layer is formed near the drain region by the trapped hot electrons. This HEIP phenomenon reduces the effective channel length by forming an inversion layer adjacent to the drain region, and as a result, the short channel effect becomes more severe. This HEIP phenomenon occurs in the general active region, but also occurs at the interface between the active region and the isolation region. Therefore, in order to suppress the phenomenon in which the HEIP phenomenon occurs at the interface between the active region and the device isolation region, it is necessary to form the gate pattern in this portion to have a sufficient width.

FIG. 1 is a layout diagram illustrating a gate pattern to be manufactured to prevent a HEIP phenomenon at an interface between an active region and an isolation region.

As illustrated in FIG. 1, a gate pattern 130 having a stripe shape is disposed to cross the device isolation region 110 and the active region 120 disposed adjacent to each other. The gate pattern 130 has a relatively small width w1 in the device isolation region 110 and the active region 120, while relatively at the boundary between the device isolation region 110 and the active region 120. It has a large width w2. As described above, by having a relatively large width w2 at the boundary between the device isolation region 110 and the active region 120, the occurrence of HEIP phenomenon at this portion can be suppressed.

FIG. 2 is a layout diagram illustrating a conventional mask used to form the gate pattern of FIG. 1.

As shown in FIG. 2, the conventional mask 200 has a structure in which the light blocking layer pattern 220 is disposed on the transparent substrate 210. The light blocking film pattern 220 has a shape similar to the gate pattern to be formed, that is, the gate pattern 130 shown in FIG. 1. Therefore, the width at the portion corresponding to the boundary between the device isolation region 110 and the active region 120 is relatively larger than the width at other portions.

When the etching process following the exposure and development processes is performed using the conventional mask 200 as described above, the gate pattern 130 illustrated in FIG. 1 may be obtained. That is, the profile of the gate pattern 130 at the boundary between the device isolation region 110 and the active region 120 is defined as the protrusion degree (a) of the protrusion of the light blocking layer pattern 220 of the mask 200 and the length ( depends on b) and width c. In this case, precise CD (Critical Dimension) adjustment is not easy at the boundary between the device isolation region 110 and the active region 120 due to misalignment of the mask 200. Further, it is difficult to obtain the gate pattern 130 of the desired profile because CD adjustment is difficult.

The technical problem to be achieved by the present invention is to provide a method of forming a pattern of a semiconductor device to facilitate CD control and to form a pattern of a desired profile.

In order to achieve the above technical problem, the method of forming a pattern of a semiconductor device according to the present invention has a relatively small first width in the first region and has a stripe shape, and has a relatively large second width in the second region. A pattern forming method of a semiconductor device for forming a pattern, comprising: forming a photoresist film on an object film to be patterned; A photoresist film pattern is formed to expose a portion of the target film to be removed by performing an exposure and development process, wherein the exposure process includes a main pattern having a width corresponding to the first width in the first region and the second region. Performing a mask layer pattern having at least one auxiliary pattern disposed adjacent to the main pattern in the second region; And forming a pattern by removing the exposed portion of the target film quality by an etching process using the photoresist film pattern as an etching mask.

The pattern may be a gate pattern.

In this case, the second region having a relatively large second width among the widths of the gate pattern may include a boundary between the device isolation region and the active region.

The mask may be a phase inversion mask.

In this case, it is preferable that the light transmittance of the main pattern of the said phase inversion mask is 6% or less, and the inverted phase is 180 degree | times.

The auxiliary pattern may have a bar shape arranged in parallel with the main pattern.

Preferably, the separation distance between the auxiliary pattern and the main pattern is 2.5 to 3 times the width of the auxiliary pattern.

Preferably, the width of the auxiliary pattern is 1/3 to 1/2 times the width of the main pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

3 is a layout diagram illustrating a mask used in a method of forming a pattern of a semiconductor device according to the present invention.

Referring to FIG. 3, the mask 300 used in the method for forming a pattern of a semiconductor device according to the present invention includes a main pattern 320 and an auxiliary pattern 330 disposed on the transparent substrate 310. The main pattern 320 and the auxiliary pattern 330 may be patterns for blocking light. The mask 300 is for forming the gate pattern of FIG. 1 (130 of FIG. 1). The main pattern 320 has a profile similar to the gate pattern 130 to be formed, and thus has a stripe shape. The auxiliary pattern 330 may include a first auxiliary pattern 331 disposed to be spaced apart from both sides of the main pattern 320 at a first interval d1, and a side surface of the main pattern 320 and the first gap d1. The second auxiliary pattern 332 is disposed to be parallel to the first auxiliary pattern 331 at a larger second interval d2. In some cases, the first auxiliary pattern 331 may include only the first auxiliary pattern 331, or may further include a third auxiliary pattern disposed in parallel with the second auxiliary pattern 332.

The number of auxiliary patterns 330 is determined by the profile of the pattern to be formed. In order to form a pattern having the same profile as the gate pattern 130 of FIG. 1, the distance d1 between the main pattern 320 and the first auxiliary pattern 331 is about 2.5 to 3 of the width of the first auxiliary pattern 331. Double your stomach. Similarly, an interval between the first auxiliary pattern 331 and the second auxiliary pattern 332 is also about 2.5 to 3 times the width of the first auxiliary pattern 331.

The width of the auxiliary pattern 330 is such that the width of the auxiliary pattern 330 does not affect the photoresist film pattern when the actual photolithography process is performed. That is, even when the exposure and development processes are performed using the mask 300 of FIG. 3, a photoresist film pattern such as the auxiliary pattern 330 is not formed. To this end, the width of the auxiliary pattern 330 is approximately 1/3 to 1/2 times the width of the main pattern 320.

4 is a cross-sectional view of the mask of FIG. 3 taken along the line IV-IV '.

Referring to FIG. 4, an anti-reflection film 311 is disposed on the transparent substrate 310, and the main phase shift film pattern 320a and the auxiliary phase shift film patterns 331a and 332a are disposed thereon. The auxiliary upper phase shift pattern 331a and 332a include a first auxiliary phase shift pattern 331a and a second auxiliary phase shift pattern 332a. The main pattern 320 is disposed on the main phase inversion film pattern 320a. The first auxiliary pattern 331 and the second auxiliary pattern 332 are disposed on the first auxiliary phase inversion film pattern 331a and the second auxiliary phase inversion film pattern 332a, respectively. The main pattern 320 and the first and second auxiliary patterns 331 and 332 are made of a chromium film. The light transmittances of the main phase inversion film pattern 320a and the auxiliary phase inversion film patterns 331a and 332a are approximately 6% or less, and the inverted phase is approximately 180 degrees. In the present embodiment, the phase inversion mask has been described as an example, but is not necessarily limited thereto. For example, only the main phase inversion film pattern 320a, or only the auxiliary phase inversion film patterns 331a and 332a, or the main phase inversion film pattern 320a and the auxiliary phase inversion film patterns 331a and 332a may be absent. .

5 through 9 are cross-sectional views illustrating a method of forming a gate pattern by performing a photolithography process using the mask of FIG. 3. 5 and 7 are cross-sectional views taken along the line A-A 'of FIG. 3, FIG. 8 is a cross-sectional view taken along the line B-B' of FIG. 3, and FIGS. 6 and 9 are shown in FIG. It is sectional drawing shown along the line C-C '.

First, referring to FIGS. 5 and 6, the gate insulating layer 510 is formed of, for example, an oxide layer on the semiconductor substrate 500 where the active region 120 is defined by the device isolation region 110. The device isolation region 110 is a region in which the trench device isolation layer 111 is disposed, and in some cases, a LOCOS (LOCal Oxidation of Silicon) device isolation layer may be disposed. Next, a gate 520 is formed on the gate insulating film 510, for example, as a polysilicon film, a metal silicide film, and a capping layer. Next, a photoresist film 530 is formed over the gate 520.

Next, referring to FIGS. 7 to 9, an opening for exposing a portion of the gate 520 by performing an exposure process and a development process using the mask 300 of FIG. 3 on the resultant of FIGS. 5 and 6 ( A photoresist film pattern 532 having 533 is formed. Then, a stripe-type photoresist film pattern 532 is formed to penetrate the device isolation region 110 and the active region 120 long (see FIG. 9). At this time, at the boundary between the device isolation region 110 and the active region 120, a relatively large photoresist film pattern 532 is formed due to the presence of the auxiliary pattern 330 of FIG. 3 (see FIG. 7). In the remaining part, a photoresist film pattern 532 having a relatively small width is formed (see FIG. 8).

Next, an etching process using the photoresist pattern 532 as an etching mask is performed to remove the exposed portion of the gate 520 exposed by the opening 533. As a result, a gate pattern having a profile similar to that of the photoresist layer pattern 532 may be obtained. After the etching process for forming the gate pattern is performed, a conventional strip process is performed to remove the photoresist film pattern 532.

FIG. 10 is a plan view illustrating a gate pattern formed by a method of forming a semiconductor device in accordance with the present invention overlaid with the mask of FIG. 3.

Referring to FIG. 10, the gate pattern 522 is formed to have a relatively small first width w1 ′ in the device isolation region 110 and the active region 120. On the other hand, the boundary between the device isolation region 110 and the active region 120 is formed to have a second width w2 'that is relatively larger than the first width w1'. This is because a mask (300 of FIG. 3) having an auxiliary pattern 330 disposed at a boundary between the device isolation region 110 and the active region 120 is used. Also, no separate pattern is made by the auxiliary pattern 330. The profile of the protruding portion of the gate pattern 522 at the boundary between the device isolation region 110 and the active region 120 is the distance d1 between the main pattern 320 and the auxiliary pattern 330 of the mask 300. ), And thus, by easily adjusting the CD, the gate pattern 522 of the desired profile can be made. In addition, the end of the protruding portion of the gate pattern 522 is formed flat as compared with the conventional case, it is possible to effectively suppress the occurrence of the HEIP phenomenon.

As described above, according to the method for forming a pattern of a semiconductor device according to the present invention, by performing a photolithography process using a mask having auxiliary patterns on both sides of a main pattern, By forming a large gate pattern, it is possible to effectively suppress the occurrence of the HEIP phenomenon. Furthermore, the CD can be easily adjusted by adjusting the distance between the main pattern and the auxiliary pattern, and the advantage is also provided that the pattern can be formed to have a desired profile.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (8)

In the method of forming a pattern of a semiconductor device for forming a gate pattern having a relatively small first width in the first region and having a relatively large second width in the second region, Forming a photoresist film on the target film to be patterned; A photoresist film pattern is formed to expose a portion of the target film to be removed by performing an exposure and development process, wherein the exposure process includes a main pattern having a width corresponding to the first width in the first region and the second region. And a mask having at least one auxiliary pattern disposed in the second region and adjacent to the main pattern; And And forming a gate pattern by removing an exposed portion of the target film quality by an etching process using the photoresist pattern as an etching mask. delete The method of claim 1, And a second region having a relatively larger second width among the widths of the gate pattern includes a boundary portion between the device isolation region and the active region. The method of claim 1, And the mask is a phase inversion mask. The method of claim 4, wherein The light transmittance of the main pattern of the phase inversion mask is 6% or less, and the inverted phase is 180 degrees pattern formation method of a semiconductor device. The method of claim 1, The auxiliary pattern is a pattern forming method of a semiconductor device, characterized in that it has a bar shape arranged in parallel with the main pattern. The method of claim 1, The spacing distance between the auxiliary pattern and the main pattern is 2.5 to 3 times the width of the auxiliary pattern, the pattern forming method of a semiconductor device. The method of claim 1, And the width of the auxiliary pattern is 1/3 to 1/2 times the width of the main pattern.

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