JP2004247606A - Photomask, semiconductor device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily remove the limit on the shifter width, prevent the narrowing of a gate wiring pattern, wire breaking and retraction, and distortion of a gate electrode pattern, and facilitate the shrinking processing of the device area, and improve the uniformity of the size of an extremely fine gate. <P>SOLUTION: Upon forming a gate composed of a gate electrode and a gate wiring, only the gate electrode pattern 12 is formed by a double exposure processing using a first mask 1 and a second mask 2, and thereafter the gate wiring pattern 13 is formed by an exposing processing using a third mask 3. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a photomask, a semiconductor device, and a method of manufacturing the same, and is particularly preferably applied to a case where a gate electrode having an extremely fine size is formed.
[0002]
[Prior art]
In recent years, with the miniaturization of devices, it has become difficult to form fine patterns and fine pitches. In order to form fine patterns, a double exposure process using two photomasks in one layer has been introduced. ing. At present, a so-called phase edge technique is one of the techniques that have received special attention in this double exposure process. This technique is mainly used at the time of forming a gate. In a region where a gate pattern of an extremely fine size is formed, in addition to a mask (binary mask or halftone phase shift mask) for forming a normal pattern, a Levenson phase shift mask is used. Is used. The Levenson phase shift mask has an effect of inverting the amplitude of light in this region by arranging a shifter having a 0 phase on one side and a π phase on the other side of a pattern serving as a gate electrode, thereby increasing contrast. This makes it possible to stably form even a pattern having a size of 100 nm or less.
[0003]
FIG. 14 is a schematic plan view showing a conventional method of forming a gate pattern by a phase edge technique using a Levenson phase shift mask. In this specification, a relatively narrow portion existing in the active region is referred to as a gate electrode, a relatively wide portion existing outside the active region is referred to as a gate wiring, and a gate is constituted by the gate electrode and the gate wiring. explain.
[0004]
FIG. 14A shows a pattern image 101 of a first mask for forming a normal gate wiring pattern. The portion serving as the gate electrode pattern is formed wide, but is formed large in advance in order to secure a margin for alignment with the pattern image 102 of the second mask which is a Levenson phase shift mask. FIG. 14B shows a pattern image 102 of the second mask. This is a mask formed so that the phases of the left and right transmission regions become 0 and π, and the portion sandwiched between them becomes the gate electrode pattern. FIG. 14C shows a state in which the first mask and the second mask are overlapped. By continuously transferring these two masks onto a wafer, a gate pattern 103 shown in FIG. 14D is formed.
[0005]
FIGS. 15 and 16 are schematic plan views showing a conventional gate forming method by a phase edge technique using a Levenson phase shift mask. In each figure, the upper part shows the part of the gate electrode, and the latter part shows the part of the gate wiring.
[0006]
First, a gate insulating film 104 is formed on the silicon substrate 101 (FIG. 15A) on which the active region 103 is formed by forming the element isolation structure 102 (FIG. 15B). Next, a polysilicon film 105, a hard mask 106, an antireflection film 107, and a resist 108 are sequentially formed (FIG. 15C).
[0007]
On the silicon substrate 101 in this state, the gate pattern is transferred to the resist 108 by the phase edge technique described above to form a resist pattern 109 (FIG. 16A). Using the resist pattern 109 as a mask, the antireflection film 107, the hard mask 106, the polysilicon film 105, and the gate insulating film 104 are etched.
[0008]
At this time, a trimming process may be used in the etching step in order to improve the performance of the gate electrode. By using the trimming process, it can be processed into a pattern narrower than the gate electrode dimension formed by the resist pattern 109 (FIG. 16B).
[0009]
Then, sidewalls 110 are formed on both side surfaces of the polysilicon film 105 by anisotropic etching after depositing a silicon oxide film on the entire surface, and source / drain 111 is formed by ion implantation of impurities (FIG. 16C )).
[0010]
Similarly, a process capable of forming a gate electrode pattern thinner than a resist pattern will be described with reference to FIGS. This is a structure generally called a trench gate.
[0011]
First, a protective film 121 made of, for example, a silicon oxide film is formed on the silicon substrate 101 (FIG. 17A) on which the active region 103 is formed by forming the element isolation structure 102 (FIG. 17B). Next, after a polysilicon film 105 is formed (FIG. 17C), an antireflection film 107 and a resist 108 are sequentially formed (FIG. 18A).
[0012]
On the silicon substrate 101 in this state, the gate pattern is transferred to the resist 108 by the phase edge technique described above to form a resist pattern 109 (FIG. 18B). Using the resist pattern 109 as a mask, the antireflection film 107, the polysilicon film 105, and the protective film 121 are etched (FIG. 18C).
[0013]
Next, after the source / drain 111 is formed by ion implantation of an impurity, an insulating film 112 is deposited so as to bury the polysilicon film 105 (FIG. 19A). It is subjected to chemical mechanical polishing until it is exposed (FIG. 19B).
[0014]
Next, after removing the polysilicon film 105 and the protective film 121 (FIG. 19C), another insulating film 114 is formed on the insulating film 112 so as to cover the inner wall of the groove 113 formed in the insulating film 112. (FIG. 20A), a sidewall 115 is formed on the inner wall of the groove 113 by anisotropic etching of the entire surface (FIG. 20B). At this time, the gate electrode portion is shrunk.
[0015]
Then, after sequentially forming the gate insulating film 116 (FIG. 20C) and the conductive film 117 (FIG. 21A), the conductive film 117 is subjected to chemical mechanical polishing until the upper surface of the gate insulating film 116 is exposed ( FIG. 21 (b).
[0016]
[Patent Document 1]
JP-A-11-260699
[Patent Document 2]
JP 2000-260701 A
[0017]
[Problems to be solved by the invention]
However, the phase edge technique for forming such a fine pattern also has some problems.
[0018]
The first problem is the size of the shifter. In the pattern to be the gate electrode, the pattern is thinned according to the design value by the dark portion formed by the Levenson phase shift mask, and there is no concern that the pattern is disconnected. However, in a pattern to be a gate wiring, the shifter arrangement is a very serious problem. There is no problem if the pitch is large and the distance between the wiring pattern and the shifter pattern is sufficient, but if this spacing is reduced due to the miniaturization of the device, the gate wiring will be too close to the shifter and will be affected by the shifter. There are problems such as the pattern becoming thinner only in the portion adjacent to the shifter and severe disconnection. As a countermeasure, a method such as limiting the size of the shifter can be considered. However, since a certain size of the shifter width is required to obtain high contrast, the countermeasure is insufficient.
[0019]
FIG. 22 is a schematic plan view for explaining the thinning of the gate wiring pattern, which is the first problem.
As shown in FIG. 22A, when another gate wiring pattern 203 exists near the active region 202 in addition to the gate wiring pattern 201, the Levenson phase shift mask of FIG. When the exposure is performed, a part of the gate wiring pattern 203 is processed to be narrow as shown in FIG. 22D because the distance between the shifter 204 and the gate wiring pattern 203 is too short as shown in FIG. Would. If such a pattern arrangement exists on both sides of the gate wiring pattern 201, there is a case where the wire is disconnected.
[0020]
Further, the above problem and the securing of the size of the shifter are obstacles to shrinking the device area.
[0021]
The second problem is distortion of the gate electrode pattern. Although not unique to the phase edge technology, the gate electrode pattern is deformed so as to be pulled by the gate wiring pattern during baking or etching after development in an ultra-fine resist pattern (the gate electrode pattern is twisted or distorted). . In particular, this phenomenon is increasing due to a trimming technique by etching (a technique of isotropically etching and shrinking a resist pattern), which has been recently introduced. As a result, not only the dimensional uniformity of the gate electrode pattern but also the gate electrode pattern is not formed at the designed position, and thus a problem such as narrowing a short margin with another layer occurs.
[0022]
FIG. 23 is a schematic plan view for explaining a case 2, which occurs when the gate wiring pattern connected to the gate electrode pattern is asymmetric, which is problem 2.
FIG. 23A illustrates a case where the size of the gate wiring pattern is different from that of the gate electrode pattern above and below the gate electrode pattern. The gate electrode pattern is exposed by overlapping the Levenson phase shift mask of FIG. 23B as shown in FIG. In this case, there is no problem when the size of the gate electrode is large, but in the case of a narrow gate electrode, the resist pattern is pulled by the gate wiring pattern where a large amount of resist exists due to baking after development. The gate electrode pattern is deformed (torsion or distortion occurs in the gate electrode pattern). Further, by performing etching, this deformation may be larger.
[0023]
Problem 3 is shrinkage of the gate electrode pattern. In recent years, a gate electrode having a width smaller than that which can be formed by a resist pattern is required. As described above, a trimming process may be performed at the time of etching. At this time, the gate wiring pattern is shrinked together with the gate electrode pattern, and the wiring resistance is increased. From the design stage, even if an attempt is made to increase the thickness by the amount of trimming, there is a case where it cannot be easily improved due to the problem of the wiring pitch (when the pitch is small and the resist pattern cannot be resolved and short-circuited).
[0024]
The present invention has been made in view of the above problems, and it is easy to eliminate the limitation of the shifter width, and at the same time, it is possible to prevent the thinning of the gate wiring pattern, the occurrence of disconnection and receding, and the distortion of the gate electrode pattern, An object of the present invention is to provide a photomask, a semiconductor device, and a method for manufacturing the same, which facilitate shrink processing of a device area and improve dimensional uniformity of an ultrafine gate.
[0025]
[Means for Solving the Problems]
As a result of intensive studies, the present inventor has reached various aspects of the invention described below.
[0026]
The photomask of the present invention is a photomask for forming a gate including a gate electrode and a gate wiring, and has a first mask and a first mask having respective mask patterns for forming only a gate electrode pattern by double exposure. 2 and a third mask having a mask pattern for forming a gate wiring pattern.
[0027]
The semiconductor device of the present invention is a semiconductor device having a gate including a gate electrode and a gate wiring, wherein the gate electrode is formed in an island shape, and the gate wiring is formed on the gate electrode in a layer above the gate electrode. It is formed so that it may be connected to.
[0028]
The method for manufacturing a semiconductor device according to the present invention includes a step of forming only a gate electrode pattern by a double exposure process using a first mask and a second mask when forming a gate including a gate electrode and a gate wiring. Forming a gate wiring pattern by exposure using a third mask.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
-Basic gist of the present invention-
The present inventor solves the above-mentioned three problems associated with the phase edge technology at once, namely, the size of the shifter of the Levenson phase shift mask, the distortion of the gate electrode pattern, and the problem of shrinkage of the gate electrode pattern. The inventors have conceived of forming a gate electrode pattern and a gate wiring pattern using different masks.
[0030]
A specific example is shown in FIG. Here, a solution corresponding to Problem 1 will be described. First, a gate electrode pattern is formed using two masks. FIG. 1A shows a pattern image 1 of a first mask which is a binary mask or a halftone phase shift mask, and FIG. 1B shows a pattern image 2 of a second mask which is a Levenson phase shift mask. As shown in FIG. 1A, the pattern image 1 of the first mask has a wide symmetrical shape corresponding to the active region 11. On the other hand, as shown in FIG. 1B, the pattern image 2 of the second mask is a mask formed such that the phases of the left and right transmission regions become 0 and π, and the narrow image sandwiched between them is formed. Is a gate electrode pattern. In this manner, by exposing the first mask and the second mask in a superposed manner, a narrow gate electrode pattern following the pattern image 2 of the second mask is formed.
[0031]
Subsequently, a gate wiring pattern is formed. FIG. 1C shows a pattern image 3 of a third mask which is a binary mask or a halftone phase shift mask. The third mask is disposed above the formed gate electrode so that the third mask is connected to the gate wiring pattern. By performing exposure using the third mask, a wide gate wiring pattern following the pattern image 3 of the third mask is formed. FIG. 1D shows a state in which the gate electrode pattern 12 and the gate wiring pattern 13 are exposed by overlapping all of the first to third masks.
[0032]
In such a photomask structure, the gate electrode pattern 12 and the gate wiring pattern 13 are formed using different masks. Therefore, the shifter of the second mask used when forming the gate electrode pattern and the gate wiring pattern 13 are formed. Does not interfere, for example, preventing the thinning or disconnection of the gate wiring pattern 13 adjacent to the element active region 11, and at the same time, preventing the size of the shifter from being restricted depending on the gate wiring pattern 13. .
[0033]
Another specific example is shown in FIG. Here, a solution corresponding to Problem 2 will be particularly described.
FIGS. 2A and 2B are the same as FIGS. 1A and 1B. In FIG. 2C, only one gate pattern is shown for the sake of convenience in order to particularly refer to Problem 2. FIG. 1D shows an image in which the gate electrode pattern 12 and the gate wiring pattern 13 are exposed by overlapping all of the first to third masks.
[0034]
In such a photomask structure, since the gate electrode pattern 12 and the gate wiring pattern 13 are formed using different masks, the first mask corresponding to the gate electrode pattern 12 is formed as shown in FIG. Since there is no restriction on the shape of the pattern image 1 and it can be made symmetrical as shown in the figure, the gate wiring pattern 13 has a simple linear shape. This makes the stress applied to the gate electrode pattern 12 uniform, prevents the gate electrode pattern from being distorted or twisted, and allows the gate electrode to be formed with uniform dimensions.
[0035]
In the structure of the photomask as shown in FIGS. 1 and 2, it is possible to solve the problem 3, that is, to shrink only the gate electrode pattern without narrowing the wiring pattern when shrinking the gate.
[0036]
Further, the structure of the photomask contributes to a reduction in the element area. FIG. 3 is a schematic plan view for explaining the device reduction effect. As shown in FIGS. 3A and 3B, in the conventional phase edge technology, it is inevitable to provide an extra region in order to increase the dimensional uniformity of the gate electrode pattern at the lead-out portion of the gate electrode pattern. On the other hand, in the present invention, as shown in FIGS. 3C and 3D (FIG. 3C corresponds to FIG. 3A and FIG. 3D corresponds to FIG. 3B). By arranging the junctions vertically with each other, the junctions can be arranged also on the active region 11, and the element area can be further reduced.
[0037]
As described above, according to the present invention, in forming a fine gate pattern with a fine pitch using the phase edge technology, the formation of the gate electrode pattern and the formation of the gate wiring pattern are performed separately, so that the shifter width is reduced. , The thinning, disconnection, receding, and the like of the wiring pattern portion are prevented, and the occurrence of distortion of the gate electrode pattern is prevented, so that the device area can be easily shrunk.
[0038]
-Specific embodiments of the present invention-
(1st Embodiment)
Here, a method for manufacturing a MOS transistor using a trimming process will be described. In each figure, the upper part shows the part of the gate electrode, and the latter part shows the part of the gate wiring.
[0039]
First, a gate insulating film 24 is formed on a silicon substrate 21 (FIG. 4A) on which an active region 23 is formed by forming an element isolation structure 22 by, for example, STI (Shallow Trench Isolation) method (FIG. b)). Next, a polysilicon film 25 having a thickness of about 100 nm, a hard mask 26 made of a silicon oxide film having a thickness of about 20 nm to 30 nm, an organic antireflection film 27 having a thickness of about 80 nm, and a film serving as a chemically amplified ArF positive resist. A resist 28 having a thickness of about 250 nm is sequentially formed (FIG. 4C).
[0040]
On the silicon substrate 21 in this state, the gate electrode pattern is transferred to the resist 28 by the phase edge technique described previously with reference to FIG. 1 to form a resist pattern 29 (FIG. 5A). The photomask used at this time is composed of a first mask which is a halftone phase shift mask for ArF (HTPSM: transmittance 6%) and a second mask which is a Levenson type phase shift mask for ArF. The respective exposure conditions are as follows. For a halftone phase shift mask, 輪 annular illumination (σ = 0.425 / 0.85) with NA = 0.75 and an exposure amount of 180 J / m ² And for the Levenson-type phase shifter mask, NA = 0.75 and σ = 0.4, and the exposure amount is 80 J / m. ² ~ 100J / m ² Degree. Here, it is necessary that both end portions of the gate electrode pattern have a substantially symmetrical shape (as described above, the asymmetrical shape causes torsion and distortion of the pattern. ).
[0041]
Subsequently, using the resist pattern 29 as a mask, the antireflection film 27, the hard mask 26, the polysilicon film 25, and the gate insulating film 24 are etched to form an island-shaped gate electrode 41.
[0042]
At this time, a trimming process is used in the etching step for the purpose of improving the performance of the gate electrode. By the trimming process, the polysilicon film 25 can be processed into a pattern narrower than the gate electrode formed by the resist pattern 29 (FIG. 5B). The trimming performed here is of a type that shrinks only a resist which is an organic material and a bulk portion made of polysilicon and a silicon oxide film. The condition is Cl ₂ / O ₂ And a gas flow rate of about 20 sccm / 30 sccm to about 50 sccm, and a source / bias of about 200 W / 30 W, respectively. The pressure was about 1.33 Pa (10 mTorr), the end point was used, and the over-etching condition was 30%. By this trimming, trimming of about 40 nm is performed on both sides including the bulk portion. Thereafter, the polysilicon film 25 is dry-etched using the resist pattern 29 and the bulk portion as an etching mask.
[0043]
Although not used this time, a silicon oxide film having a thickness of about 50 nm may be formed on the polysilicon film in order to stably etch the polysilicon film. The silicon oxide film is used as a hard mask, the trimmed resist pattern and the bulk portion are transferred once to the hard mask, and the polysilicon film is etched using the hard mask pattern as a mask. Thereafter, the silicon oxide film is removed by wet etching.
[0044]
Subsequently, sidewalls 30 are formed on both side surfaces of the polysilicon film 25 by anisotropic etching after a silicon oxide film is deposited on the entire surface, and source / drain 31 is formed by ion implantation of impurities (FIG. 5 ( c)).
[0045]
Subsequently, an insulating film 32, which is a high-density plasma oxide film (HDP), is deposited so as to bury the polysilicon film 25 (FIG. 6A). This insulating film 32 is used until the upper surface of the polysilicon film 25 is exposed. Chemical mechanical polishing is performed (FIG. 6B).
[0046]
Subsequently, after a polysilicon film 33 is formed to a thickness of about 100 nm (FIG. 6C), an organic antireflection film 34 and a resist 35 which is a chemically amplified ArF positive resist are again formed on the polysilicon film 33. Are formed to a thickness of about 80 nm and about 250 nm, respectively (FIG. 7A).
[0047]
On the silicon substrate 21 in this state, the gate wiring pattern is transferred to the resist 35 by the phase edge technique described earlier with reference to FIG. 1, for example, to form a resist pattern 36 (FIG. 7B). At this time, a third mask which is a halftone phase shift mask for ArF (HTPSM: transmittance 6%) is used as the photomask. The exposure conditions were as follows: 1/2 annular illumination with NA = 0.75 (σ = 0.425 / 0.85), and exposure amount of 150 J / m ² ~ 200J / m ² Degree.
[0048]
The photomask used in this case needs to have a shape that two-dimensionally covers the previously formed gate electrode pattern. Further, it is desirable that a portion formed for bonding with the upper layer is formed in a portion that two-dimensionally overlaps the active region (device area can be easily reduced).
[0049]
Then, using the resist pattern 36 as an etching mask, the antireflection film 34 and the polysilicon film 33 are etched to form a gate wiring 42 on the gate electrode 41 so as to be connected thereto.
By performing these steps in order, a very fine gate 43 composed of the gate electrode 41 and the gate wiring 42 is formed.
[0050]
Thereafter, a MOS transistor is completed through formation of an interlayer insulating film, a contact hole, a wiring layer, and the like.
[0051]
As described above, according to the present embodiment, it is easy to eliminate the limitation of the shifter width, and it is possible to prevent the thinning, disconnection and receding of the gate wiring pattern and the distortion of the gate electrode pattern, and to reduce the shrinkage of the device area. Processing is also facilitated, and the dimensional uniformity of the ultrafine gate can be improved.
[0052]
(Second embodiment)
Here, a method of manufacturing a MOS transistor using a trench gate process will be described. In each figure, the upper part shows the part of the gate electrode, and the latter part shows the part of the gate wiring.
[0053]
First, on the silicon substrate 21 (FIG. 8A) on which the active region 23 is formed by forming the element isolation structure 22, a protective film 51 made of a silicon oxide film having a thickness of about 1 nm to 2 nm is formed (FIG. 8A). 8 (b)). Next, after forming a polysilicon film 25 having a thickness of about 100 nm (FIG. 8C), an organic antireflection film 27 having a thickness of about 80 nm and a resist having a thickness of about 250 nm, which is a chemically amplified ArF positive resist. 28 are sequentially formed (FIG. 9A).
[0054]
On the silicon substrate 21 in this state, the gate electrode pattern is transferred to the resist 28 by the phase edge technique described above with reference to FIG. 1 to form a resist pattern 29 (FIG. 9B). The photomask used at this time is composed of a first mask that is a binary mask (COG) and a second mask that is a Levenson-type phase shift mask for ArF. Here, the first mask and the second mask are formed on the same photomask. The respective exposure conditions were as follows: for a binary mask, 輪 annular illumination (σ = 0.425 / 0.85) with NA = 0.75, and an exposure amount of 180 J / m ² And for the Levenson-type phase shifter mask, NA = 0.75 and σ = 0.4, and the exposure amount is 80 J / m. ² ~ 100J / m ² Degree. Here, it is necessary that both ends of the gate electrode pattern to be transferred have a substantially symmetrical shape (as described above, the asymmetrical shape may cause twisting or distortion of the pattern. It becomes.).
[0055]
Subsequently, using the resist pattern 29 as a mask, the antireflection film 27, the polysilicon film 25, and the protective film 51 are etched to form the polysilicon film 25 into an island gate electrode shape (FIG. 9C).
[0056]
Although not used this time, a silicon oxide film having a thickness of about 50 nm may be formed on the polysilicon film in order to stably etch the polysilicon film. The silicon oxide film is used as a hard mask, a resist pattern is transferred once to the hard mask, and the polysilicon film is etched using the hard mask pattern as a mask.
[0057]
Subsequently, impurities are ion-implanted into the silicon substrate 21 on both sides of the polysilicon film 25 to form a source / drain 31.
[0058]
Subsequently, an insulating film 32, which is a high-density plasma oxide film (HDP), is deposited so as to bury the polysilicon film 25 (FIG. 10A). This insulating film 32 is used until the upper surface of the polysilicon film 25 is exposed. A chemical mechanical polishing is performed (FIG. 10B).
[0059]
Subsequently, after the polysilicon film 25 and the protective film 51 are removed by wet etching (FIG. 10C), other portions of the polysilicon film 25 and the protective film 51 are formed on the insulating film 32 so as to cover the inner walls of the grooves 52 formed in the insulating film 32 by the removal. (FIG. 11A), and a sidewall 54 having a thickness of about 15 nm is formed on the inner wall of the groove 52 by anisotropic etching of the entire surface (FIG. 11B). At this time, the portion serving as the gate electrode is shrunk by about 30 nm.
[0060]
Subsequently, a gate insulating film 55 made of a silicon oxynitride film (SiON) and having a thickness of about 1 nm (FIG. 11C), and a conductive film 56 made of tungsten and having a thickness of about 100 nm (FIG. 12A) are sequentially formed. Form.
[0061]
Subsequently, an organic antireflection film 57 and a resist 58, which is a chemically amplified ArF positive resist, are again formed on the conductive film 56 to a thickness of about 80 nm and about 250 nm, respectively (FIG. 12B).
[0062]
On the silicon substrate 21 in this state, the gate wiring pattern is transferred to the resist 58 by the phase edge technique described previously with reference to FIG. 1 to form a resist pattern 59 (FIG. 12C). At this time, a third mask which is a halftone phase shift mask for ArF (HTPSM: transmittance 6%) is used as the photomask. The exposure conditions were as follows: 1/2 annular illumination with NA = 0.75 (σ = 0.425 / 0.85), and exposure amount of 150 J / m ² ~ 200J / m ² Degree.
[0063]
The photomask used in this case needs to have a shape that two-dimensionally covers the previously formed gate electrode pattern. Further, it is desirable that a portion formed for bonding with the upper layer is formed in a portion that two-dimensionally overlaps the active region (device area can be easily reduced).
[0064]
Then, using the resist pattern 59 as an etching mask, the antireflection film 57 and the conductive film 56 are etched to form the gate electrode 61 following the island-shaped electrode shape of the groove 51 and the gate wiring 62 so as to be formed integrally with the upper layer. Is formed (FIG. 13). By performing these steps in order, a very fine gate 63 in which the gate electrode 61 and the gate wiring 62 are integrally formed is formed.
[0065]
As described above, according to the present embodiment, it is easy to eliminate the limitation of the shifter width, and it is possible to prevent the thinning, disconnection and receding of the gate wiring pattern and the distortion of the gate electrode pattern, and to reduce the shrinkage of the device area. Processing is also facilitated, and the dimensional uniformity of the ultrafine gate can be improved.
[0066]
Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.
[0067]
(Supplementary Note 1) In forming a gate including a gate electrode and a gate wiring,
Forming only the gate electrode pattern by a double exposure process using the first mask and the second mask;
Forming a gate wiring pattern by exposure using a third mask;
A method for manufacturing a semiconductor device, comprising:
[0068]
(Supplementary note 2) The method of manufacturing a semiconductor device according to supplementary note 1, wherein at least one of the first and second masks is a phase shift mask.
[0069]
(Supplementary Note 3) The method for manufacturing a semiconductor device according to Supplementary Note 1 or 2, wherein the transferred gate electrode pattern is located on an active region.
[0070]
(Supplementary note 4) The method of manufacturing a semiconductor device according to Supplementary note 3, wherein the two-dimensional shape of the gate electrode pattern to be transferred is such that both end portions drawn from the active region are symmetrical.
[0071]
(Supplementary Note 5) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the formation region of the gate wiring pattern includes the formation region of the gate electrode pattern.
[0072]
(Supplementary Note 6) A photomask for forming a gate including a gate electrode and a gate wiring,
A first mask and a second mask each having a mask pattern for forming only a gate electrode pattern by double exposure,
A third mask having a mask pattern for forming a gate wiring pattern;
A photomask comprising:
[0073]
(Supplementary note 7) The photomask according to supplementary note 6, wherein at least one of the first mask and the second mask is a phase shift mask.
[0074]
(Supplementary Note 8) In each of the mask patterns of the first mask and the second mask, a two-dimensional shape of the gate electrode pattern transferred by the double exposure is drawn from an active region, and both end portions are symmetrical. 8. The photomask according to attachment 6 or 7, wherein
[0075]
(Supplementary Note 9) The formation region of the gate wiring pattern transferred by the mask pattern of the third mask is transferred by double exposure of each of the mask patterns of the first mask and the second mask. 9. The photomask according to any one of supplementary notes 6 to 8, wherein the photomask covers a formation region of the gate electrode pattern.
[0076]
(Supplementary Note 10) A semiconductor device having a gate including a gate electrode and a gate wiring,
The gate electrode is formed in an island shape,
The semiconductor device, wherein the gate wiring is formed above the gate electrode so as to be connected to the gate electrode.
[0077]
(Supplementary Note 11) The semiconductor device according to supplementary note 10, wherein the gate electrode is formed on an active region of the substrate.
[0078]
(Supplementary note 12) The semiconductor device according to supplementary note 11, wherein the two-dimensional shape of the gate electrode is such that both end portions drawn from the active region are symmetrical.
[0079]
(Supplementary Note 13) The semiconductor device according to any one of Supplementary Notes 10 to 12, wherein the gate wiring is formed so as to cover the gate electrode.
[0080]
(Supplementary note 14) The semiconductor device according to any one of Supplementary notes 10 to 13, wherein the gate electrode is formed so as to fill an electrode-shaped groove formed in an insulating film provided on the substrate. Semiconductor device.
[0081]
【The invention's effect】
According to the present invention, when forming an extremely fine gate pattern with an extremely fine pitch using a phase edge technique, the formation of the gate electrode pattern and the formation of the gate wiring pattern are performed separately, thereby eliminating the limitation of the shifter width. In addition, the thinning, disconnection and receding of the gate wiring pattern and the distortion of the gate electrode pattern can be prevented, the device area can be easily shrunk, and the dimensional uniformity of the ultra-fine gate can be improved. It becomes.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing a method for forming a gate electrode and a wiring pattern using a double exposure technique according to the present invention.
FIG. 2 is a schematic plan view showing a method of forming a gate electrode and a wiring pattern using a double exposure technique according to the present invention.
FIG. 3 is a schematic plan view for explaining an effect of reducing a device area by a method of forming a gate electrode and a wiring pattern using a double exposure technique according to the present invention.
FIG. 4 is a schematic cross-sectional view showing a method for manufacturing the MOS transistor according to the first embodiment of the present invention in the order of steps.
FIG. 5 is a schematic cross-sectional view showing a method of manufacturing the MOS transistor according to the first embodiment of the present invention in the order of steps, following FIG. 4;
FIG. 6 is a schematic cross-sectional view showing a manufacturing method of the MOS transistor according to the first embodiment of the present invention in the order of steps, following FIG. 5;
FIG. 7 is a schematic cross-sectional view showing a manufacturing method of the MOS transistor according to the first embodiment of the present invention in the order of steps, following FIG. 6;
FIG. 8 is a schematic cross-sectional view showing a method for manufacturing a MOS transistor according to the second embodiment of the present invention in the order of steps.
FIG. 9 is a schematic cross-sectional view showing a method of manufacturing the MOS transistor according to the second embodiment of the present invention in the order of steps, following FIG. 8;
FIG. 10 is a schematic cross-sectional view showing a method of manufacturing the MOS transistor according to the second embodiment of the present invention in the order of steps, following FIG. 9;
FIG. 11 is a schematic cross-sectional view showing a manufacturing method of the MOS transistor according to the second embodiment of the present invention in the order of steps, following FIG. 10;
FIG. 12 is a schematic cross-sectional view showing a method of manufacturing the MOS transistor according to the second embodiment of the present invention in the order of steps, following FIG. 11;
FIG. 13 is a schematic cross-sectional view showing a method of manufacturing the MOS transistor according to the second embodiment of the present invention in the order of steps, following FIG. 12;
FIG. 14 is a schematic plan view showing a method for forming a gate electrode and a wiring pattern using a conventional double exposure technique.
FIG. 15 is a schematic plan view showing a conventional gate forming method by a phase edge technique using a Levenson phase shift mask.
FIG. 16 is a schematic plan view showing a conventional method of forming a gate by a phase edge technique using a Levenson phase shift mask, following FIG. 15;
FIG. 17 is a schematic plan view showing a conventional method of forming a gate by a phase edge technique using a Levenson phase shift mask.
FIG. 18 is a schematic plan view showing a conventional method of forming a gate by a phase edge technique using a Levenson phase shift mask, following FIG. 17;
FIG. 19 is a schematic plan view showing a conventional gate forming method by a phase edge technique using a Levenson phase shift mask, following FIG. 18;
FIG. 20 is a schematic plan view showing a conventional method of forming a gate by a phase edge technique using a Levenson phase shift mask, following FIG. 19;
FIG. 21 is a schematic plan view showing a conventional method of forming a gate by a phase edge technique using a Levenson phase shift mask, following FIG. 20;
FIG. 22 is a schematic plan view for explaining a thinning of a gate wiring pattern which is a problem 1.
FIG. 23 is a schematic plan view for explaining a problem 2, which occurs when a gate wiring pattern connected to a gate electrode pattern is asymmetric.
[Explanation of symbols]
1. Pattern image of the first mask
2 Pattern image of the second mask
3 Pattern image of the third mask
11,23 Active area
12 Gate electrode pattern
13 Gate wiring pattern
21 Silicon substrate
22 Element isolation structure
24,55 Gate insulating film
25,33 polysilicon film
26 Hard Mask
27, 34, 57 Anti-reflective coating
28, 35, 58 resist
29,36,59 resist pattern
30 Sidewall
31 source / drain
32,53 insulating film
41,61 Gate electrode
42,62 Gate wiring
43, 63 gate
51 Protective film
52 grooves
56 conductive film

Claims (9)

When forming a gate composed of a gate electrode and a gate wiring,
Forming only the gate electrode pattern by a double exposure process using the first mask and the second mask;
Forming a gate wiring pattern by an exposure treatment using a third mask. 2. The method according to claim 1, wherein the transferred gate electrode pattern is located on an active region. 3. The method according to claim 2, wherein the two-dimensional shape of the transferred gate electrode pattern has a symmetrical shape at both ends drawn from the active region. A photomask for forming a gate including a gate electrode and a gate wiring,
A first mask and a second mask each having a mask pattern for forming only a gate electrode pattern by double exposure,
A third mask having a mask pattern for forming a gate wiring pattern. The photomask according to claim 4, wherein at least one of the first mask and the second mask is a phase shift mask. A semiconductor device having a gate including a gate electrode and a gate wiring,
The gate electrode is formed in an island shape,
The semiconductor device, wherein the gate wiring is formed above the gate electrode so as to be connected to the gate electrode. 7. The semiconductor device according to claim 6, wherein said gate electrode is formed on an active region of a substrate. 8. The semiconductor device according to claim 7, wherein the two-dimensional shape of the gate electrode has a symmetrical shape at both ends drawn from the active region. 9. The semiconductor device according to claim 6, wherein the gate wiring is formed so as to cover the gate electrode.

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