KR20070112529A - Panel assembly for display device - Google Patents

Abstract

A display panel for display device is provided to facilitate a test process and to prevent damage of an output pad by installing an additional test pad at a side opposite to a data driving IC region. A plurality of pixels are arranged in a matrix. A signal line is connected to the pixels. An output pad(OP) is connected to the signal line. A test pad(TP) is positioned at a side opposite to the output pad and is connected to the signal line. A gap between the output pads is larger than a gap between the test pads. The signal line is a data line for transmitting a data voltage or a gate line for transmitting a gate voltage. A data driving IC generates the data voltage. The data driving IC is mounted on a tape carrier package or a display panel.

Description

Display panel for display device {PANEL ASSEMBLY FOR DISPLAY DEVICE}

With reference to the accompanying drawings will be described in detail the embodiments of the present invention to make the present invention clear.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a schematic layout view of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 4 is a schematic layout view of input / output pads and test pads located in the data driver IC region illustrated in FIG. 3.

5 is an example of an inspection apparatus used to inspect the display apparatus according to an exemplary embodiment of the present invention.

The present invention relates to a display panel for a display device.

Recently, organic light emitting diode display, plasma display panel (PDP), liquid crystal display (liquid crystal display, LCD) instead of heavy and large cathode ray tube (CRT) The same flat panel display is actively being developed.

The PDP is a device for displaying characters or images using plasma generated by gas discharge, and the organic light emitting diode display displays characters or images by using electroluminescence of specific organic materials or polymers. The liquid crystal display device applies an electric field to a liquid crystal layer interposed between two display panels, and adjusts the intensity of the electric field to adjust a transmittance of light passing through the liquid crystal layer to obtain a desired image.

Among such flat panel displays, for example, a liquid crystal display and an organic light emitting display may turn on / off a switching element of a pixel by emitting a gate signal to a pixel including a switching element, a display panel having a display signal line, and a gate line among the display signal lines. A gate driver to be turned off, a data driver to apply a data voltage to the data lines of the display signal lines, and a signal controller to control them.

On the other hand, the gate driver and the data driver are generally composed of a plurality of integrated circuits in the form of chips, which are mounted on a flexible printed circuit film (FPC) or directly mounted on a display panel [COG (chip on glass)].

Meanwhile, in the process of manufacturing the display device, various inspection processes are performed to detect defects such as disconnection or short circuit, such as an array test, a visual inspection (VI) test, a gross test, and a module test. .

At this time, the end of the gate line and the data line is made of a pad having a wide end portion in order to improve the contact characteristics of the external device.

On the other hand, in particular, the gross test uses a gross test equipment having the same conditions as the drive IC to perform the test under the same conditions as the drive IC, and applies a test signal by contacting a pad and a needle, a probe, connected thereto.

For example, if the data driver IC is mounted on the FPC, the gross test equipment also mounts the test data driver IC on the FPC [tape carrier package (TCP) method]. There is a connection between the FPC and the probe, and a signal is applied to the data line through a probe located at the end of the connection.

At this time, as the resolution increases, the gap between the pads tends to be narrowed. As a result, the probe cannot be properly contacted with the pad, which makes it difficult to perform the test and may damage the pad during the pad contact process. .

Accordingly, an object of the present invention is to provide a display device that can solve the problems of the prior art.

According to an aspect of the present invention, a display panel for a display device includes a plurality of pixels arranged in a matrix form, a signal line connected to the pixels, an output pad connected to the signal lines, and the output. And a test pad connected to the signal line on the opposite side of the pad.

Here, the interval of the test pad may be wider than the interval of the output pad.

In this case, the signal line may be a data line transferring a data voltage.

The display device may include a data driver IC to generate the data voltage, and the data driver IC may be mounted on a tape carrier package or mounted on the display panel.

Alternatively, the signal line may be a gate line transferring a gate voltage, and the display device may include a gate driving IC to generate the gate voltage, and the gate driving IC may be mounted on a tape carrier package or mounted on the display panel. There may be.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A display device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings, and a liquid crystal display device will be described as an example.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data signal ( D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX, for example, the pixel PX connected to the i-th (i = 1, 2,, n) gate line G _i and the j-th (j = 1, 2,, m) data line Dj. ) Includes a switching element Q connected to the signal line G _i D _j , a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m and the thin film transistor switching element Q. It may be. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a load for applying a data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of image data transmission for the pixels PX in one row [bundling]. Signal LOAD and data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage ") RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixels PX in one row (bundling), and each digital image signal DAT. By converting the digital image signal (DAT) into an analog data signal by selecting the gray scale voltage corresponding to), it is applied to the corresponding data lines (D ₁ -D _m ).

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the switching element Q turned on.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

FIG. 3 is a schematic layout view of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 4 is a schematic layout view of an input / output pad and an inspection pad located in a data driving IC region shown in FIG. 3, and FIG. An example of an inspection apparatus used for an inspection of a display apparatus according to an exemplary embodiment is described.

3 to 5, a plurality of tape tape carrier packages (TCPs) 540 on which the data driver ICs 510 are mounted are attached to the upper edge of the liquid crystal panel assembly 300. The other side of the data TCP 540 is attached to a data printed circuit film (PCB) 530. The data PCB 530 includes the signal controller 600 and the gray voltage generator 800 described above, and transmits a signal to the liquid crystal panel assembly 300 through the data TCP 540. A plurality of gate TCPs 410 on which the gate driving ICs 410 are mounted are attached to the left edge of the liquid crystal panel assembly 300.

Each data drive IC region 540a, 540b, 540c, 540d to which the data TCP 540 is attached includes a wide end input pad IP and an output pad OP, from the data PCB 530. Various signals are transmitted to the liquid crystal panel assembly 300.

In this case, the data line DL extends substantially parallel to each other in the display area DA through a so-called fan-out area FAO that extends straight on the output pad OP and spreads in a fan shape.

In addition, the test pad group TPG is positioned at the lower peripheral area PA of the liquid crystal panel assembly 300, that is, opposite to the data driving IC area, and each test pad TP of the test pad group TPG has a data line ( DL).

As shown in FIG. 5, the gross test equipment 550 extends from the test data driver IC 552, the TCP 551 on which the test data driver IC 552 is mounted, and the data driver IC 552. Most of the signal line 553 and the signal line 553 are provided and includes a connection portion 554 narrowing at the end and a probe 555 connected to the signal line 553.

At this time, it can be seen that the interval P2 between the test pads TP is larger than the interval P1 between the output pads OP.

Therefore, when the probe 555 is contacted and inspected, it is more convenient to perform the inspection by contacting the probe 555 to the test pad TP side than the relatively narrow output pad OP side. That is, in the related art, since the probe 555 is contacted with the output pad OP to perform the inspection, it is not easy to contact the probe 555, which causes a problem such that the output pad OP is scratched, and later, Defects may occur. However, according to the exemplary embodiment of the present invention, since the test pads TP having a relatively wide interval P2 are separately placed, the test pads are easily contacted with each other, and the output pad OP is not connected at all. Do not damage.

Meanwhile, in the embodiment of the present invention, the case in which the data driver IC 510 is mounted in the TCP method has been described. However, the present invention may also be applied to the case in which the wiring interval is mounted in the narrower COG method. In addition, the present invention may be applied to the gate driving IC 410, for example, an inspection pad may be provided on the opposite side to the gate driving IC 410, that is, to the right.

In this way, by placing the separate test pad TP on the opposite side of the data driving IC regions 540a, 540b, 540c, and 540d, the test can be easily performed and the damage of the output pad OP can be prevented.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (8)

A plurality of pixels arranged in a matrix form, A signal line connected to the pixel, An output pad connected to the signal line, and A test pad connected to the signal line on the opposite side of the output pad Display panel for a display device comprising a. In claim 1, A display panel for a display device having a larger spacing between the test pads than the spacing of the output pads. In claim 2, And the signal line is a data line for transmitting a data voltage. In claim 3, The display device includes a data driver IC to generate the data voltage. The data driving IC is mounted in a tape carrier package. Display panel for display device. In claim 3, The display device includes a data driver IC to generate the data voltage. The data driver IC is mounted on the display panel. Display panel for display device. In claim 2, And the signal line is a gate line for transmitting a gate voltage. In claim 6, The display device includes a gate driving IC to generate the gate voltage. The gate drive IC is mounted in a tape carrier package Display panel for display device. In claim 6, The display device includes a gate driving IC to generate the gate voltage. The gate driving IC is mounted on the display panel. Display panel for display device.

Images