KR20070111150A - Liquid crystal display - Google Patents

Abstract

An LCD(Liquid Crystal Display) is provided to place a gate driving unit and a storage voltage applying unit in opposite sides to be integrated in a limited peripheral area even though a resolution increases, and prevent overlapping of a gate output by installing a compensating circuit. Plural pixels include switching devices and pixel electrodes. A gate line and a data line are respectively connected to the switching device. A storage voltage line is stretched in parallel to the gate line and overlapped with the pixel electrode. A gate driving unit(400) applies gate voltage to the gate line. A storage voltage applying unit(700) applies storage voltage to the storage voltage line. A compensation circuit(470) is located between the gate driving unit and the storage voltage applying unit.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

With reference to the accompanying drawings will be described in detail the embodiments of the present invention to make the present invention clear.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a gate driver and a sustain voltage applying unit illustrated in FIG. 1.

FIG. 4 is a waveform diagram showing input and output signals of the NAND circuit shown in FIG.

5A and 5B are views illustrating output waveforms according to an embodiment of the present invention and waveforms according to the prior art.

<Description of Drawing>

3: liquid crystal layer 100: lower display panel

191: pixel electrode 200: upper display panel

230: color filter 270: common electrode

300: liquid crystal panel assembly 400: gate driver

500: data driver 600: signal controller

700: sustain voltage applying unit 800: gray voltage generator

R, G, B: Input image data DE: Data enable signal

OE: output enable signal

MCLK: Main Clock Hsync: Horizontal Sync Signal

Vsync: Vertical Sync Signal CONT1: Gate Control Signal

CONT2: data control signal DAT: digital video signal

Clc: Liquid Crystal Capacitor Cst: Keeping Capacitor

Q: switching device

The present invention relates to a liquid crystal display device.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

Such a liquid crystal display includes a display panel including a pixel including a switching element, a display signal line, a gate driver to turn on / off a switching element of a pixel by sending a gate signal to a gate line among the display signal lines, and to generate a plurality of gray voltages. A gray voltage generator, a data driver which selects a voltage corresponding to the image data among the gray voltages as a data voltage and applies a data voltage to the data lines of the display signal lines, and a signal controller to control the gray voltages.

In this case, unlike the large liquid crystal display, the small and medium-sized liquid crystal display uses line inversion that inverts the polarity of the common voltage and the data voltage in pixel rows. At this time, the common voltage is inverted by one pixel row having a high level and a low level.

On the other hand, the storage capacitor serving as an auxiliary of the liquid crystal capacitor is formed by overlapping the storage voltage line provided on the lower panel and the pixel electrode with an insulator interposed therebetween, and a predetermined voltage such as a common voltage is applied to the storage voltage line.

In this case, in the small and medium-sized liquid crystal display, a sustain voltage applying unit for applying a sustain voltage to the sustain voltage line is integrated with the gate driver. As a result, the width of the peripheral area outside the display area where most of the pixels and the display signal lines are provided is only about 1.4 mm, making it difficult to arrange these driving circuits. In particular, the higher the resolution, the more so.

In addition, when the gate signal is delayed, a common voltage of two levels may be applied during one horizontal period, thereby making it impossible to properly perform line inversion.

Therefore, the technical problem to be achieved by the present invention is to provide a liquid crystal display device that can solve the problems of the prior art.

According to an exemplary embodiment of the present invention, a liquid crystal display including a display area and a peripheral area includes a plurality of pixels each including a switching element and a pixel electrode, and a gate line connected to the switching element, respectively. And a sustain voltage line extending parallel to the data line, the gate line and overlapping the pixel electrode, a gate driver applying a gate voltage to the gate line, a sustain voltage applying unit applying a sustain voltage to the sustain voltage line, and the gate driver. And a correction circuit positioned between the sustain voltage applying unit, wherein the pixel is located in the display area, and the gate driver and the sustain voltage applying unit are located in the peripheral area, but are disposed opposite to each other.

The correction circuit may receive an output enable signal and the gate voltage defining an output of the gate voltage.

The gate driver may include a first direction selector, a shift register, a first level shifter, and a first buffer connected to the first direction selector.

The sustain voltage applying unit may include a second direction selector, a latch, a second level shifter, and a second buffer connected to the second direction selector.

The latch may generate a common voltage as the sustain voltage in synchronization with a high period of the gate voltage from the correction circuit.

The liquid crystal display may further include a data driver configured to apply a data voltage to the data line, and the data voltage and the common voltage may be inverted in units of one pixel row.

The gate driver and the sustain voltage applying unit may be integrated in the liquid crystal display.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400 connected thereto, a sustain voltage applying unit 700, and a liquid crystal panel assembly 300. The data driver 500, the gray voltage generator 800 connected to the data driver 500, and a signal controller 600 for controlling the data driver 500 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m , C ₁ -C _n , and a plurality of pixels connected to the plurality of signal lines (e.g. pixel) PX. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n , D ₁ -D _m , and C ₁ -C _n transfer data signals and a plurality of gate lines G ₁ -G _n that carry gate signals (also called “scan signals”). And a plurality of data lines D ₁ -D _m and a storage voltage line C ₁ -C _n which transfers a storage voltage. The gate line and the sustain voltage line G ₁ -G _n , C ₁ -C _n extend approximately in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend approximately in the column direction and are substantially parallel to each other. Do.

Each pixel PX, for example, the pixel PX connected to the i-th (i = 1, 2,, n) gate line G _i and the j-th (j = 1, 2,, m) data line Dj. ) Includes a switching element Q connected to the signal line G _i D _j , a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary role of the liquid crystal capacitor Clc, is formed by overlapping the storage voltage line C ₁ -C _n and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the sustain voltage lines C ₁ -C _n . However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The sustain voltage applying unit 700 is located on the opposite side of the gate driver 400 and is connected to the end of the gate lines G ₁ -G _n to receive the gate output Gout. The sustain voltage applying unit 700 receives a common voltage Vcom from a common voltage generator (not shown) and applies the sustain voltage line C _{1 to} C _n as a sustain voltage.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, 700, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP), or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, 700, and 800 may be formed by the liquid crystal together with the signal lines G ₁ -G _n , D ₁ -D _m , C ₁ -C _n and the thin film transistor switching element Q. It may be integrated in the display panel assembly 300. In addition, the driving devices 400, 500, 600, 700, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 further includes an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a load for applying a data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of image data transmission for the pixels PX in one row [bundling]. Signal LOAD and data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage &quot;) RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixels PX in one row (bundling), and each digital image signal DAT. By converting the digital image signal (DAT) into an analog data signal by selecting the gray scale voltage corresponding to), it is applied to the corresponding data lines (D ₁ -D _m ).

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the switching element Q turned on.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

3 is a block diagram of the gate driver 400 and the sustain voltage applying unit 700 shown in FIG. 1.

Referring to FIG. 3, the gate driver 400 includes a direction selector 410, a shift register 420, a logic circuit 430, a level shifter 440, and a buffer 450.

The sustain voltage applying unit 700 includes a direction selector 710, a latch 720, a level shifter 730, and a buffer 740.

In addition, a correction circuit 470 is positioned between the gate driver 400 and the sustain voltage applying unit 700, and the correction circuit 470 is located at either of the gate driver 400 and the sustain voltage applying unit 700. It does not matter. In addition, the driving circuit 400 may be included in one of the driving circuits 400 and 700 to be integrated in the liquid crystal panel assembly 300.

The direction selectors 410 and 710 of the gate driver 400 and the sustain voltage applying unit 700 may have a gate voltage Gout at the gate lines G ₁ -G _n and the sustain voltage lines C ₁ -C _n during driving. And the order of applying the sustain voltage Vst. For example, in the small and medium-sized liquid crystal display device, in the state in which the display panel unit including the liquid crystal panel assembly 300 is not rotated, the gate voltage Gout and the sustain from the first gate line G ₁ and the first sustain voltage line C ₁ . When the voltage Vst is applied to each other and the screen is rotated 180 degrees, the gate voltage Gout and the sustain voltage Vst are applied to the last gate line C _n and the sustain voltage line C _n . .

The shift register 420 sequentially generates the gate voltage Gout.

The level shifter 430 makes the output from the shift register 420 above or below a predetermined level, and the buffer 440 maintains the output from the level shifter 420 at a constant voltage so that the gate lines G ₁ -G _n. ) Is applied.

The correction circuit 470 receives the gate output Gout and the output enable signal OE, removes the overlapping portions of the gate output Gout, and sends them out. For example, as shown in Fig. 4, when the gate signal Gout (j) and the next gate signal Gout (j + 1) overlap each other due to a delay, the output enable signal OE overlaps with this. The gate outputs Gout '(j) and Gout' (j + 1) passing through the correction circuit 470 are separated from each other by the width of the high section of the output enable signal OE.

Meanwhile, the latch 720 of the sustain voltage applying unit 700 receives the common voltage Vcom and the gate output Gout '. The latch 720 outputs the common voltage Vcom as the sustain voltage Vst for one frame in synchronization with the gate output Gout. More specifically, the common voltage Vcom is output by the width of the high section of the gate output Gout '.

At this time, as shown in FIG. 5A, the common voltage Vcom is output by the width of the high section of the gate output Gout '(j). In FIG. 5A, the common voltage Vcoml having the low level is the latch output Lout. Is generated as: On the contrary, as shown in FIG. 5B, when the gate output Gout (j) is delayed to increase the width of the high section, the latch output Lout simultaneously generates the high and low common voltages Vcomh and Vcoml. Can be. However, this phenomenon can be prevented by passing through the correction circuit 470 according to the embodiment of the present invention.

The level shifter 730 and the buffer 740 operate in the same manner as the level shifter 440 and the buffer 450 of the gate driver 400 as described above, so that the sustain voltage Vst is applied to the sustain voltage lines C ₁ -C _n . Is authorized.

As such, when the gate driver 400 and the sustain voltage applying unit 700 are disposed opposite to each other, the gate driver 400 and the sustain voltage applying unit 700 may be integrated in the peripheral area outside the display area. In particular, the buffers 440 and 740 of the gate driver 400 and the sustain voltage applying unit 700 occupy most of the area in the driving circuits 400 and 700 to integrate the two driving circuits 400 and 700 on one side. Is not easy, and it is more so if the resolution is increased to increase the size of the buffers 440 and 740. However, when the gate driver 400 and the sustain voltage applying unit 700 are disposed opposite to each other, the gate driver 400 and the sustain voltage applying unit 700 may be disposed in the peripheral region as much as the resolution increases.

In addition, a correction circuit 470 may be provided to prevent overlapping of the gate output Gout.

In this manner, the gate driver 400 and the sustain voltage applying unit 700 are disposed opposite to each other to integrate in a limited peripheral area even when the resolution is increased, while the correction circuit 470 is provided to overlap the gate output Gout. You can prevent it.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (7)

A liquid crystal display device comprising a display area and a peripheral area, A plurality of pixels each comprising a switching element and a pixel electrode, A gate line and a data line respectively connected to the switching element; A sustain voltage line extending parallel to the gate line and overlapping the pixel electrode; A gate driver applying a gate voltage to the gate line; A sustain voltage applying unit for applying a sustain voltage to the sustain voltage line, and A correction circuit positioned between the gate driver and the sustain voltage applying unit Including; The pixel is positioned in the display area, The gate driver and the sustain voltage applying unit are located in the peripheral area, but are disposed opposite to each other. Liquid crystal display. In claim 1, And the correction circuit is configured to receive an output enable signal defining the output of the gate voltage and the gate voltage. In claim 2, The gate driver includes a first direction selector, a shift register, a first level shifter, and a first buffer connected to the first direction selector. In claim 3, The holding voltage applying unit includes a second direction selector and a latch, a second level shifter, and a second buffer connected to the second direction selector in turn. In claim 4, And the latch generates a common voltage as the sustain voltage in synchronization with a high period of a gate voltage from the correction circuit. In claim 5, A data driver configured to apply a data voltage to the data line; The data voltage and the common voltage are inverted with each other by one pixel row. Liquid crystal display. In claim 6, And the gate driver and the sustain voltage applying unit are integrated in the liquid crystal display.

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