KR20070109297A - Lcd and driving method thereof - Google Patents

Abstract

An LCD device and a driving method thereof are provided to prevent power loss in a high grayness by adjusting a supplement period of a data voltage, which is supplied to respective pixels during a scan time. An LCD(Liquid Crystal Display) device includes a liquid crystal panel(110), a timing controller(190) and a data driver(120). The liquid crystal panel includes plural pixels. The timing controller controls the divide and latch of data, and supplement of an analog data voltage. The data driver divides input digital data to plural digital data, latches the divided digital data, and supplies an analog data voltage to respective pixels during a scan time according to a grayness value of the latched digital data.

Description

Liquid crystal display and driving method thereof

1 is an equivalent circuit diagram of a pixel formed in a general liquid crystal display device.

2 is a block diagram of a conventional liquid crystal display device.

3 is a characteristic diagram of data voltage supplied to each pixel of a conventional liquid crystal display device.

4 is a block diagram of a liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram of a data driver in FIG. 4. FIG.

6 is a characteristic diagram of data voltages supplied to each pixel of the liquid crystal display according to the present invention;

Explanation of symbols on the main parts of the drawings

100 and 200: liquid crystal display 110: liquid crystal display panel

120, 220: data driver 130: gate driver

140: gamma reference voltage generator 150: backlight assembly

160: inverter 170: common voltage generator

180: gate driving voltage generator 190, 210: timing controller

221: decoder 222: data divider

223: latch portion 224: storage portion

225: data supply control unit 226: data supply unit

227: buffer section

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of supplying a data voltage to each pixel of the liquid crystal display panel by a pumping method.

A liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal, and an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell enables active control of the switching element. This is advantageous for video implementation. As the switching element used in the active matrix liquid crystal display device, a thin film transistor (hereinafter referred to as TFT) is mainly used as shown in FIG. 1.

Referring to FIG. 1, an active matrix type liquid crystal display converts digital input data into an analog data voltage based on a gamma reference voltage and supplies it to the data line DL and simultaneously supplies scan pulses to the gate line GL. The liquid crystal cell Clc is charged.

The gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and one electrode of the storage capacitor Cst. Connected.

The common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc.

The storage capacitor Cst charges a data voltage applied from the data line DL when the TFT is turned on, thereby maintaining a constant voltage of the liquid crystal cell Clc.

When the scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode so that the voltage on the data line DL is applied to the pixel electrode of the liquid crystal cell Clc. Supply. At this time, the liquid crystal molecules of the liquid crystal cell Clc modulate the incident light by changing the arrangement by the electric field between the pixel electrode and the common electrode.

A configuration of a conventional liquid crystal display device having pixels having such a structure will be described with reference to FIG. 2.

2 is a block diagram of a conventional liquid crystal display device.

Referring to FIG. 2, the liquid crystal display 100 according to the related art includes a thin film transistor for driving the liquid crystal cell Clc at the intersection of the data lines DL1 to DLm and the gate lines GL1 to GLn. TFT: a thin film transistor (110) having a thin film transistor (110), a data driver (120) for supplying data to the data lines (DL1 to DLm) of the liquid crystal display panel 110, the liquid crystal display panel 110 A gate driver 130 for supplying scan pulses to the gate lines GL1 to GLn of the gate lines, a gamma reference voltage generator 140 for generating a gamma reference voltage and supplying it to the data driver 120, and a liquid crystal display panel The backlight assembly 150 for irradiating light to the 110, the inverter 160 for applying an alternating voltage and current to the backlight assembly 160, and a common voltage Vcom are generated to generate the liquid crystal display panel 110. Common voltage generator 170 for supplying the common electrode of the liquid crystal cell Clc of Controlling the gate driver voltage generator 180, the data driver 120, and the gate driver 130 to generate and supply the gate high voltage VGH and the gate low voltage VGL to the gate driver 130. A timing controller 190 is provided.

In the liquid crystal display panel 110, liquid crystal is injected between two glass substrates. The data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal to the lower glass substrate of the liquid crystal display panel 110. TFTs are formed at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. The TFT supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scan pulse. The gate electrodes of the TFTs are connected to the gate lines GL1 to GLn, and the source electrodes of the TFTs are connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst.

The TFT is turned on in response to the scan pulse supplied to the gate terminal via the gate lines GL1 to GLn. When the TFT is turned on, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.

The data driver 120 supplies data to the data lines DL1 to DLm in response to the data driving control signal DDC supplied from the timing controller 190, and digital video data supplied from the timing controller 190. (RGB) is sampled and latched, and then converted into an analog data voltage capable of expressing gray scales in the liquid crystal cell Clc of the liquid crystal display panel 110 based on the gamma reference voltage supplied from the gamma reference voltage generator 140. Supply to the data lines DL1 to DLm.

The gate driver 130 sequentially generates scan pulses, that is, gate pulses, in response to the gate driving control signal GDC and the gate shift clock GSC supplied from the timing controller 190, thereby providing the gate lines GL1 to GLn. To feed. In this case, the gate driver 130 determines the high level voltage and the low level voltage of the scan pulse based on the gate high voltage VGH and the gate low voltage VGL supplied from the gate driving voltage generator 180.

The gamma reference voltage generator 140 receives a high potential power supply voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and output the same to the data driver 120.

The backlight assembly 150 is disposed on the rear surface of the liquid crystal display panel 110 and emits light by an AC voltage and a current supplied from the inverter 160 to irradiate light to each pixel of the liquid crystal display panel 110.

The inverter 160 converts the square wave signal generated therein into a triangular wave signal and compares the triangular wave signal with a DC power supply voltage (VCC) supplied from the system to generate a burst dimming signal proportional to the comparison result. . When a burst dimming signal determined according to an internal square wave signal is generated, a driving IC (not shown) for controlling the generation of AC voltage and current in the inverter 160 is supplied to the backlight assembly 150 according to the burst dimming signal. Control the generation of alternating voltage and current.

The common voltage generator 170 receives the high potential power voltage VDD to generate the common voltage Vcom and supplies the common voltage Vcom to the common electrodes of the liquid crystal cells Clc of each pixel of the liquid crystal display panel 110.

The gate driving voltage generator 180 receives the high potential power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL to supply the gate driver 130 to the gate driver 130. Here, the gate driving voltage generation unit 180 generates a gate high voltage VGH that is greater than or equal to the threshold voltage of the TFTs provided in each pixel of the liquid crystal display panel 110, and the gate low voltage that is less than or equal to the threshold voltage of the TFT. VGL). The gate high voltage VGH and the gate low voltage VGL generated in this way are used to determine the high level voltage and the low level voltage of the scan pulse generated by the gate driver 130, respectively.

The timing controller 190 supplies digital video data RGB, which is supplied from a digital video card (not shown), to the data driver 120, and also horizontal / vertical synchronization signals H and V according to the clock signal CLK. The data driving control signal DDC and the gate driving control signal GDC may be generated and supplied to the data driver 120 and the gate driver 130, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and a gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

In the conventional liquid crystal display having the configuration and function as described above, as shown in FIG. 3, the data driver 120 continuously supplies the data voltage to each pixel for a predetermined time and has different levels for each gray level. Since the data voltage was supplied to each pixel by using the voltage as the power supply voltage, the power loss was high in the high gradation using a very high voltage as the power supply voltage compared to the low gradation.

In the conventional liquid crystal display, a D / A converter (not shown) included in the data driver 120 is different for each gray level in order to convert the digital data voltage input from the timing controller 190 into an analog data voltage. A gamma reference voltage of a level was supplied. Since the D / A converter processes data through a predetermined circuit configuration, the level range of the gamma reference voltage that can be supplied and processed for each gray level is restricted. High Bit Color Depth was difficult to implement.

The present invention has been made to solve the above problems, and an object of the present invention is to discontinuously adjust the analog data voltage by adjusting the supply period of the data voltage supplied to each pixel of the liquid crystal display panel for one scan time. There is provided a liquid crystal display device which can be supplied and a driving method thereof.

An object of the present invention is to adjust the supply period of the data voltage supplied to each pixel of the liquid crystal display panel during one scan time, so that the data voltage of different levels can be supplied for each gray level using a constant voltage as the power supply voltage. And a driving method thereof.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of preventing power loss in high gray levels by supplying data voltages of different levels for each gray level by using a constant voltage as a power supply voltage.

Disclosure of Invention An object of the present invention is to provide a liquid crystal display device and a method of driving the same, by using a constant voltage as a power supply voltage and discontinuously supplying data voltages of different levels for each gray level for one scan time, thereby easily implementing high-bit color adapter. To provide.

The liquid crystal display device of the present invention for achieving the above object is a liquid crystal display panel formed with a plurality of pixels; A timing controller for controlling division and latching of data and controlling supply of analog data voltages; And distributing and latching the input digital data into a plurality of digital data according to the control of the timing controller, and discontinuously supplying analog data voltages to each pixel for one scan time according to the grayscale values of the latched digital data. And a data driving means for performing the same.

The data driving means includes a decoder for decoding the input digital data; A data dividing unit for dividing the digital data decoded by the decoder according to the dividing control signal from the timing controller; A latch unit for latching digital data divided by the data divider; A storage unit for storing a plurality of timing data; Pulse width modulation for supplying a data voltage based on the read timing data in synchronization with the synchronization signal from the timing controller and reading the timing data of the storage unit and the gray value of the digital data latched by the latch unit. A data supply controller for adjusting and outputting a duty ratio of a signal; And a data supply unit for supplying an analog data voltage to each pixel discontinuously during one scan time by receiving a high potential power voltage according to the duty ratio of the pulse width modulation signal.

The liquid crystal display device of the present invention comprises: a decoder for decoding input digital data; A data divider for dividing the digital data decoded by the decoder according to a divide control signal; A latch unit for latching digital data divided by the data divider; A storage unit for storing a plurality of timing data; Read the timing data of the storage unit in synchronization with the synchronization signal, and determine the duty ratio of the pulse width modulation signal for controlling the supply of the data voltage based on the read timing data according to the gray value of the digital data latched by the latch unit. A data supply controller for adjusting and outputting the data; And a data supply unit for supplying an analog data voltage to each pixel discontinuously during one scan time by receiving a high potential power voltage according to the duty ratio of the pulse width modulation signal.

The data supply controller is configured to store a lookup table in which a plurality of data voltage levels to be supplied to the pixels and duty ratios of the plurality of pulse width modulation signals correspond to one-to-one.

The data supply controller determines the level of the data voltage to be supplied to each pixel through the gray level of the latched digital data, and then, based on the timing data corresponding to the determined level of the data voltage among the read timing data. The duty ratio of the pulse width modulated signal to be supplied to each pixel for one scan time is determined by referring to the lookup table.

The data supply control unit may supply a pulse width modulation signal having the determined duty ratio to the data supply unit.

The data supply unit may include N-MOS transistors having a gate connected in a one-to-one correspondence to the pulse width modulation signal output terminals of the data supply controller, a drain to which the high potential power voltage is applied, and a source connected to the liquid crystal display panel. Include.

The N-MOS transistors may be turned on / off by the pulse width modulation signal applied to a gate to discontinuously switch the high potential power voltage applied to the drain to supply an analog data voltage to the liquid crystal display panel. .

A driving method of a liquid crystal display device of the present invention includes: decoding input digital data; Dividing the decoded digital data according to a division control signal; Latching the divided digital data; Adjusting a duty ratio of a pulse width modulation signal for supplying a data voltage based on predetermined timing data according to gray level values of the latched digital data; And supplying an analog data voltage to each pixel discontinuously during one scan time by receiving a high potential power voltage according to the duty ratio of the pulse width modulation signal. Here, the present invention determines the level of the data voltage to be supplied to each pixel through the gray value of the latched digital data, and then, based on the timing data suitable for the determined level of the data voltage among the predetermined timing data The duty ratio of the pulse width modulated signal to be supplied to each pixel during one scan time is determined by referring to the lookup table of the.

On the other hand, one scan time is a supply period of the scan pulse supplied to one gate line.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

4 is a configuration diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 4, in the liquid crystal display device 200 of the present invention, as in FIG. 2, the liquid crystal display panel 110, the gate driver 130, the backlight assembly 150, the inverter 160, and the common voltage are generated. The unit 170 is provided.

The liquid crystal display device 200 according to the present invention includes a timing controller 210 for controlling data division and latching and controlling supply of an analog data voltage, and digital data input under control of the timing controller 210. And a data driver 220 for dividing and latching the digital data into a plurality of digital data and supplying an analog data voltage to each pixel in accordance with the gray value of the latched digital data.

The timing controller 210 supplies digital video data RGB, which is supplied from a digital video card (not shown), to the data driver 220, and also horizontal / vertical synchronization signals H and V according to the clock signal CLK. The data driving control signal DDC and the gate driving control signal GDC are generated using the same and supplied to the data driver 220 and the gate driver 130, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and the gate driving control signal GDC. ) Includes a gate start pulse (GSP) and a gate output enable (GOE).

In addition, the timing controller 210 controls the data division by supplying the division control signals DCS1 to DCSm to the data driver 220, and supplies a synchronization signal Sync to the data driver 220 to supply analog data voltages. To control the supply.

When digital data is input from the timing controller 210, the data driver 220 decodes the input digital data, and then decodes the decoded digital data according to the division control signals DCS1 to DCSm, where m (m is a natural number of 2 or more). It divides and latches into) digital data, and converts divided m digital data into m analog data.

Then, the data driver 220 synchronizes the data supply by the synchronization signal Sync from the timing controller 210 and then applies the high potential power voltage VDD according to the grayscale values of the m latched digital data. When applied, the analog data voltage is discontinuously supplied to each pixel for one scan time based on predetermined timing data. Here, the data driver 220 buffers the generated analog data voltages and supplies them to the data lines DL1 to DLm.

A data driver 220 having such a function will be described in more detail with reference to FIG. 6.

6 is a circuit diagram of a data driver included in the driving device of the liquid crystal display according to the exemplary embodiment of the present invention.

Referring to FIG. 6, the data driver 220 may include a decoder 221 for decoding input digital data and digital data decoded according to the division control signals DCS1 to DCSm, where m is m or more. A data divider 222 for dividing the divided digital data, a latch unit 223 for latching the divided m digital data, a storage unit 224 for storing a plurality of timing data, Timing data read in accordance with the gray value of the m digital data latched by the latch unit 223 and read timing data of the storage unit 224 in synchronization with the synchronization signal Sync from the timing controller 210. The duty ratio of the pulse width modulation signal PWM from the data supply control unit 225 and the data supply control unit 225 for adjusting and outputting the duty ratio of the pulse width modulation signal PWM for controlling the supply of the data voltages. on Accordingly, data is supplied by buffering the analog data voltage generated from the data supply unit 226 and the data supply unit 226 for supplying the analog data voltage to each pixel discontinuously during a scan time by receiving the high potential power voltage VDD. A buffer unit 227 for supplying the lines DL1 to DLm is provided.

The decoder 221 deconforms the digital data input from the timing controller 210 to make a signal system suitable for the D / A converter 224. When the six digital data are input from the timing controller 210, the decoder 221 selects only one digital data among the 64 digital data in which the six digital data are combined and outputs the digital data to the data divider 222. .

The data divider 222 may include a gate connected to an output terminal of the divided control signals DCS1 to DCSm of the timing controller 210, a source connected to an output terminal of the decoder 221, and a drain of the latch unit 223. M P-MOS transistors PM1-1 to PM1-m respectively connected to the plurality of transistors. Here, the PMOS transistors PM1-1 to PM1-m are sequentially driven by the division control signals DCS1 to DCSm to switch the digital data applied to the source to the latch unit 223 connected to the drain. . That is, the divided control signals DCS1 to DCSm are supplied to gates of the PMOS transistors PM1-1 to PM1-m corresponding to one-to-one, respectively.

For example, when the timing controller 210 turns on the P-MOS transistor PM1-1 by first supplying the low level division control signal DCS1 to the gate of the first P-MOS transistor PM1-1, the P-MOS is turned on. The transistor PM1-1 switches the digital data applied to the source and supplies it to the latch unit 223 connected to the drain, and the timing controller 210 finally supplies the low level division control signal DCSm to the last. When the P-MOS transistors PM1-m are turned on by supplying them to the gates of the P-MOS transistors PM1-m, the P-MOS transistors PM1-m switch the digital data applied to the source to connect the latch unit 223 connected to the drain. ). As such, the timing controller 210 sequentially supplies the low-level division control signals DCS1 to DCSm, but sequentially from the first PMOS transistor PM1-1 to the last PMOS transistor PM1-m. As a result, the PMOS transistors PM1-1 to PM1-m are sequentially driven. Accordingly, the P-MOS transistors PM1-1 to PM1-m sequentially switch one decoded data and supply it to the latch unit 223. As a result, one data output from the decoder 221 is divided into m digital data by being sequentially switched by the PMOS transistors PM1-1 through PM1-m.

The latch unit 223 includes a switching unit 223-1 for simultaneously switching m digital data divided according to the division control signal DCSm, and m digital data switched through the switching unit 223-1. The D / A converter 224 by secondly inverting the level of the m digital data inverted by the first inverting unit 223-2 and the first inverting unit 223-2. A second inverting portion (223-3) for supplying to the.

The switching unit 223-1 has a gate connected in common to an output terminal of the division control signal DCSm of the timing controller 210, and a source of the PMOS transistors PM1-1 to PM1- of the data division unit 222. P-MOS transistors PM2-1 to PM2-m connected to the drains of m) in one-to-one correspondence, respectively, and having drains connected one-to-one to the m input terminals of the first inverting unit 223-2. It is provided.

Since the low level division control signal DCSm output from the timing controller 210 is simultaneously applied to the gates of the PMOS transistors PM2-1 to PM2-m, the PMOS transistors PM2-1 to PM2- are applied to the gates of the PMOS transistors PM2-1 to PM2-m. m) is simultaneously turned on and simultaneously supplies m digital data divided by the data divider 222 to the first inverter 223-2. Here, the sources of the P-MOS transistors PM2-1 to PM2-m are connected to the drains of the P-MOS transistors PM1-1 to PM1-m in a one-to-one correspondence, so that the P-MOS transistors PM2- are connected. 1) switches the digital data divided by the P-MOS transistor PM1-1 to the first inverting unit 223-2, and the P-MOS transistor PM2-2 is switched by the P-MOS transistor PM1-2. The divided digital data is switched to the first inverting unit 223-2, and the P-MOS transistor PM2-3 converts the digital data divided by the P-MOS transistor PM1-3 into the first inverting unit 223-2. ), The P-MOS transistor PM2-4 switches the digital data divided by the P-MOS transistor PM1-4 to the first inverting unit 223-2, and the P-MOS transistor PM2-5. Switches the digital data divided by the P-MOS transistor PM1-5 to the first inverting unit 223-2, and the P-MOS transistor PM2-m is P. The digital data divided by the MOS transistors PM1-m is switched to the first inverting unit 223-2. As such, the other PMOS transistors PM2-6 to PM2- (m-1) also correspond to their source in one-to-one correspondence with their respective PMOS transistors PM1-6 to PM1- (m-1). ) And the digital data divided by the second switch to the first inverting unit (223-2).

At this time, the timing controller 210 transmits the low level division control signal DCSm to the gate of the last PMOS transistor PM1-m of the data divider 222 and the PMOS transistors of the switching unit 223-1. Since it is simultaneously supplied to the gates of PM2-1 to PM2-m, the last PMOS transistor PM1-m of the data divider 222 and the PMOS transistors PM2-1 of the switching unit 223-1. To PM2-m) are turned on at the same time. That is, the division of the m digital data is completed by the data divider 222 and the P-MOS transistors PM2-1 to PM2-m of the switching unit 223 are turned on to divide the m digital data. At the same time, it is switched to the first inverting unit 223-2.

The first inverting unit 223-2 has an input terminal connected in a one-to-one correspondence with drains of the PMOS transistors PM2-1 to PM2-m of the switching unit 223-1, and the output terminal is connected to the second inverting unit 223. M inverters IV1-1 to IN1-m connected in one-to-one correspondence with m input terminals of -3).

Since the input terminals of the m inverters IV1-1 to IN1-m are connected in one-to-one correspondence with the drains of the PMOS transistors PM2-1 to PM2-m, respectively, the inverter IV1-1 is connected to the PMOS. The level of the digital data switched by the transistor PM2-1 is inverted, the inverter IV1-2 inverts the level of the digital data switched by the PMOS transistor PM2-2, and the inverter IV1-3. ) Inverts the level of digital data switched by P-MOS transistor PM2-3, inverter IV1-4 inverts the level of digital data switched by P-MOS transistor PM2-4, and inverter IV1-5 inverts the level of digital data switched by PMOS transistor PM2-5, and inverter IV1-m is the level of digital data switched by PMOS transistor PM2-m. Invert As described above, the other inverters IV1-6 to IN1-(m-1) also correspond to their input terminals in a one-to-one correspondence to PMOS transistors PM2-6 to PM2- (m-1) to which drains are connected. Inverts the level of the switched digital data.

The second inverting unit 223-3 has an input terminal connected in one-to-one correspondence with output terminals of the inverters IV1-1 to IN1-m of the first inverting unit 223-2, and the output terminal is connected to the D / A converter 224. M inverters IV2-1 to IN2-m connected thereto.

The input terminals of the m inverters IV2-1 to IN2-m are connected in one-to-one correspondence with the output terminals of the inverters IV1-1 to IN1-m of the first inverting unit 223-2. The inverter IV2-1 of the inverting unit 223-3 inverts the level of the digital data inverted again by the inverter IV1-1 of the first inverting unit 223-2, and then inverts the second inverting unit 223. The inverter IV2-2 of -3 again inverts the level of the digital data inverted by the inverter IV1-2 of the first inverting unit 223-2, and then inverts the level of the second inverting unit 223-3. Inverter IV2-3 inverts the level of digital data inverted by inverter IV1-3 of first inverting unit 223-2 again, and inverter IV2- of second inverting unit 223-3. 4 again inverts the level of the digital data inverted by the inverter IV1-4 of the first inverting unit 223-2, and the inverter IV2-5 of the second inverting unit 223-3 is made inverted. 1 Reset the level of digital data inverted by the inverter IV1-5 of the inverting unit 223-2. An inverter (IV2-m) of all sikimyeo, and the second half in (223-3) is then re-inverting the level of the first inverted by an inverter (IV1-m) of the inverted portion (223-2), the digital data. In this way, the other inverters IV2-6 to IN2- (m-1) also correspond one-to-one with their input terminals, and are inverted by the inverters IV1-6 to IN1- (m-1) to which the output terminals are connected. The level of the digital data is reversed again.

The storage unit 224 is implemented with a memory device such as EEPROM to store timing data. These timing data serve as a reference for adjusting the duty ratio of the pulse width modulated signal that is changed according to the gray scale value of the data.

When the synchronization signal Sync is input from the timing controller 210, the data supply controller 225 synchronizes to supply an analog data voltage, and simultaneously reads timing data of the storage unit 224. In this state, when the digital data latched from the latch unit 223 is input, the data supply control unit 225 determines the level of the data voltage to be supplied to each pixel through the gray value of the digital data, and then reads the timing data. The duty ratio of the pulse width modulated signal to be supplied to each pixel during one scan time is determined by referring to a predetermined lookup table based on the timing data corresponding to the level of the data voltage determined. When the duty ratio of the pulse width modulated signal is determined as described above, the data supply controller 225 supplies the determined pulse width modulated signal of the duty ratio to the data supply unit 226.

Here, a plurality of data voltage levels to be supplied to the pixels of the liquid crystal display panel 110 and duty ratios of the plurality of pulse width modulation signals are set in a predetermined lookup table in one-to-one correspondence. The predetermined lookup table is implemented to be stored in the data supply controller 225, but is not limited thereto and may be implemented to be stored in the storage 224.

The data supply unit 226 has a gate connected in a one-to-one correspondence to the pulse width modulation signal output terminals of the data supply control unit 225, a drain to which a high potential power voltage is applied, and a source connected to the buffer unit 227. The MOS transistors NM1-1 to NM1-m are provided.

The N-MOS transistors NM1-1 through NM1-m are turned on / off by a pulse width modulated signal applied to a gate, and the on / off period is adjusted according to the duty of the pulse width modulated signal. The N-MOS transistors NM1-1 to NM1-m are turned on when a high level pulse width modulation signal is applied to the gate to switch the high potential power voltage VDD applied to the drain to convert the analog data voltage. When the pulse width modulation signal of low level is applied to the gate, the signal is turned off to stop the supply of the analog data voltage. Since the on / off periods of the N-MOS transistors NM1-1 to NM1-m are adjusted according to the duty ratio of the pulse width modulated signal, as shown in FIG. Supplied discontinuously.

As described above, the present invention discontinuously supplies data voltages of different levels for each gray level by using a constant high potential power supply voltage VDD as a power supply voltage, thereby preventing power loss in high gray levels and facilitating high bit color adapters. Can be implemented. Here, the meaning of facilitating the implementation of the high bit color adapter is that the number of colors to be displayed can be increased.

The buffer unit 227 includes buffers having an input terminal connected in one-to-one correspondence to the sources of the NMOS transistors NM1-1 through NM1-m and an output terminal connected in a one-to-one correspondence with the data lines DL1 through DLm. (BF1 to BFn).

The buffers BF1 to BFn buffer the analog data voltages supplied from the NMOS transistors corresponding to their input terminals among the NMOS transistors NM1-1 to NM1-m to buffer the data lines DL1 to DLm. ) To the data line connected to its output terminal.

As described above, the present invention uses a constant voltage as a power supply voltage by adjusting a supply period of a data voltage supplied to each pixel of a liquid crystal display panel for one scan time to discontinuously use data voltages of different levels for each gray level. This prevents power loss at high gradations and facilitates high-bit color adapters.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (17)

A liquid crystal display panel in which a plurality of pixels are formed; A timing controller for controlling division and latching of data and controlling supply of analog data voltages; And According to the control of the timing controller, the input digital data is divided into a plurality of digital data and latched, and the analog data voltage is discontinuously supplied to each pixel for one scan time according to the gray value of the latched digital data. Data driving means Liquid crystal display comprising a. The method of claim 1, The data driving means, A decoder for decoding the input digital data; A data dividing unit for dividing the digital data decoded by the decoder according to the dividing control signal from the timing controller; A latch unit for latching digital data divided by the data divider; A storage unit for storing a plurality of timing data; The pulse width for controlling the supply of the data voltage based on the read timing data in synchronization with the synchronization signal from the timing controller and reading the timing data of the storage unit and the gray value of the digital data latched by the latch unit. A data supply controller for adjusting and outputting a duty ratio of the modulated signal; And Data supply unit for supplying analog data voltage to each pixel discontinuously for one scan time by receiving a high potential power voltage according to the duty ratio of the pulse width modulation signal Liquid crystal display comprising a. The method of claim 2, And the data supply controller receives the synchronization signal from the timing controller. The method of claim 2, And the data supply controller stores a look-up table in which a plurality of data voltage levels to be supplied to pixels of the liquid crystal display panel and duty ratios of a plurality of pulse width modulation signals correspond to one-to-one. The method of claim 4, wherein The data supply controller determines the level of the data voltage to be supplied to each pixel through the gray level of the latched digital data, and then, based on the timing data corresponding to the determined level of the data voltage among the read timing data. And a duty ratio of a pulse width modulated signal to be supplied to each pixel during one scan time with reference to the lookup table. The method of claim 5, And the data supply controller supplies the pulse width modulation signal of the determined duty ratio to the data supply unit. The method of claim 2, The data supply unit, N-MOS transistors having a gate connected in a one-to-one correspondence to pulse width modulation signal output terminals of the data supply controller, a drain to which the high potential power voltage is applied, and a source connected to the liquid crystal display panel. Liquid crystal display comprising a. The method of claim 7, wherein The N-MOS transistors are turned on / off by the pulse width modulation signal applied to a gate to discontinuously switch the high potential power voltage applied to the drain to supply an analog data voltage to the liquid crystal display panel. LCD display device. A decoder for decoding the input digital data; A data divider for dividing the digital data decoded by the decoder according to a divide control signal; A latch unit for latching digital data divided by the data divider; A storage unit for storing a plurality of timing data; Read the timing data of the storage unit in synchronization with the synchronization signal, and determine the duty ratio of the pulse width modulation signal for controlling the supply of the data voltage based on the read timing data according to the gray value of the digital data latched by the latch unit. A data supply controller for adjusting and outputting the data; And Data supply unit for supplying analog data voltage to each pixel discontinuously for one scan time by receiving a high potential power voltage according to the duty ratio of the pulse width modulation signal Liquid crystal display comprising a. The method of claim 9, And the data supply controller stores a lookup table in which the duty cycles of the plurality of data voltage levels to be supplied to the pixels and the duty ratios of the plurality of pulse width modulation signals correspond one to one. The method of claim 10, The data supply controller determines the level of the data voltage to be supplied to each pixel through the gray level of the latched digital data, and then, based on the timing data corresponding to the determined level of the data voltage among the read timing data. And a duty ratio of a pulse width modulated signal to be supplied to each pixel during one scan time with reference to a lookup table. The method of claim 11, And the data supply controller supplies the pulse width modulation signal of the determined duty ratio to the data supply unit. The method of claim 9, The data supply unit, N-MOS transistors having a gate connected in a one-to-one correspondence to pulse width modulation signal output terminals of the data supply controller, a drain to which the high potential power voltage is applied, and a source connected to the liquid crystal display panel. Liquid crystal display comprising a. The method of claim 13, The N-MOS transistors are turned on / off by the pulse width modulation signal applied to a gate to discontinuously switch the high potential power voltage applied to the drain to supply an analog data voltage to the liquid crystal display panel. LCD display device. Decoding the input digital data; Dividing the decoded digital data according to a division control signal; Latching the divided digital data; Adjusting a duty ratio of a pulse width modulation signal for supplying a data voltage based on predetermined timing data according to gray level values of the latched digital data; And Supplying an analog data voltage to each pixel discontinuously during a scan time by receiving a high potential power voltage according to the duty ratio of the pulse width modulation signal; Method of driving a liquid crystal display comprising a. The method of claim 15, In the duty ratio adjusting step, after determining the level of the data voltage to be supplied to each pixel through the gray level of the latched digital data, the timing data corresponding to the determined level of the data voltage among the predetermined timing data is referred to. And a duty ratio of a pulse width modulated signal to be supplied to each pixel for one scan time by referring to a predetermined lookup table. The method of claim 16, And a plurality of data voltage levels to be supplied to the pixels and duty ratios of the plurality of pulse width modulation signals in the predetermined lookup table in one-to-one correspondence.

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