KR20080078361A - Lcd and drive method thereof - Google Patents

Abstract

An LCD device and a driving method thereof are provided to reduce an area of a data driver by decoding digital data latched in the data driver based on a predetermined bit unit. An LCD(Liquid Crystal Display) device includes a timing controller(180), a gamma reference voltage generator(140), and a data driver(120). The timing controller controls gray scales of I-bit digital data inputted from a system. The gamma reference voltage generator generates a gamma reference voltage. The data driver separates first and second data from the inputted I-bit digital data, decodes independently the first and second data, and outputs analog data voltages by simultaneously switching the analog data voltage according to the first and second data using plural first to m D/A(Digital to Analog) converters.

Description

Liquid crystal display and driving method thereof

1 is an equivalent circuit diagram of each pixel formed in a general liquid crystal display device.

2 is a block diagram of a liquid crystal display device according to an exemplary embodiment of the present invention.

3 is a block diagram of a data driving circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: liquid crystal display device 110: liquid crystal display panel

120: data driving circuit 130: gate driving circuit

140: gamma reference voltage generator 150: backlight assembly

160: inverter 170: common voltage generator

180: timing controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of using a low voltage decoder occupying a small area by decoding and decoding digital data latched in a data driving circuit by a predetermined bit unit.

A liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal, and an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell enables active control of the switching element. This is advantageous for video implementation. As the switching element used in the active matrix type liquid crystal display device, a thin film transistor (TFT) is mainly used as shown in FIG. 1.

Referring to FIG. 1, an active matrix type liquid crystal display converts digital input data into an analog data voltage based on a gamma reference voltage and supplies it to the data line DL and simultaneously supplies scan pulses to the gate line GL. The liquid crystal cell CLc is charged.

The gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell CLc and one electrode of the storage capacitor Cst. Connected.

The common voltage Vcom is supplied to the common electrode of the liquid crystal cell CLc.

The storage capacitor Cst charges a data voltage applied from the data line DL when the TFT is turned on to maintain a constant voltage of the liquid crystal cell CLc.

When the scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode so that the voltage on the data line DL is applied to the pixel electrode of the liquid crystal cell CLc. Supply. At this time, the liquid crystal molecules of the liquid crystal cell CLc modulate the incident light by changing the arrangement by the electric field between the pixel electrode and the common electrode.

A data driving circuit of a conventional liquid crystal display device having pixels having such a structure latches the input low voltage digital data and then level shifts the latched digital data to a high voltage. The data driving circuit decodes the level shifted high voltage digital data into an analog data voltage, wherein the data driving circuit decodes the level shifted high voltage digital data using high voltage decoders occupying a large area.

As described above, the conventional liquid crystal display device has a problem in that the area of the data driving circuit is increased by providing high voltage decoders having a large area in the data driving circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device and a method of driving the same, which can decode and decode digital data latched in a data unit by a predetermined bit unit. There is.

Another object of the present invention is to provide a liquid crystal display device and a method of driving the same, which can use a low voltage decoder that occupies a small area by separating and decoding digital data latched in a data driving circuit by a predetermined bit unit.

It is another object of the present invention to provide a liquid crystal display device and a driving method thereof which can reduce the area of a data driving circuit by using a low voltage decoder occupying a small area in the data driving circuit.

The liquid crystal display device of the present invention for achieving the above object comprises a timing controller for controlling the gradation of the l-bit (l is a natural number of two or more) digital data input from the system; A gamma reference voltage generator for generating a gamma reference voltage; And separating the input l-bit digital data into "lk bit first data" and k-bit second data (k is a natural number), decoding the first and second data separately, and decoding the decoded first and second data. And a data driving circuit which simultaneously outputs an analog data voltage by simultaneously switching the gamma reference voltage according to the data.

A data driving circuit of a liquid crystal display according to the present invention comprises: a latch unit for latching input l-bit digital data (l is a natural number of two or more); A plurality of bus lines configured to separate the latched l-bit digital data into " l-k bit first data " and k bit second data (k being a natural number); Simultaneously decode the first and second data separated and input separately through a bus line connected to one of the plurality of bus lines, and simultaneously switch the input gamma reference voltage according to the decoded first and second data. And first to m-th D / A converters to output analog data voltages.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method comprising: latching an inputted l bit (l is 2 or more natural numbers) digital data; Separating the latched l-bit digital data into " l-k bit first data " and k bit second data (k being a natural number);

Decoding the first and second data separately; And switching the gamma reference voltage according to the decoded first and second data to output an analog data voltage.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 2, in the liquid crystal display device 100 according to an exemplary embodiment, a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn cross each other to correspond to each other. Supplying data to the liquid crystal display panel 110 having a thin film transistor (TFT) for driving the liquid crystal cell CLc and the data lines DL1 to DLm of the liquid crystal display panel 110. A data driving circuit 120 for supplying the gate driving circuit 130 to supply scan pulses to the gate lines GL1 to GLn of the liquid crystal display panel 110, and a gamma reference voltage to generate the data driving circuit 120. A gamma reference voltage generator 140 for supplying the light source, a backlight assembly 150 for irradiating light to the liquid crystal display panel 110, and an inverter for applying an alternating voltage and current to the backlight assembly 150. 160 and a common voltage Vcom to generate liquid of the liquid crystal display panel 110. And a timing controller 180 for controlling the common voltage generating unit 170, and a data drive circuit 130 to 120 and the gate obtain donghoe for supplying to the common electrode of the cells (CLc). Where m and n are natural numbers.

In the liquid crystal display panel 110, liquid crystal is injected between two glass substrates. The data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal to the lower glass substrate of the liquid crystal display panel 110. TFTs are formed at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. The TFT supplies the data on the data lines DL1 to DLm to the liquid crystal cell CLc in response to the scan pulse. The gate electrode of the TFT is connected to the gate lines GL1 to GLn, and the source electrode of the TFT is connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell CLc and the storage capacitor Cst.

The TFT is turned on in response to a scan pulse supplied to the gate terminal via the gate line connected to its gate terminal among the gate lines GL1 to GLn. Video data on the data line connected to the drain terminal of the TFT among the data lines DL1 to DLm at the turn-on of the TFT is supplied to the pixel electrode of the liquid crystal cell CLc.

The data driving circuit 120 supplies data to the data lines DL1 to DLm in response to the data driving control signal DDC supplied from the timing controller 180, and digital video supplied from the timing controller 180. After sampling and latching data (such as RGB data or RGBW data), the liquid crystal cell CLc of the liquid crystal display panel 110 based on the gamma reference voltages GMA1 to GMAi supplied from the gamma reference voltage generator 140. Is converted into an analog data voltage capable of expressing gray scale and supplied to the data lines DL1 to DLm.

In particular, the data driver circuit 120 decodes the latched digital data by a predetermined bit unit to perform decoding twice.

The gate driving circuit 130 sequentially generates scan pulses in response to the gate driving control signal GDC and the gate shift clock GSC supplied from the timing controller 180 to supply the gate lines GL1 to GLn. . In this case, the gate driving circuit 130 determines the high level voltage and the low level voltage of the scan pulse according to the gate high voltage VGH and the gate low voltage VGL supplied from the gate driving voltage generator (not shown). .

The gamma reference voltage generator 140 receives the high potential power voltage VDD to generate the gamma reference voltages GMA1 to GMAi and outputs them to the data driving circuit 120. I is a natural number of two or more.

The backlight assembly 150 is disposed on the rear surface of the liquid crystal display panel 110 and emits light by an AC voltage and a current supplied from the inverter 160 to irradiate light to each pixel of the liquid crystal display panel 110.

The inverter 160 converts the square wave signal generated therein into a triangular wave signal and compares the triangular wave signal with a DC power supply voltage (VCC) supplied from the system to generate a burst dimming signal proportional to the comparison result. . When a burst dimming signal determined according to an internal square wave signal is generated, a driving IC (not shown) for controlling the generation of AC voltage and current in the inverter 160 is supplied to the backlight assembly 150 according to the burst dimming signal. Control the generation of alternating voltage and current.

The common voltage generator 170 receives the high potential power voltage VDD to generate the common voltage Vcom and supplies the common voltage Vcom to the common electrodes of the liquid crystal cells CLc included in each pixel of the liquid crystal display panel 110.

The timing controller 180 supplies the digital video data RGB supplied from the system to the data driving circuit 120 and uses the horizontal / vertical synchronization signals H and V according to the system clock signal SCLK. The driving control signal DDC and the gate driving control signal GDC are generated and supplied to the data driving circuit 120 and the gate driving circuit 130, respectively. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and a gate driving control signal GDC. ) Includes a gate shift clock (GSC), a gate start pulse (GSP), a gate output enable (GOE), and the like.

3 is a configuration diagram of a data driving circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the data driving circuit 120 according to the present invention includes a control unit 121 for converting digital data serially input from the timing controller 180 in parallel, and a sampling signal used for latching data. The shift register 122 generated, the latch unit 123 for latching digital data input in parallel from the controller 121 according to the sampling signal, and a resistor string for dividing the gamma reference voltages GMA1 to GMAi ( 124 and first to m-th D / A converters 125 for converting the digital data latched by the latch unit 123 into analog data voltages using the gamma reference voltage divided by the resistor string 124. -An output buffer for buffering the analog data voltage converted by -1 to 125-m and the first to m-th D / A converters 125-1 to 125-m to the data lines DL1 to DLm. 126 is provided.

The controller 121 converts the digital data (RGB data, RGBW data, etc.) serially input from the timing controller 180 in parallel for one horizontal period and outputs them in parallel to the latch unit 123.

The shift register 122 shifts the source start pulse SSP from the timing controller 180 according to the source shift clock signal SSC from the timing controller 180 to generate a sampling signal used to latch digital data. Supply to the latch unit 123.

The latch unit 123 latches digital data input in parallel from the control unit 121 according to the sampling signal from the shift register 122 and outputs the digital data to the D / A converter 124.

The resistor string 124 is composed of a plurality of resistors R1 to Rj (j is a natural number of two or more) connected in series. The gamma reference voltages GMA1 to GMAi supplied from the gamma reference voltage generation unit 140 are divided by the resistors R1 to Rj of the resistor string 124 to be first to m-th D / A converters 125-. 1 to 125-m). In addition, the resistors provided in the resistor string 124 are not necessarily implemented in a series structure but may be implemented in a parallel structure.

The first to m th D / A converters 125-1 to 125-m convert the digital data latched through the latch unit 124 using the gamma reference voltage divided by the resistor string 124 to the analog data voltage. Is converted to the output buffer 126. These first to m-th D / A converters 125-1 to 125-m have the same circuit configuration and function, and are examples of the first, second and m-th D / A converters 125-1 and 125-m. 2, 125-m).

The first D / A converter 125-1 shifts the level (k is a natural number) of " lk bit " digital data input from the latch unit 123 via an l-bit bus line (l is a natural number of two or more). A first-first level shifter 125-1a for decoding, a first-first decoder 125-1b for decoding digital data shifted by the first-first level shifter 125-1a, and a first- From the first-first switch 125-1c for switching the gamma reference voltage turned on by the data decoded by the first decoder 125-1b and divided by the resistor string 123, and from the latch unit 123. First-decoder decoder 125-1d for decoding " k-bit " digital data separated and input through an l-bit busline, and k-bit digital data decoded by the 1-2th decoder 125-1d. The resistance string is turned on by the first and second level shifters 125-1e for shifting the level of the signal and the k-bit data shifted through the first and second level shifters 125-1e. And a second switch 125-1f for switching the gamma reference voltage divided by 123.

The second D / A converter 125-2 is a second-first level shifter 125-2a for shifting the level of the "lk bit" digital data input from the latch unit 123 via the l-bit busline. And a 2-1 decoder 125-2b for decoding the digital data shifted by the 2-1 level shifter 125-2a, and data decoded by the 2-1 decoder 125-2b. Is switched on by the second-first switch 125-2c for switching the gamma reference voltage divided by the resistor string 123, and is separated from the latch unit 123 through the l-bit bus line and input "k". 2-2 decoder 125-2d for decoding bit " digital data and 2-2 level shifter for shifting the level of k-bit digital data decoded by the 2-2 decoder 125-2d. Gamma reference field divided by the resistor string 123 by turning on by 125-bit and k-bit data shifted through the second-second level shifter 125-2e. A and a second-second switch (125-2f) for switching.

The m-th D / A converter 125-m is the m-th for shifting the level of "lk bit" digital data input from the latch unit 123 via the l-bit bus line (l is a natural number of 2 or more). An m-1 decoder 125-mb for decoding the level shifter 125-ma, the digital data shifted by the m-1 th level shifter 125-ma, and an m-1 decoder 125-ma. m-th switch 125-mc for switching the gamma reference voltage turned on by the data decoded by mb and divided by the resistor string 123, and the l-bit bus line from the latch unit 123. Shifting the level of the m-th decoder 125-md for decoding " k-bit " digital data separated and input through the " k-bit " digital data decoded by the m-th decoder 125-md. Is turned on by the m-2 level shifter 125-me and the k-bit data shifted through the m-2 level shifter 125-me, and is then turned on by the resistor string 123. And an m-th switch 125-mf for switching the divided gamma reference voltage.

Here, the first to m th D / A converters 125-1 to 125-m are connected to the latch unit 123 through an l-bit bus line connected correspondingly thereto.

All decoders included in the first to m-th D / A converters 125-1 to 125-m are low voltage decoders having a significantly smaller area than high voltage decoders.

As described above, since the first to m-th D / A converters 125-1 to 125-m having the same circuit configuration have the same function, the operation of the first D / A converter 125-1 will be described as an example. do.

When the latch unit 123 outputs the latched l-bit digital data through the bus line connected with the first D / A converter 125-1, the l-bit digital data is separated by hardware and set by the bus line. They are separated and input to the first-first level shifter 125-1a and the first-second decoder 125-1d. At this time, the separated k-bit data among the l-bit digital data is input to the 1-2 decoder 125-1d, and the remaining "l-k bit data" is input to the 1-1 level shifter 125-1a.

When the 1-1th level shifter 125-1a level shifts the input "lk bit data" and outputs it to the 1-1 decoder 125-1b, the 1-1 decoder 125-1b level shifts. The decoded "lk bit data" is decoded and outputted to the first-first switch 125-1c. At this time, the first-first switch 125-1c is turned on by the decoded “l-k bit data” to switch the gamma reference voltage divided by the resistor string 124 to the output buffer 126.

At the same time, the 1-2 decoder 125-1d decodes the input k-bit data and outputs the decoded k-bit data to the 1-2 level shifter 125-1e. The decoded k-bit data is level-shifted and output to the 1-2 switch 125-1f. In this case, the 1-2 switches 125-1f turn on the 1-2 level shifter 125-1e by the shifted k-bit data to output the gamma reference voltage divided by the resistor string 124 to the output buffer ( 126). The voltage switched through the first-first switch 125-1c and the first-second switch 125-1f is an analog data voltage supplied to the liquid crystal display panel 110.

The separated and switched data voltage is simultaneously applied to the output buffer 126 through a bus line connected between the first D / A converter 125-1 and the output buffer 126.

The output buffer 126 buffers the analog data voltages converted by the first to m-th D / A converters 125-1 to 125-m and supplies them to the data lines DL1 to DLm.

As described above, the present invention is characterized by using a low voltage decoder that occupies a small area without using a high voltage decoder having a large area by decoding the latched digital data by a predetermined bit unit. In particular, since the area of the high voltage decoder is larger than the total area occupied by the low voltage decoder, the level shifter and the switch, the first to m-th D / A converters 125-1 to 125-m are provided with two low voltage decoders. Although further provided with a level shifter and a switch in addition, the present invention substantially reduces the area of the data driving circuit compared to the prior art using a high voltage decoder.

As described above, the present invention uses a low voltage decoder that occupies a small area by separating and decoding digital data latched in the data driving circuit by a predetermined bit unit, thereby reducing the area of the data driving circuit. .

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (11)

A timing controller which controls the gradation implementation of l bits (l is a natural number of two or more) digital data input from the system; A gamma reference voltage generator for generating a gamma reference voltage; And Separate the input l-bit digital data into "lk bit first data" and k-bit second data (k is a natural number), decode the first and second data separately, and decode the first and second decoded data. Data driving circuit for outputting analog data voltage by simultaneously switching the gamma reference voltage according to data Liquid crystal display comprising a. The method of claim 1, And the data driver circuit decodes the first data by a low voltage first decoder after level shifting the first data. The method of claim 2, And the data driving circuit decodes the second data with a low voltage second decoder and then level shifts the second data. The method according to any one of claims 1 to 3, And the data driving circuit simultaneously switches the gamma reference voltage according to the decoded first and second data. A latch unit for latching input l-bit digital data (l is a natural number of two or more); A plurality of bus lines configured to separate the latched l-bit digital data into " l-k bit first data " and k bit second data (k being a natural number); Simultaneously decode the first and second data separated and input separately through a bus line connected to one of the plurality of bus lines, and simultaneously switch the input gamma reference voltage according to the decoded first and second data. To m-th D / A converters to output analog data voltages Data driving circuit of the liquid crystal display device comprising a. The method of claim 5, wherein The first to m-th D / A converter, respectively, A first level shifter for shifting the level of the first data; A first decoder for decoding the first data shifted by the first level shifter; A first switch turned on by the first data decoded through the first decoder to switch the input gamma reference voltage; A second decoder for decoding the second data; A second level shifter for shifting the level of second data decoded by the second decoder; And A second switch turned on by the second data shifted through the second level shifter to switch the input gamma reference voltage Data driving circuit of the liquid crystal display device comprising a. The method of claim 6, And the first and second decoders are low voltage decoders having a smaller area than the high voltage decoders. Latching inputted l bits (l is a natural number of two or more); Separating the latched l-bit digital data into " l-k bit first data " and k bit second data (k being a natural number); Decoding the first and second data separately; And Switching the gamma reference voltage according to the decoded first and second data to output an analog data voltage Method of driving a liquid crystal display comprising a. The method of claim 8, In the decoding step, And first level shifting the latched first data and then decoding the latched first data using a low voltage first decoder. The method of claim 9, In the decoding step, And decoding the latched second data by a low voltage second decoder to level shift the second latched data. The method according to any one of claims 8 to 10, In the output step, And simultaneously switching the gamma reference voltages according to the decoded first and second data.

Images