KR20070087995A - Method for forming silver layer and method for fabricating display substrate using the method - Google Patents

Abstract

A method for forming an Ag layer and a method for manufacturing a display substrate using the same are provided to reduce signal delay of a display device by forming signal lines of Ag having lowl resistance. An oxide silicon layer(35) formed on a base layer(33) including silicon is plasma-processed to increase roughness of an interface(34) of the base layer and the oxide silicon layer. The oxide silicon layer is etched to be removed. An Ag layer is formed on the base layer. To increase the brightness of the interface, the oxide silicon layer is plasma-processed by using a reactive gas selected from the group consisting of argon(Ar), nitrogen(N2), ammonia(NH3), and a mixture thereof. In the etching of the oxide silicon layer, the oxide silicon layer is etched by using an etching solution containing fluoric acid(HF).

Description

Forming method of silver layer and manufacturing method of display substrate using same {METHOD FOR FORMING SILVER LAYER AND METHOD FOR FABRICATING DISPLAY SUBSTRATE USING THE METHOD}

1A to 1D are flowcharts illustrating a method of forming a silver layer according to an embodiment of the present invention.

2A to 2C are flowcharts illustrating a method of forming a silver layer according to another embodiment of the present invention.

3 is a plan view of a display substrate manufactured by a method of manufacturing a display substrate according to an exemplary embodiment of the present invention.

4A through 4E are flowcharts illustrating a method of manufacturing the display substrate illustrated in FIG. 3.

<Explanation of symbols for main parts of the drawings>

10, 310: glass substrate 20, 320: silicon nitride layer

31, 331: amorphous silicon layer 33, 333: doped amorphous silicon layer

34, 334: interface 35, 335: silicon oxide layer

350: passivation layer 370: pixel electrode

SE: source electrode GE: gate electrode

DE: drain electrode C: channel layer

TFT: Thin Film Transistor

The present invention relates to a method of forming a silver layer and a method of manufacturing a display substrate using the same. More specifically, the present invention relates to a method of forming a silver layer to improve adhesion between the lower layer and the silver (Ag) layer and a method of manufacturing a display substrate using the same.

In general, an active matrix liquid crystal display (LCD) includes substrates facing each other and a liquid crystal layer interposed between the substrates. A plurality of data lines, gate lines, and signal lines, such as a switching element connected to the data lines and the gate lines, are formed on the lower one of the substrates.

 Al-based alloys such as AlNd and pure Al are mainly used as the wiring material of the switching element. However, development of low-resistance metal wiring is absolutely required in a larger large area and high-resolution liquid crystal display device. Therefore, interest in low-resistance wiring such as Ag, which has a lower resistivity than Al currently used, is increasing.

 The silver (Ag) has a resistivity of 1.5 (μΩ-cm) in the bulk state, and the resistivity of the Ag thin film is about 2.1 (μΩ-cm) which is increased from the bulk value, and thus the lowest resistivity value of the thin film metal. Have Therefore, when AlNd is replaced with Ag, it has the advantage of having a half level of resistance. However, the silver layer has problems such as poor adhesion to a glass substrate or SiO 2 layer, poor chemical resistance, and easily react with dry etching gas, which is a subsequent process, to cause corrosion.

On the other hand, in order to solve the problem of poor adhesion with other layers, IZO / Ag / IZO wiring, ITO / Ag / ITO wiring, and Mo /, in which a film having improved adhesion and drying resistance to Ag etching is deposited on the upper and lower Ag wirings. A technique for wiring such as Ag / ITO has been disclosed. However, in the process of forming the source and drain wirings of the thin film transistor, if the metal layer of the multilayer is formed using another metal layer as the lower layer of the silver layer, there is a problem that the productivity of the manufacturing process is lowered.

Therefore, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a method of forming a silver layer to improve the adhesion between the silicon layer and the silver layer.

Another object of the present invention is to provide a method of manufacturing a display substrate using the method of forming the silver layer.

In order to realize the above object of the present invention, the method for forming a silver layer according to the embodiment is a plasma treatment of the silicon oxide layer formed on the base layer containing silicon, the roughness of the interface between the base layer and the silicon oxide layer ( roughness), etching and removing the silicon oxide layer, and forming a silver layer on the base layer.

Preferably, the step of increasing the roughness of the interface is performed by plasma treating the silicon oxide layer with a reaction gas selected from argon (Ar), nitrogen (N 2), ammonia (NH 3) and a mixture of these gases. The etching of the silicon oxide layer may be performed by etching the silicon oxide layer with an etchant containing hydrogen fluoride (HF). The base layer may be an amorphous silicon layer doped with n-type.

In order to achieve the above object of the present invention, a method of forming a silver layer according to another embodiment includes preparing a glass substrate having a surface roughness of 100 (Å) or more, and forming a silver layer on the glass substrate. .

Preferably, in the preparing of the glass substrate, a glass substrate having a surface roughness of 100 (Å) or less is mixed with DI water and hydrogen fluoride (HF) at a ratio of 200: 1 to 200: 5. Etching with an etchant to increase the surface roughness to 100 or more.

In order to realize the above object of the present invention, a method of manufacturing a display substrate according to an embodiment includes forming a gate wiring and a gate electrode on a glass substrate, and a silicon nitride layer covering the gate wiring and the gate electrode. Forming an amorphous silicon layer and an n-type doped amorphous silicon layer on the silicon nitride layer corresponding to the gate electrode; and forming an oxide silicon layer doped with the n-type doped amorphous silicon layer. Plasma treating the silicon layer to increase the roughness of the interface between the amorphous silicon layer and the silicon oxide layer doped with the n-type, and etching and removing the silicon oxide layer, and the n-type Source (Ag) is deposited on the amorphous silicon layer doped with a source source to cross the gate wiring, and the amorphous silicon doped with the n-type And forming a source electrode and a drain electrode spaced from each other on the floor.

Preferably, the step of increasing the roughness (roughness) of the interface of the silicon oxide layer is the silicon oxide layer with a reaction gas selected from argon (Ar), nitrogen (N2), ammonia (NH3) and a mixture thereof It is carried out by plasma treatment. The forming of the gate wiring and the gate electrode may include preparing a glass substrate having a surface roughness of 100 (Å) or more, and depositing silver (Ag) on the glass substrate to form the gate wiring and the gate electrode. Include. The method of manufacturing the display substrate further includes forming a passivation layer on the glass substrate on which the source electrode and the drain electrode are formed, and forming a pixel electrode electrically connected to the drain electrode.

According to the method of forming the silver layer and the manufacturing method of the display substrate using the same, a low resistance wiring can be formed to provide a display substrate having reduced signal delay or the like.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Silver (Ag) layer  Formation method

1A to 1D are flowcharts illustrating a method of forming a silver layer according to an embodiment of the present invention.

1A to 1D, a method of forming a silver layer is performed by plasma treatment of a silicon oxide layer 35 formed on a base layer 33 containing silicon, thereby forming the base layer 33 and the silicon oxide layer 35. Increasing the roughness of the interface 34 between the liver, etching and removing the silicon oxide layer 35, and forming a silver layer 40 on the base layer 33. .

First, as shown in FIG. 1A, a substrate on which the base layer 33 is formed is prepared. The substrate includes a glass substrate 10, a silicon nitride layer 20, an amorphous silicon layer 31, a base layer 33, and a silicon oxide layer 35, and the silicon nitride layer 20 and an amorphous silicon layer. The base layer 33 and the silicon oxide layer 35 are laminated on the glass substrate 10 in the order of their names.

In the present embodiment, the base layer 33 is an amorphous silicon layer 33 doped with n-type. In another embodiment, the substrate on which the silver layer 40 is formed may include various material layers, but the base layer 33 is preferably a layer on which a natural silicon oxide layer may be formed.

The silicon nitride layer 21 is deposited on the substrate 10 through high temperature chemical vapor deposition and low temperature chemical vapor deposition. The silicon nitride layer 21 is used as a final protective film of a silicon device because it has a property of a good diffusion barrier that is difficult to diffuse water or sodium.

The silicon oxide layer 35 is a layer formed by naturally oxidizing the amorphous silicon layer 33 doped with the n-type in contact with air. The silicon oxide layer 35 has a thickness of about 20 to 30 (kPa).

In order to form a high-quality wiring of the circuit part using the silver layer 40, the adhesion between the silver layer 40 and the lower layer of the silver layer 40, that is, the amorphous silicon layer 33 doped with the n-type Must be excellent Since the silver layer 40 is capable of electrically ohmic contact with the amorphous silicon layer 33 doped with the n-type, the amorphous silicon layer 33 doped with the silver layer 40 and n-type is possible. When the adhesive force between the) is improved, the silver layer 40 may be a material of excellent circuit wiring.

In general, adhesion between two materials is formed by diffusion and material bonding between the two materials, and it is known that the adhesion between the two materials increases as the area of the interface between the two materials increases.

Since there is little solubility that silver dissolves into the amorphous silicon layer 33 doped with the n-type, the adhesion between the silver layer 40 and the amorphous silicon layer 33 doped with the n-type is basically poor. However, if the area of the interface 34 between the silver layer 40 and the n-type doped amorphous silicon layer 33 is increased, the area between the silver layer 40 and the amorphous silicon layer 33 doped with the n-type is increased. Adhesion can be improved.

To this end, as shown in FIG. 1A, roughness of the interface 34 between the silver layer 40 and the amorphous silicon layer 33 doped with n-type is performed by plasma treatment of the silicon oxide layer 35. Improve). Here, the roughness is an index indicating the roughness of the surface, and is defined as the height difference between the highest portion and the lowest portion of the uneven surface.

Specifically, the silicon oxide layer 35 is plasma treated by a plasma chemical vapor deposition apparatus using a gas selected from argon (Ar), nitrogen (N 2), ammonia (NH 3), and a mixed gas thereof as a reaction gas. The substrate 10 is disposed on a lower electrode disposed in the chamber, and a reaction gas selected from argon (Ar), nitrogen (N 2), ammonia (NH 3), and a mixture of these gases is supplied into the chamber. High frequency power is applied to the upper electrode facing the lower electrode.

When free electrons generated by the glow discharge between the lower electrode and the upper electrode get enough energy to collide with the reaction gas molecules, ions of the reaction gas are generated to form a plasma. The ionized reaction gas obtains large energy and impinges on the silicon oxide layer 35. In this case, since the silicon oxide layer 35 is very thin, the impact amount due to the collision of the reaction gas ions is transferred to the amorphous silicon layer 33 doped with the n-type, which is the lower layer of the silicon oxide layer 35. As a result, as shown in FIG. 1B, the silicon oxide layer 35 and the amorphous silicon layer 33 doped with n-type are formed to have non-uniform thickness. That is, the surface roughness of the silicon oxide layer 35 and the amorphous silicon layer 33 doped with n-type is greatly increased.

Subsequently, the silicon oxide layer 35 is etched to expose the amorphous silicon layer 33 doped with n-type with increased surface roughness, as shown in FIG. 1C. Hydrofluoric acid (HF) is used as an etching solution of the silicon oxide layer 35. The etchant is preferably a mixture of DI water and hydrogen fluoride (HF) at about 200: 1.

Finally, as shown in FIG. 1D, the silver layer 40 is deposited on the n-type doped amorphous silicon layer 33 by sputtering. At this time, since the surface roughness of the amorphous silicon layer 33 doped with the n-type was greatly increased, the silver layer 40 and the amorphous silicon layer 33 doped with the n-type are well adhered.

2A to 2C are flowcharts illustrating a method of forming a silver layer according to another embodiment of the present invention.

2A to 2C, a method of forming a silver layer includes preparing a glass substrate 110 having a surface roughness of 100 (Å) or more, and forming a silver layer 120 on the glass substrate 110. Include.

First, in the case of the glass substrate 110 shown in Figure 2a, the surface roughness may be about 100 (Å) or less. In the case of the glass substrate 110 used as a display market of the display device, the surface 111 is formed to be very flat as a special glass substrate. In the present embodiment, before the silver layer 120 is formed on the glass substrate 110, the surface 111 of the glass substrate 110 is etched with an etchant, as shown in FIG. 2B, wherein the glass substrate is etched. Increase the surface roughness of (110).

Specifically, hydrofluoric acid (HF) is used as the etching solution. In order to increase the surface roughness of the glass substrate 110 to 100 (Å) or more, the etching solution is a mixture of DI water and hydrogen fluoride (HF) in a ratio of 200: 1 to 200: 5 It is preferable. The etchant increases the height difference between the high and low portions of the surface of the glass substrate 110 to increase the surface roughness of the glass substrate 110 to about 100 (Å) or more.

Thereafter, the silver layer 120 is formed by depositing silver on the surface 112 of which the surface roughness of the glass substrate 110 is increased in a sputtering manner. Since the surface roughness of the glass substrate 110 is greatly increased, the silver layer 120 adheres well to the surface 112 of the glass substrate 110.

Manufacturing Method of Display Board

3 is a plan view of a display substrate manufactured by a method of manufacturing a display substrate according to an exemplary embodiment of the present invention. 4A through 4E are process diagrams of the method of manufacturing the display substrate illustrated in FIG. 3. Specifically, FIGS. 4A to 4E are cross-sectional views taken along the line II ′ of FIG. 3, and show cross-sections according to process progress.

3 to 4E, a method of manufacturing a display substrate includes forming a gate wiring GL and a gate electrode GE on a glass substrate 310, and forming the gate wiring GL and the gate electrode GE. Forming a silicon nitride layer 320 and an amorphous silicon layer 331 and an n-type doped amorphous silicon layer on the silicon nitride layer 320 corresponding to the gate electrode GE. 333) and plasma treating the silicon oxide layer 335 formed on the n-type doped amorphous silicon layer 333 to oxidize the amorphous silicon layer 333 doped with the n-type. Increasing the roughness of the interface 334 between the silicon layer 335, Etching and removing the silicon oxide layer 335, On the amorphous silicon layer 333 doped with the n-type Source (SL) intersecting the gate line (GL) by depositing silver (Ag) on each other, and And forming a gyeokdoen source electrode (SE) and a drain electrode (DE).

First, as shown in FIG. 4A, a gate metal is deposited on the glass substrate 310 by a sputtering method, and the gate wiring GL and the gate electrode GE are formed through a photolithography process and an etching process. . The gate wiring GL and the gate electrode GE may be made of aluminum (Al), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), silver (Ag), and the like. Can be done.

When the gate line GL and the gate electrode GE are formed of silver (Ag), the forming of the gate line GL and the gate electrode GE may include forming a glass substrate having a surface roughness of 100 (Å) or more. And preparing silver (Ag) on the glass substrate 310 to form the gate line GL and the gate electrode GE. Preparing a glass substrate having a surface roughness of 100 (Å) or more is substantially the same as preparing a glass substrate having a surface roughness of 100 (Å) or more described with reference to FIGS. 2A to 2C.

Next, the silicon nitride layer 320 is formed to cover the entire glass substrate 310 on which the gate line GL and the gate electrode GE are formed by plasma chemical vapor deposition. The silicon nitride layer 320 is a protective insulating layer that insulates and protects the gate line GL and the gate electrode GE.

Thereafter, as shown in FIG. 4B, the amorphous silicon layer 331 and the amorphous silicon layer 333 doped with n-type are sequentially formed on the silicon nitride layer 320. For example, the amorphous silicon layer 331 is deposited through a plasma chemical vapor deposition method using a reaction gas in which SiF 4, H 2, and Ar are mixed, and a small amount of phosphine (PH 3), which is a doping gas, is mixed in the reaction gas. To deposit the amorphous silicon layer 333 doped with the n-type. At this time, the surface of the amorphous silicon layer 333 doped with n-type is naturally oxidized in contact with air. As a result, a silicon oxide layer 335 is formed on the n-type doped amorphous silicon layer 333.

Next, the silicon oxide layer 335 is plasma-treated with a reaction gas selected from argon (Ar), nitrogen (N 2), ammonia (NH 3), and a mixed gas thereof to form an amorphous silicon layer doped with the n-type ( The roughness of the interface 334 between the 333 and the silicon oxide layer 335 is increased. Increasing the roughness of the interface 334 is substantially the same as increasing the roughness of the interface 34 described in FIGS. 1A-1D.

Subsequently, in order to form a channel layer on the silicon nitride layer 320 corresponding to the gate electrode GE, the silicon oxide layer as shown in FIG. 4C through a photolithography process and an etching process. 335, the amorphous silicon layer 333 and the amorphous silicon layer 331 doped with n-type are patterned.

Subsequently, the silicon oxide layer 335 is etched to expose the amorphous silicon layer 333 doped with n-type having an increased surface roughness. Hydrofluoric acid (HF) is used as an etching solution of the silicon oxide layer 335. The etchant is preferably a mixture of DI water and hydrogen fluoride (HF) at about 200: 1.

In another embodiment, a process of patterning the silicon oxide layer 335, the amorphous silicon layer 333 doped with n-type, and the amorphous silicon layer 331, and etching and removing the silicon oxide layer 335 is performed. The order of progress of the processes can be reversed.

Thereafter, a silver layer is deposited on the n-type doped amorphous silicon layer 333 in a sputtering manner, as shown in FIG. 4D, the source wiring SL crossing the gate wiring GL, and the A source electrode SE and a drain electrode DE spaced apart from each other are formed on the n-type doped amorphous silicon layer 333 corresponding to the gate electrode GE.

In the process of forming the source wiring SL, the source electrode SE, and the drain electrode DE, an amorphous silicon layer doped with an n-type corresponding to the source electrode SE and the drain electrode DE. 333 is removed, and the corresponding amorphous silicon layer 331 is partially etched therebetween. As a result, a channel layer C is formed to electrically switch the source electrode SE and the drain electrode DE. In this case, since the surface roughness of the n-type doped amorphous silicon layer 333 is greatly increased, the source electrode SE and the drain electrode DE are the amorphous silicon layer 333 doped with the n-type. It adheres well to a phase.

Referring to FIG. 4E, the method of manufacturing the display substrate includes forming a passivation layer 350 on a glass substrate 310 on which the source electrode SE and the drain electrode DE are formed, and the passivation layer 350. And forming a pixel electrode 370 electrically connected to the drain electrode DE through a contact hole formed in the second hole.

The pixel electrode 370 is an indium-tin-oxide (ITO), indium-zinc-oxide (IZO), or indium-tin-zinc oxide (Indium-), which is a transparent conductive material. Tin-Zinc-Oxide).

As described in detail above, according to the present invention, the cohesion between the silver layer and the base layer is increased by greatly increasing the roughness of the interface between the silver layer and the base layer on which the silver layer is formed, for example, an amorphous silicon layer doped with n-type. Can greatly improve. Therefore, the signal wirings of the display device can be reduced by forming signal wires of silver having a very small resistance. As a result, it is possible to provide a display substrate which improves the display quality.

In the detailed description of the present invention described above with reference to the preferred embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary skill in the art will be described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

Claims (10)

Plasma processing the silicon oxide layer formed on the base layer including silicon to increase roughness of an interface between the base layer and the silicon oxide layer; Etching away the silicon oxide layer; And Forming a silver (Ag) layer on the base layer, characterized in that it comprises a. The method of claim 1, wherein the increasing of the roughness of the interface is performed by plasma treating the silicon oxide layer with a reaction gas selected from argon (Ar), nitrogen (N 2), ammonia (NH 3), and a mixture thereof. Formation method of the silver layer characterized by the above-mentioned. The method of claim 2, wherein the etching of the silicon oxide layer comprises etching the silicon oxide layer with an etchant containing hydrogen fluoride (HF). 4. The method of claim 3, wherein the base layer is an amorphous silicon layer doped with n-type. Preparing a glass substrate having a surface roughness of 100 (Å) or more; And Forming a silver layer on the glass substrate. The method of claim 5, wherein the preparing of the glass substrate comprises a glass substrate having a surface roughness of 100 (Å) or less in a ratio of DI water and hydrogen fluoride (HF) of 200: 1 to 200: 5. The method of forming a silver layer, comprising the step of etching with a mixed etchant to increase the surface roughness to 100 (Å) or more. Forming a gate wiring and a gate electrode on the glass substrate; Forming a silicon nitride layer covering the gate wiring and the gate electrode;  Forming an amorphous silicon layer and an n-type doped amorphous silicon layer on the silicon nitride layer corresponding to the gate electrode; Plasma treatment of the silicon oxide layer formed on the n-type doped amorphous silicon layer to increase roughness of an interface between the n-type doped amorphous silicon layer and the silicon oxide layer; Etching away the silicon oxide layer; And Depositing silver (Ag) on the n-type doped amorphous silicon layer to form a source wiring crossing the gate wiring, and a source electrode and a drain electrode spaced apart from each other. Manufacturing method. The method of claim 7, wherein the step of increasing the roughness of the interface is plasma treatment of the silicon oxide layer with a reaction gas selected from argon (Ar), nitrogen (N2), ammonia (NH3) and a mixture thereof Method of manufacturing a display substrate, characterized in that performed by. The method of claim 8, wherein the forming of the gate wiring and the gate electrode is performed. Preparing a glass substrate having a surface roughness of 100 (Å) or more; And And depositing silver (Ag) on the glass substrate to form the gate wiring and the gate electrode. The method of claim 9, Forming a passivation layer on the glass substrate on which the source electrode and the drain electrode are formed; And And forming a pixel electrode electrically connected to the drain electrode.

Images