KR20070083107A - Display device and driving method of the same - Google Patents

Abstract

A display apparatus and a driving method thereof are provided to achieve high resolution of the display apparatus by implementing first and second data drivers at both sides of a data patterning section. A display apparatus includes a display panel(100), and first and second data drivers(120,130). The display panel includes plural pixel units defined by gate patterns(GL1~GLn) and data patterns. The first data driver drives odd-numbered data patterns(DL1~DLm-1) of the data patterns. The second data driver drives even-numbered data patterns(DL2~DLm) of the data patterns. The first and second data drivers are formed at one end portion and the other end portion of the data patterns, respectively.

Description

DISPLAY DEVICE AND DRIVING METHOD OF THE SAME}

1 is a schematic structural block diagram of a display device according to an exemplary embodiment of the present invention.

2 is a signal waveform diagram of the timing controller of FIG. 1.

3 is a detailed block diagram of the first data driver IC.

4 is a detailed block diagram of the second data driver IC.

<Description of the symbols for the main parts of the drawings>

100: display panel 110: gate driver

120: first data driver 130: second data driver

140: timing controller 150: gamma reference voltage generator

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a display device and a driving method thereof, and more particularly, to a display device for realizing high definition and a driving method thereof.

Generally, a liquid crystal display device includes a display panel displaying an image by light transmittance of a liquid crystal, and a driving circuit unit electrically connected to the display panel to provide driving signals for displaying an image to the display panel.

The display panel includes an array substrate and an opposing substrate (eg, a color filter substrate) bonded to each other at a predetermined interval, and a liquid crystal layer interposed between the array substrate and the opposing substrate. A plurality of pixel portions are formed in the display panel by intersecting gate lines and data lines. Each pixel unit includes a thin film transistor having a gate electrode and a source electrode electrically connected to a gate line and a data line, and a liquid crystal capacitor and a storage capacitor electrically connected to a drain electrode of the thin film transistor.

The driving circuit unit includes a gate driver, a data driver, and a timing controller, and the timing controller controls the gate driver and the data driver. The gate driver outputs a gate signal to the gate lines in response to the data signals output to the data lines. The data driver converts a data signal input from an external graphic device into an analog data signal and outputs the data signal to the data lines.

The data driver includes a data driver IC that processes data by grouping a plurality of data wires in predetermined units. The data driving IC outputs the input data signal to the data lines through various data processing processes.

Such liquid crystal display devices have recently been trending toward high resolution and high definition. That is, the number of data wires increases, while the number of data wires that one data driving IC can drive is limited. Therefore, a large number of data driver ICs are required to drive data wires that increase with high resolution and high definition. However, due to spatial constraints, it is difficult to form a sufficient number of data driver ICs, which makes it difficult to develop high resolution and high resolution models. In addition, the high resolution and the high resolution cause a driving frequency increase in accordance with the processing of the data signal, there is a problem that increases the power consumption.

Accordingly, the technical problem of the present invention is to solve the above disadvantages, and an object of the present invention is to provide a display device and a driving method for realizing high definition and reducing power consumption to reduce power consumption.

A display device according to an embodiment for realizing the above object of the present invention includes a display panel, a first data driver and a second data driver. The display panel includes a plurality of pixel parts formed by intersecting gate lines and data lines. The first data driver drives odd-numbered data wires among the data wires, and the second data driver drives even-numbered data wires among the data wires.

According to an aspect of the present invention, there is provided a method of driving a display device, the method including: receiving a main clock signal and a data signal in synchronization with the main clock signal; Generating a data clock signal divided by the main clock signal; Latching odd-numbered data signals of the data signals and even-numbered data signals of the data signals based on the data clock signals; And outputting the latched odd-numbered data and even-numbered data signals to odd-numbered data lines and even-numbered data lines, respectively.

According to such a display device and its driving method, power consumption can be reduced by halving the driving frequency, and it becomes possible to form a sufficient data driving IC for driving data wires that increase with high definition.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention, and FIG. 2 is a signal waveform diagram of the timing controller of FIG. 1.

1 and 2, a display device according to an exemplary embodiment of the present invention includes a timing controller 140, a gate driver 110, a first data driver 120, a second data driver 130, and a gamma reference voltage. The generator 150 and the display panel 100 are included. The gate driver 110, the first data driver 120, the second data driver 130, the gamma reference voltage generator 150, and the timing controller 140 may drive the display panel 100 to display an image. It is defined as a driving circuit section for applying signals.

The display panel 100 includes an array substrate and an opposing substrate (eg, a color filter substrate) facing each other at a predetermined interval, and a liquid crystal layer interposed between the array substrate and the opposing substrate. The display panel 100 includes a plurality of pixel parts formed by crossing gate lines GL1 to GLn and data lines DL1 to DLm. Each pixel unit includes a thin film transistor TFT that is a switching element, a liquid crystal capacitor CLC, and a storage capacitor CST that are electrically connected to the thin film transistor TFT. In this case, the gate electrode and the source electrode of the TFT are electrically connected to the gate line and the data line, respectively, and the liquid crystal capacitor CLC and the storage capacitor CST are electrically connected to the drain electrode.

The timing controller 140 inputs externally the synchronization signals and the data signal DATA including the main clock signal MCLK, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE. Receive. Based on the received synchronization signals, gate control signals for controlling the gate driver 110 and data control signals for controlling the first data driver 120 and the second data driver 130 are generated.

Specifically, gate control signals including the vertical start signal STV and the gate clock signal GATE CLK for controlling the gate driver 110 are generated and provided to the gate driver 110. The same data control is generated by generating data control signals including a horizontal start signal STH, a data clock signal DCLK, and a load signal LOAD for controlling the first data driver 120 and the second data driver 130. The signals are provided to the first data driver 120 and the second data driver 130, respectively.

In addition, the timing controller 140 divides the input data signal DATA into the first data signal DATA_1 and the second data signal DATA_2, so that the first data signal DATA_1 is the first data driver 120. The second data signal DATA_2 is provided to the second data driver 130.

Specifically, as illustrated in FIG. 2, the data signal DATA received from the external graphic device is divided into a first data signal DATA_1 that is an odd data signal and a second data signal DATA_2 that is an even data signal. To be treated. At this time, the data clock in which the main clock signal MCLK is divided into two so as to divide the input data signal DATA into an odd data signal and an even data signal at the same clock timing as the main clock signal MCLK may be processed. Data processing is performed based on the signal DCLK. The data clock signal DCLK in which the main clock signal MCLK is divided into two has a frequency 1/2 of the frequency of the main clock signal MCLK.

That is, the data signal DATA input from the external graphic device is applied with the data signal of the unit pixel unit corresponding to every cycle of the main clock signal MCLK. On the other hand, the timing controller 140 simultaneously outputs the first data signal DATA_1 and the second data signal DATA_2 to the first data driver 120 and the second data driver 130, respectively. As a result, the timing controller 140 generates and uses the data clock signal DCLK in which the main clock signal MCLK is divided into two to adjust the clock timing.

The gate driver 110 is formed at one end of the gate lines GL1 to GLn and receives gate control signals including the vertical start signal STV and the gate clock signal GATE CLK from the timing controller 140. . The gate signals are sequentially output to the gate lines GL1 to GLn formed on the display panel 100 in synchronization with the input gate control signals.

The gamma reference voltage generator 150 generates a plurality of gamma reference voltages VGMA and outputs them to the first data driver 120 and the second data driver 130, respectively.

The first data driver 120 includes at least one first data driver IC for processing the first data signal DATA_1 received from the timing controller 140 in units of horizontal pixels. The first data driver 120 converts the first data signal DATA_1 into an analog signal based on the provided data control signals and outputs the analog data to odd-numbered data lines.

The second data driver 130 includes at least one second data driver IC for processing the second data signal DATA_2 received from the timing controller 140 in units of horizontal pixels. The second data driver 130 converts the second data signal DATA_2 into an analog signal based on the provided data control signals and outputs the analog data to the even-numbered data lines.

Here, the first data driver 120 and the second data driver 130 receive the same data control signals from the timing controller 140.

The first data driver 120 is formed at one end of the data lines DL1 to DLm, and the second data driver 130 is formed at the other end of the data lines DL1 to DLm.

3 is a detailed block diagram of the first data driver IC.

1 and 3, the first data driver IC includes a data register 310, a shift register 320, a latch unit 330, a digital / analog converter 340, and an output buffer unit 350. do.

The data register 310 relays the first data signal DATA_1 provided from the timing controller 140 to the latch unit 330. That is, the odd-numbered data signal is relayed to the latch unit 330.

The shift register 320 generates a sequential sampling signal and provides it to the latch unit 330. Specifically, the horizontal start signal STH input from the timing controller 140 is shifted in response to the data clock signal DCLK, and is provided to the latch unit 330 as a sampling signal.

The latch unit 330 includes a plurality of unit latches. The latch unit 330 samples and latches the first data signal DATA_1 in response to a sampling signal, and latches in response to a load signal LOAD applied from the timing controller 140. The first data signal DATA_1 is simultaneously output in units of horizontal pixels. That is, in response to the sampling signal provided from the shift register 320, after sampling and latching the first data signal DATA_1 (eg, the odd-numbered data signal) provided from the data register 310, the load signal LOAD may be When input, the first data signal DATA_1 corresponding to one horizontal pixel column latched is simultaneously output.

The data / analog converter 340 receives the first data signal DATA_1 provided from the latch unit 330 and is based on the plurality of gamma reference voltages VGMA provided from the gamma reference voltage generator 150. To convert it into a corresponding analog data signal and output it.

The output buffer unit 350 includes a plurality of buffers, and buffers an analog data signal output from the data / analog converter 340 to output odd-numbered data lines.

4 is a detailed block diagram of the second data driver IC.

1 and 4, the second data driver IC includes a data register 310, a shift register 320, a latch unit 330, a digital / analog converter 340, and an output buffer unit 350. do.

The configuration of the second data driver IC is the same as that of the first data driver IC, and has only the difference of receiving the second data signal DATA_1, converting it to an analog data signal, and outputting the data signal to the even data lines. Therefore, the detailed description of the second data driver IC will be omitted for convenience of description.

Meanwhile, the first data driver IC and the second data driver IC may be formed by a chip on glass (COG) method formed on a substrate of the display panel 100 or may be a tape carrier package (TCP). Mounted on the substrate 100 and electrically connected to the data pads of the display panel 100. In general, the chip-on-glass method is applied to the small and medium-sized display device to increase the ratio of the display panel 100 and to increase the configuration of the impact or vibration of the mobile product.

As described above, according to the present invention, a first data driver for driving odd-numbered data wires and a second data driver for driving even-numbered data wires are provided, and the first data driver and the second data driver are data wired. By forming the respective ends of the field, the power consumption can be reduced by reducing the driving frequency, and the data driving IC is formed by dividing the both ends, so that the data driving unit can be easily formed to cope with a high resolution and high definition model.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (6)

A display panel in which a plurality of pixel portions are formed by crossing gate lines and data lines; A first data driver to drive odd-numbered data lines among the data lines; And And a second data driver for driving even-numbered data lines among the data lines. The display device of claim 1, wherein the first data driver is formed at one end of the data lines and the second data driver is formed at the other end of the data lines. The display device of claim 2, wherein the first data driver and the second data driver simultaneously output data signals of one horizontal pixel column. The display apparatus of claim 1, further comprising: receiving a main clock signal and a data signal from an external device, and outputting a data clock signal divided by two main clock signals to the first data driver and the second data driver, respectively; And a timing controller configured to output an odd-numbered data signal of the data signal to the first data driver and output an even-numbered data signal of the data signal to a second data driver. A driving method of a display device including a display panel in which a plurality of pixel portions are formed by crossing gate lines and data lines. Receiving a data signal in synchronization with the main clock signal and the main clock signal from the outside; Generating a data clock signal divided by the main clock signal; Latching odd-numbered data signals of the data signals and even-numbered data signals of the data signals based on the data clock signals; And And outputting the latched odd-numbered data and even-numbered data signals to odd-numbered data lines and even-numbered data lines, respectively. The method of claim 5, wherein the odd-numbered data signal is output to one end of the data wires and the even-numbered data signal is output to the other end of the data wires.

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