KR20070076653A - Thin film transistor substrate and method of manufacturing the same - Google Patents

Abstract

A thin film transistor substrate and a manufacturing method thereof are provided to prevent disconnection of a pixel electrode formed on a patterned passivation layer and improve a product yield and productivity by forming a gentle side profile of a photoresist formed on a drain electrode and a passivation layer, and preventing undercut when the passivation layer is etched. A gate electrode(110) is formed on a substrate(100). A gate insulating layer(120) is formed on the substrate including the gate electrode. An active layer(130) is formed on the gate insulating layer, and is patterned. A source electrode(140) and a drain electrode(150) are formed on the active layer. A passivation layer(160) is formed on an entire structure. The passivation layer is patterned to form a contact hole(200) on the drain electrode. A pixel electrode(170) is formed on the contact hole and the passivation layer. The drain electrode includes a pattern part(155) formed by removing the electrode at a portion of a circumstance of the contact hole.

Description

Thin Film Transistor Substrate And Method Of Manufacturing The Same

1 is a plan view of a thin film transistor substrate according to the present invention.

2 is a cross-sectional view taken along the line A-A.

3A to 3C are cross-sectional views for explaining the formation of a contact hole according to the present invention.

4A and 4B are sectional views showing another example of the drain electrode according to the present invention.

5A through 5E are cross-sectional views sequentially illustrating a process of manufacturing a thin film transistor substrate according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100 substrate 110 gate electrode

120: gate insulating film 130: active layer

140: source electrode 150: drain electrode

160: protective film 170: pixel electrode

180: photoresist pattern 200: contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same. More particularly, a thin film transistor substrate capable of preventing undercut during etching of a protective layer for forming a contact hole and preventing disconnection of a pixel electrode and a manufacturing thereof It is about a method.

In general, a liquid crystal display (LCD) includes a thin film transistor substrate including a thin film transistor (TFT) and a pixel electrode including a gate electrode, a source electrode, and a drain electrode, a black matrix, a color filter, It consists of a common electrode substrate in which a common electrode etc. were formed, and the liquid crystal sealed between two board | substrates. Here, the liquid crystal display displays an image by applying a voltage between two substrates to drive the liquid crystal and controlling the transmittance of light.

The patterns formed on the substrate of the liquid crystal display are repeatedly manufactured by a deposition process, a cleaning process, an exposure process of forming a pattern using a mask, an etching process, and the like, and the gate electrode, the active layer, and the source electrode of the thin film transistor substrate. The drain electrode, the protective film, the pixel electrode and the like are formed by repeating the above processes.

In the thin film transistor substrate, a gate electrode is formed on the transparent substrate, and a gate insulating film is formed on the substrate including the gate electrode. An active layer is formed on the gate insulating layer, and a source electrode and a drain electrode are formed on the active layer to form a thin film transistor. In addition, a passivation layer is further formed on the source electrode and the drain electrode to protect the thin film transistor, and a portion of the passivation layer penetrates to form a contact hole connecting the drain electrode and the pixel electrode to each other.

A brief description will be given of the formation of a contact hole connecting the drain electrode and the pixel electrode to form a protective film on the source and drain electrodes and then apply a photosensitive material such as a photoresist. The photoresist is exposed and developed using a predetermined mask to form a photoresist pattern, and the protective film is etched so that a part of the drain electrode is opened using the photoresist pattern as an etch mask. In this case, a contact hole connected to the pixel electrode may be formed through the open drain electrode.

However, when the protective layer is etched using the photoresist pattern, an undercut phenomenon occurs in which excessive etching occurs to the side of the lower portion of the photoresist pattern. The occurrence of such undercut makes it difficult to form a contact hole having a desired design rule, and thus it is difficult to form a source or drain electrode with a desired design rule. In addition, when undercut occurs, there is a problem of causing open of the pixel electrode formed on the patterned passivation layer.

The present invention is to solve the above problems, by forming a pattern of the drain electrode around the contact hole, thereby forming a side profile of the photoresist formed on the drain electrode and the protective film to form a contact hole gently and An object of the present invention is to provide a thin film transistor substrate capable of preventing undercut during etching and preventing disconnection of a pixel electrode, and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a method including: forming a gate electrode on a substrate, forming a gate insulating film on the substrate including the gate electrode, and forming and patterning an active layer on the gate insulating film; Forming a source electrode and a drain electrode on the active layer, forming a protective film on the entire structure, patterning the protective film to form a contact hole on the drain electrode, and a pixel electrode on the contact hole and the protective film And forming a portion of the contact hole around the contact hole, wherein the drain electrode includes a pattern portion from which the electrode is removed.

The forming of the contact hole may include forming a photoresist pattern having a contact region open on the passivation layer, performing an etching process of the passivation layer through the photoresist pattern, and removing the remaining photoresist pattern. It may include. The photoresist pattern preferably has a gentle side profile with a tilt angle of less than 90 ° from horizontal. More preferably the photoresist pattern is characterized by having a gentle side profile with an inclination angle of less than 37 ° from horizontal.

The drain electrode may form a pattern portion in the form of enclosing a semicircle along the circumference of the contact hole, or may form a plurality of pattern portions divided in the form of enclosing the entire circle along the circumference of the contact hole.

The present invention provides a substrate, a gate electrode formed on the substrate, a gate insulating film formed on the front surface including the gate electrode, an active layer formed on the gate insulating film, a source and drain electrode formed on the active layer, and a contact hole region on the drain electrode. A thin film transistor including a passivation layer formed on the source and drain electrodes, and a pixel electrode formed on the contact hole and the passivation layer, wherein the drain electrode includes a pattern portion having an electrode removed around a portion of the contact hole. Provide a substrate.

The pattern portion may be formed in a form of enclosing a semi-circle along the circumference of the contact hole, or may be divided into a plurality of forms in the form of enclosing the entire circle along the circumference of the contact hole.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you.

In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity, and like reference numerals designate like elements. In addition, when a part such as a layer, a film, an area, or a plate is expressed as being on or above another part, not only when each part is directly above or directly above the other part but also another part between each part and another part This includes cases.

1 is a plan view of a thin film transistor substrate according to the present invention, and FIG. 2 is a cross-sectional view taken along line A-A of the thin film transistor substrate of FIG. 1.

The thin film transistor substrate may include a plurality of gate lines that transmit a gate signal on the transparent insulating substrate 100 and extend in a first direction and have a predetermined distance in a second direction, and a plurality of source lines formed to cross the gate lines; And a pixel electrode 170 formed in the pixel region defined by the gate line and the source line, and a plurality of thin film transistors formed in a matrix form at the intersection of the gate line and the source line.

The thin film transistor causes the pixel signal supplied to the source line to be charged in the pixel electrode 170 in response to the signal supplied to the gate line. Accordingly, the thin film transistor includes a gate electrode 110 connected to the gate line, a source electrode 140 connected to the source line, a drain electrode 150 connected to the pixel electrode 170, and a gate electrode 110. The gate insulating layer 120 and the active layer 130 are sequentially formed between the source electrode 140 and the drain electrode 150.

An insulating protective layer 160 is formed on the thin film transistor. The passivation layer 160 may be formed of an inorganic material such as silicon nitride or silicon oxide, or may be formed of a low dielectric constant organic film. Of course, it may be formed of a double layer of an inorganic insulating film and an organic film. In addition, the pixel electrode 170 is formed on the passivation layer 160.

A contact hole 200 formed through a portion of the passivation layer 160 is formed on the drain electrode 150 to connect the drain electrode 150 and the pixel electrode 170. In this case, the drain electrode 150 has a pattern portion 155 having a predetermined groove shape formed around the region where the contact hole 200 is formed. As illustrated, the pattern portion 155 may be formed to enclose a semicircle along the circumference of a region where the protective layer 160 is removed to form the contact hole 200. Here, the pattern portion 155 means a region where the electrode is not formed. Due to the drain electrode 150 including the pattern portion 155, a predetermined curvature may be formed in the passivation layer 160 formed thereon. Accordingly, the passivation layer 160 for forming the contact hole 200 may be formed. The side profile of the photoresist formed at the time of etching may be gently formed. This will be described later in detail.

3A to 3C are cross-sectional views illustrating the formation of a contact hole according to the present invention. This is a cross-sectional view taken along the line B-B in the case of FIG.

Referring to FIG. 3A, a drain electrode 150 including a gate insulating layer 120 and a predetermined pattern portion 155 is formed on the substrate 100. Here, the pattern portion 155 means a region where the electrode is not formed in a groove shape. The pattern unit 155 may be formed around the region where the contact hole 200 is to be formed. To this end, after forming a conductive film on the gate insulating film 120, the drain electrode 150 is formed through an etching process through a predetermined mask pattern. At this time, the pattern portion 155 of the drain electrode 150 is also etched. When the insulating protective film 160 is formed on the drain electrode 150 including the pattern portion 155 as described above, the protective film 160 is formed with a predetermined curvature along the pattern of the drain electrode 150. That is, the portion where the drain electrode 150 is formed is formed to have a uniform thickness, but the portion where the pattern portion 155 is formed is formed in a relatively low surface shape.

Referring to FIG. 3B, after the photoresist is applied on the drain electrode 150 and the passivation layer 160, a lithography process using a mask is performed to form a photoresist pattern 180 that opens the contact region. In this case, the photoresist pattern 180 having a side profile as shown in the drawing may be manufactured due to a predetermined curvature formed in the passivation layer 160. That is, the photoresist pattern 180 having a gentle side profile with an inclination angle smaller than 90 ° from horizontal can be manufactured.

Referring to FIG. 3C, the protective layer 160 is etched through an etching process using the photoresist pattern 180 as an etch mask, and the remaining photoresist pattern 180 is removed to form the contact hole 200. As described above, in the case of the photoresist pattern 180 having a gentle side profile, undercutting may be efficiently prevented when the protective layer 160 is etched.

During the etching process, the passivation layer 160 in the region opened by the photoresist pattern 180 is etched, and as the etching proceeds, the passivation layer 160 is excessively etched toward the side of the passivation layer 160 under the photoresist pattern 180 to cause undercut. do. At the same time as the etching of the passivation layer 160, the photoresist pattern 180 also tends to be consumed to some extent. As described above, the photoresist pattern 180 having a gentle side profile has a relatively thin thickness, so May be etched. Accordingly, the side portion of the photoresist pattern 180 may be removed to etch the passivation layer 160, thereby preventing undercut due to side etching. Thus, in order to prevent the occurrence of undercut, it is preferable that the side profile of the photoresist pattern 180 is gentle. In particular, in the case of the photoresist pattern having a side profile of 37 ° or less from the horizontal when manufacturing the 26-inch monitor, it was found that no undercut occurred at the time of forming the contact hole.

4A and 4B are sectional views showing another example of the drain electrode according to the present invention. As described above, the drain electrode 150 of the present invention includes a pattern portion 155 around the region where the contact hole 200 is formed. The pattern portion 155 may be formed in a shape surrounding the semicircle of the contact hole 200 as shown in FIG. 4A, and surrounds the entire circle of the contact hole 200 as shown in FIG. 4B. The pixel electrode may be divided into a plurality of parts so as not to be disconnected from the pixel electrode connected through the contact hole 200. The pattern portion 155 of the drain electrode 150 is not limited thereto and may be formed in various shapes around the contact hole 200, and may be formed so as not to be disconnected from the pixel electrode connected through the contact hole. Do.

5A through 5E are diagrams sequentially illustrating a process of manufacturing a thin film transistor substrate according to the present invention.

Referring to FIG. 5A, a first conductive film is formed on the transparent insulating substrate 100, and then the gate line and the gate electrode 110 are formed through a photolithography process using a first photoresist mask pattern (not shown). .

First, a first conductive film is formed on the transparent insulating substrate 100 by a deposition method using a CVD method, a PVD method, a sputtering method, or the like. It is preferable to use at least one of Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), and Cr / Al (Nd) as the first conductive film. Ar / Cr, Al / Mo, Al (Nd) / Al, Al (Nd) / Cr, Mo / Al (Nd) / Mo, Cu / Mo, Ti / Al (Nd) / Ti, Mo / Al, Mo / Ti / Al (Nd), Cu alloy / Mo, Cu alloy / Al, Cu alloy / Mo alloy, Cu alloy / Al alloy, Al / Mo alloy, Mo alloy / Al, Al alloy / Mo alloy , A Mo alloy / Al alloy or the like may be formed. Thereafter, after the photoresist film is applied, a lithography process using the first mask is performed to form the first photoresist mask pattern. An etching process using the first photoresist mask pattern as an etching mask may be performed to form the gate line and the gate electrode 110 as shown in the drawing. Thereafter, a predetermined strip process is performed to remove the first photoresist mask pattern.

Referring to FIG. 5B, the gate insulating layer 120 and the active layer 130 are sequentially formed on the entire structure shown in FIG. 5A, and then the active region of the thin film transistor is formed through a photolithography process using a second photoresist mask pattern. Form.

The gate insulating film 120 is formed on the entire substrate through a deposition method using a PECVD method, a sputtering method, or the like. In this case, it is preferable to use an inorganic insulating material including silicon oxide or silicon nitride as the gate insulating film 120. The active layer 130 is formed on the gate insulating layer 120 through the above-described deposition method. An amorphous silicon layer is used as the active layer 130. Thereafter, a photoresist film is coated on the active layer 130, and then a second photoresist mask pattern is formed by performing a lithography process using a second mask. The active layer 130 is removed by forming an active region on the gate electrode 110 by performing an etching process using the second photoresist mask pattern as an etch mask and the gate insulating layer 120 as an etch stop layer. Thereafter, a predetermined strip process is performed to remove the remaining second photoresist mask pattern. In this case, the gate insulating film 120 is preferably formed to a thickness of 1500 to 5000 kPa, and the active layer 130 is preferably formed to a thickness of 500 to 2000 kPa.

Referring to FIG. 5C, after forming the second conductive film, the source and drain electrodes 140 and 150 and the source line are formed through a photolithography process using the third photoresist mask pattern.

The second conductive film is formed on the entire structure through various deposition methods using CVD, PVD, sputtering, or the like. In this case, at least one of Mo, Al, Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), and Cr / Al (Nd) may be used as the second conductive film. It is preferable to use. Ar / Cr, Al / Mo, Al (Nd) / Al, Al (Nd) / Cr, Mo / Al (Nd) / Mo, Cu / Mo, Ti / Al (Nd) / Ti, Mo / Al, Mo / Ti / Al (Nd), Cu alloy / Mo, Cu alloy / Al, Cu alloy / Mo alloy, Cu alloy / Al alloy, Al / Mo alloy, Mo alloy / Al, Al alloy / Mo alloy , A Mo alloy / Al alloy or the like may be formed. Of course, the same material as that of the first conductive film may be used for the second conductive film. It is preferable to deposit a 2nd electroconductive film in the thickness of 1,500 micrometers-3,000 micrometers. Thereafter, a photosensitive film is coated on the second conductive film, and then a lithography process using a mask is performed to form a third photoresist mask pattern. The second conductive film is etched through an etching process using the third photoresist mask pattern as an etching mask to form a source electrode 140, a drain electrode 150, and a source line. At this time, the pattern portion 155 of the drain electrode 150, that is, the predetermined second conductive film positioned around the region where the contact hole 200 is to be formed is simultaneously etched. Next, a predetermined strip process is performed to remove the remaining third photoresist mask pattern.

By the above-described process, the source line extends in the direction crossing the gate line formed below. In addition, the source electrode 140 extends from the source line to overlap a portion of the active region, and the drain electrode 150 overlaps a portion of the active region, and a portion of the source electrode 140 extends to the pixel region and is connected to the pixel electrode 170. .

Referring to FIG. 5D, the passivation layer 160 is formed on the entire structure where the source electrode 140 and the drain electrode 150 are formed, and a portion of the passivation layer 160 is removed through an etching process using a fourth photoresist mask pattern. To form a contact hole 200.

That is, the protective film 160 is formed on the overall structure shown in FIG. 5C through various deposition methods. For the passivation layer 160, the same insulating material as that of the gate insulating layer 120 is preferably used. In addition, the protective film 160 may be formed in a multilayer. For example, it can be formed from two layers, an inorganic protective film and an organic protective film. After the photoresist is coated on the passivation layer 160, a photolithography process using a mask is performed to form a fourth photoresist mask pattern that opens the contact region. In this case, the fourth photoresist mask pattern having the moderate side profile may be formed by the pattern portion 155 of the lower drain electrode 150. Thereafter, an etching process using the fourth photoresist mask pattern as an etch mask is performed to open the drain electrode 150, the gate pad at the end of the gate line, and the plurality of contact holes at the end of the source pad. 200). The remaining fourth photoresist mask pattern is removed by performing a predetermined strip process. Here, due to the photoresist mask pattern having a gentle side profile as described above, it is possible to effectively prevent the occurrence of undercut during etching of the protective layer 160 of the contact region.

Referring to FIG. 5E, a third conductive layer is formed on the patterned passivation layer 160, and then the third conductive layer is patterned using a fifth photoresist mask pattern to connect the pixel electrode 170, the gate pad, and the source pad. Form a pad. Here, it is preferable to use a transparent conductive film containing indium tin oxide (ITO) or indium zinc oxide (IZO) as the third conductive film.

First, a third conductive film is formed on the entire structure shown in FIG. 5D by a predetermined deposition method, then a photosensitive film is applied, and a lithography process using a mask is performed to form a fifth photosensitive film mask pattern. The remaining region except for a predetermined region of the pixel region, the gate pad region, the pad region connecting the source pad region, and the drain electrode 150 connected to the pixel electrode 70 is opened by the fifth photoresist mask pattern. Next, when the open region of the third conductive film is removed through an etching process using the fifth photoresist mask pattern as an etch mask, and the fifth photoresist mask pattern is removed through a predetermined strip process, the gate pad, the source pad, and the pixel electrode ( 170) is formed.

In the thin film transistor substrate manufactured according to the manufacturing process, a pattern of the drain electrode is formed around a portion of the contact hole, thereby preventing undercut during etching of the protective film for forming the contact hole. Accordingly, there is an advantage of preventing disconnection of the pixel electrode formed on the patterned passivation layer, improving product yield, and increasing productivity.

The thin film transistor substrate of the above-described embodiment is formed by a five-sheet mask process, but is not limited thereto, and may be formed by five or more mask processes or five or less mask processes.

Hereinafter, the liquid crystal display device using the thin film transistor substrate of the present invention described above will be described.

The liquid crystal display device includes a thin film transistor substrate as a lower substrate, a common electrode substrate as an upper substrate disposed opposite thereto, and a liquid crystal layer formed between the two substrates and oriented in a desired direction with respect to the two substrates.

As described above, the thin film transistor substrate may include a plurality of gate lines that transmit a gate signal on the translucent insulating substrate and extend in a first direction and have a predetermined interval in a second direction, and a plurality of sources formed to cross the gate lines. A line, a pixel electrode formed in the pixel region defined by the gate line and the source line, and a plurality of thin film transistors formed in a matrix form at the intersection of the gate line and the source line. The thin film transistor includes a gate electrode connected to a gate line, a source electrode connected to a source line, a drain electrode connected to a pixel electrode, a gate insulating film and an active layer sequentially formed between the gate electrode, the source electrode, and the drain electrode. .

The common electrode substrate has a black matrix and a red, green and blue color filter formed on a lower surface of an insulating substrate made of a transparent insulating material such as glass to prevent light interference between light leakage and adjacent pixel regions. An overcoat film made of an organic material is formed thereon. The common electrode made of a transparent conductive material such as ITO or IZO is formed on the overcoat film.

The first alignment layer and the second alignment layer are formed on the entire structure of the thin film transistor substrate and the common electrode substrate as described above, and the substrates are bonded to each other through a spacer between the thin film transistor substrate and the common electrode substrate. In addition, a liquid crystal display is formed by injecting a liquid crystal material into a predetermined space formed by a spacer using a vacuum injection method to form a liquid crystal layer.

When a voltage is applied to the liquid crystal display, the pixel electrode receives the pixel signal supplied from the thin film transistor to generate a potential difference with the common electrode formed on the common electrode substrate. Due to this potential difference, the liquid crystal positioned between the thin film transistor and the common electrode substrate is rotated by the dielectric anisotropy, and the amount of light incident through the pixel electrode from the light source (not shown) is controlled and transmitted to the common electrode substrate.

As mentioned above, although this invention was demonstrated in detail using the preferable Example, the scope of the present invention is not limited to a specific Example and should be interpreted by the attached Claim. In addition, those skilled in the art should understand that many modifications and variations are possible without departing from the scope of the present invention.

The present invention forms a pattern of the drain electrode around the contact hole, thereby gently forming the side profile of the photoresist formed on the drain electrode and the protective film for forming the contact hole, and preventing the occurrence of undercut during the etching of the protective film. Can be. Accordingly, there is an advantage of preventing disconnection of the pixel electrode formed on the patterned passivation layer, improving product yield, and increasing productivity.

Claims (9)

Forming a gate electrode on the substrate; Forming a gate insulating film on the substrate including the gate electrode; Forming and patterning an active layer on the gate insulating film; Forming a source electrode and a drain electrode on the active layer; Forming a protective film on the entire structure; Patterning the passivation layer to form a contact hole on the drain electrode; And Forming a pixel electrode on the contact hole and the passivation layer; The drain electrode includes a pattern portion in which the electrode is removed around a portion of the contact hole. The method according to claim 1, Forming the contact hole, Forming a photoresist pattern on the protective layer, the contact region being opened; Performing an etching process of the passivation layer through the photoresist pattern; And And removing the remaining photoresist pattern. The method according to claim 2, And the photoresist pattern has a gentle side profile with an inclination angle of less than 90 ° from horizontal. The method according to claim 2, And the photoresist pattern has a gentle side profile with an inclination angle of less than 37 ° from horizontal. The method according to any one of claims 1 to 4, The drain electrode is a method of manufacturing a thin film transistor substrate, characterized in that for forming a pattern portion in the form of enclosing a semi-circle along the circumference of the contact hole. The method according to any one of claims 1 to 4, The drain electrode is a method of manufacturing a thin film transistor substrate, characterized in that for forming a plurality of pattern parts divided in a form surrounding the entire circle along the circumference of the contact hole. Board; A gate electrode formed on an upper surface of the substrate; A gate insulating film formed on the entire surface including the gate electrode; An active layer formed on the gate insulating film; Source and drain electrodes formed on the active layer; A protective film formed on the source and drain electrodes except for the contact hole region on the drain electrode; And A pixel electrode formed on the contact hole and the passivation layer; The drain electrode includes a pattern portion in which the electrode is removed around a portion of the contact hole. The method according to claim 7, The pattern portion thin film transistor substrate, characterized in that formed in the form surrounding the semicircle along the circumference of the contact hole. The method according to claim 7, The pattern portion thin film transistor substrate, characterized in that divided into a plurality in the form surrounding the entire circle along the circumference of the contact hole.

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