KR100525442B1 - liquid crystal display device and method for fabricating the same - Google Patents

Abstract

Providing a liquid crystal display device suitable for improving the image quality by preventing the generation of wavy noise by preventing the capacitance value between the pixel electrode and the data line in accordance with the on / off period of the backlight, and a method of manufacturing the same In order to achieve the above object, a liquid crystal display device includes a gate line formed in one direction on an insulating substrate; A first data line spaced apart from the gate line and formed in a direction perpendicular to the gate line; A second data line intersecting with the gate line on the same line as the first data line; A thin film transistor formed at an intersection of the gate line and the second data line; An active layer formed below the second data line, the source electrode and the drain electrode of the thin film transistor; A third data line electrically connecting the first and second data lines and crossing the gate line to define a pixel area; And a pixel electrode formed in the pixel region.

Description

Liquid crystal display device and method for manufacturing the same {liquid crystal display device and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method for manufacturing the same, which can improve a wavy noise defect that may occur in a four mask structure.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for the use of mobile image display device because of the excellent image quality, light weight, thinness, and low power consumption, and mobile type such as monitor of notebook computer. In addition, it is being developed in various ways, such as a television for receiving and displaying broadcast signals, and a monitor of a computer.

In order to use a liquid crystal display as a general screen display device in various parts, development of high quality images such as high definition, high brightness, and large area is required while maintaining the characteristics of light weight, thinness, and low power consumption. It can be said.

A general liquid crystal display device may be broadly divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second glass substrates bonded to each other with a predetermined space; It consists of a liquid crystal layer injected between the said 1st, 2nd glass substrate.

The first glass substrate (TFT array substrate) may include a plurality of gate lines arranged in one direction at a predetermined interval, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, and A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing each gate line and data line, and a plurality of thin films that transmit signals of the data line to each pixel electrode by being switched by signals of the gate line A transistor (Thin Film Transistor, hereinafter referred to as TFT) is formed.

The second glass substrate (color filter array substrate) includes a black matrix layer for blocking light in portions other than the pixel region, R, G, B color filter layers for expressing color colors, and R, G, B A common electrode is formed to implement an image of a color of. Of course, the common electrode is formed on the first glass substrate in the transverse electric field type liquid crystal display device.

The first and second glass substrates are bonded by a sealing material having a predetermined space by a spacer and having a liquid crystal injection hole, and a liquid crystal is injected between the two substrates.

In this case, in the liquid crystal injection method, the liquid crystal is injected between the two substrates by osmotic pressure when the liquid crystal injection hole is immersed in the liquid crystal container by maintaining the vacuum state between the two substrates bonded by the reality. When the liquid crystal is injected as described above, the liquid crystal injection hole is sealed with a sealing material.

On the other hand, the driving principle of the liquid crystal display device as described above uses the optical anisotropy and polarization of the liquid crystal.

Since the liquid crystal is thin and long in structure, the liquid crystal has a direction in the arrangement of molecules, and the liquid crystal may be artificially applied to control the direction of the molecular arrangement.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Therefore, R & D of selective driving TFTs of each pixel electrode is focused on improving the yield and reducing the manufacturing cost by improving productivity, thereby improving the structure of the TFT, improving the characteristics of amorphous or polycrystalline silicon, and ohmic contact resistance of the electrode. And disconnection / short circuit prevention.

More research is being done on the structure of the double TFT because of its large area, low cost, and mass production. The TFT is divided into two types according to the position of the gate.

One is a bottom gate type called inverse stagger type and the other is a top gate type called forward stagger type.

Forming a gate electrode on a substrate first is called a bottom gate type, and forming a source / drain electrode first and then forming a gate electrode is called a top gate type.

Hereinafter, an example of using four masks when manufacturing a bottom gate type liquid crystal display device in which a gate electrode is first formed and then a source / drain electrode is formed will be described.

Hereinafter, a conventional liquid crystal display device and a manufacturing method thereof will be described with reference to the accompanying drawings.

1 is an enlarged plan view of a unit pixel of a conventional liquid crystal display device, and FIG. 2 is a structural cross-sectional view of a liquid crystal display device according to the prior art on lines II ′ and II-II ′ of FIG. 1.

In the liquid crystal display according to the related art, as shown in FIGS. 1 and 2, a gate line 32 having a gate electrode 32 a is formed on a lower substrate 31, and the gate line is defined to define a pixel region. The data line 36a is formed in the direction perpendicular to the 32.

A source electrode 36b is formed by protruding from the data line 36a, and a drain electrode 36c is formed spaced apart from the source electrode 36b by a predetermined interval.

The source electrode 36b protrudes to have a '⊂' shaped groove, and the drain electrode 36c is spaced apart from the source electrode 36b at a predetermined interval inside the '⊂' shaped groove. The channel region is formed in a '⊂' shape between the electrode 36b and the drain electrode 36c.

A gate electrode 32a protrudes to one side of the gate line 32, and a gate insulating layer 33 is formed on the lower substrate 31 including the gate line 32.

An active layer 34a is formed on the gate insulating layer 33 on the gate electrode 32a. The active layer 34a includes a data line 36a, a source electrode 36b, a drain electrode 36c, A width wider than the data line 36a, the source electrode 36b, and the drain electrode 36c is formed below the channel region. At this time, the active layer 34a is made of amorphous silicon.

An ohmic contact layer 34b made of n + amorphous silicon is formed between the data line 36a, the source electrode 36b, the drain electrode 36c, and the active layer 34a except for the channel region.

A protective film 37 is formed on the entire lower substrate 31 including the data line 36a, and a contact hole 38 is formed in the protective film 37 on one region of the drain electrode 36c.

The transparent pixel electrode 39 is formed in the pixel area to contact the drain electrode 36c through the contact hole 38.

In order to manufacture the liquid crystal display device having the above configuration, four masks are required. Hereinafter, a method of manufacturing a liquid crystal display device according to the related art using four masks will be described.

3A to 3H are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to the prior art on the lines II ′ and II-II ′ of FIG. 1.

First, as shown in FIG. 3A, a gate metal is deposited on the lower substrate 31 by a sputtering method, and a first photoresist P / R1 is coated on the gate metal, and then, a first mask is used. Exposure and development are performed to form a first photoresist (P / R1) pattern for forming a gate line. The gate electrode 32a is formed to selectively protrude from the gate line 32 (see FIG. 1) and the gate line 32 by selectively removing the gate metal layer using the first photoresist (P / R1) pattern as a mask. After forming, the first photoresist (P / R1) pattern is peeled off.

The gate metal layer is formed of chromium (Cr), molybdenum (Mo), and aluminum-based metal in a single layer or a double layer structure.

As shown in FIG. 3B, a gate insulating film 33 is formed over the entire lower substrate 31 including the gate line 32 and the gate electrode 32a.

Thereafter, the first and second semiconductor layers 34 and 35 of the gate insulating layer 33 (amorphous silicon layer, n + amorphous silicon layer), and the data metal layer 36 are sequentially deposited.

Thereafter, the second photoresist P / R2 is applied onto the data metal layer 36.

As shown in FIG. 3C, a second photoresist (P / R2) pattern for a data line pattern is formed on the data metal layer 36 by an exposure and development process using a second mask (half-tone mask).

In the second mask (half-tone mask), a portion corresponding to the data line is completely blocked, and a portion corresponding to the channel region of the thin film transistor is formed to irradiate a predetermined amount of light. Therefore, the developed second photoresist (P / R2) pattern maintains the deposited thickness in the data line formation region and the source / drain electrode formation region, and the channel region of the thin film transistor is formed to be relatively thin.

Subsequently, the data metal layer 36 and the second and first semiconductor layers 35 and 34 are removed by a wet or dry process using a second photoresist (P / R2) pattern.

As shown in FIG. 3D, the second photoresist (P / R2) pattern is ashed to remove the second photoresist corresponding to the channel region of the thin film transistor. In this case, the second photoresist (P / R2) pattern may be thinner and its width may be reduced. Therefore, the widths of the subsequent data lines and the source / drain electrodes are changed.

As shown in FIG. 3E, the data metal layer 36 and the second semiconductor layer 35 corresponding to the channel region of the thin film transistor are formed using the ashed second photoresist (P / R2) pattern as a mask. ), A thin film transistor having a data line 36a, a source electrode 36b, and a drain electrode 36c is formed, and then the second photoresist P / R2 is peeled off.

Accordingly, the first semiconductor layer 34 of the channel region is exposed to separate the source electrode 36b and the drain electrode 36c, and the active layer 34a composed of the first semiconductor layer 34 and the channel region are separated. The ohmic contact layer 35a is formed on the active layer 34a.

As the material of the gate insulating film 33, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

As the data metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy) and the like are used.

As shown in FIG. 3F, the protective film 37 is formed on the entire surface of the lower substrate 31 including the data line 36a by a deposition method such as PECVD.

A third photoresist P / R3 is applied on the passivation layer 37. The third photoresist (P / R3) pattern may be formed to expose a portion of the drain electrode 36c by an exposure and development process using a third mask, and the third photoresist pattern may be used as a mask. The protective layer 37 is selectively etched to form a contact hole 38 (see FIG. 1) in the drain electrode 36c. Then, the third photoresist P / R3 is peeled off.

As the material of the protective film 37, an inorganic insulating material such as the gate insulating film 33, an acrylic organic compound having a low dielectric constant, an organic insulating material such as BCB or PFCB, or the like is used.

As shown in FIG. 3G, a transparent electrode material is deposited on the entire surface of the substrate to be connected to the drain electrode 36c through the contact hole 38. A fourth photoresist P / R4 is coated on the transparent electrode material, and a fourth photoresist P / R4 pattern is formed to pattern the pixel electrode through an exposure and development process using a fourth mask.

The transparent electrode material is selectively removed using the fourth photoresist pattern as a mask to form a pixel electrode 39 in the pixel region as shown in FIG. 3H. Then, the fourth photoresist is peeled off.

The pixel electrode 39 is electrically connected to the drain electrode 36c through the contact hole 38 (see FIG. 1).

By this process, the active layer 34a is formed with a wider line width than the data line 36a.

In the conventional liquid crystal display device manufactured by the above method, the line width of the active layer 34a is wider than that of the data line 36a and the source / drain electrodes 36b and 36c.

After fabricating the lower substrate (thin film transistor array substrate) by the above method, the alignment process for alignment of liquid crystal molecules, the sealing and spacing process, the upper and lower substrate bonding process, and the scribe & break process The lower substrate is separated into cell units to complete the liquid crystal panel of the liquid crystal display.

Since most of the liquid crystal display devices manufactured as described above are light-receiving devices that display images by controlling the amount of light coming from the outside, a separate light source for irradiating light to the liquid crystal panel, that is, a back light, is necessarily required. .

However, when the light applied from the backlight is applied as described above, the conductivity of the active layer formed of the amorphous silicon layer of the liquid crystal panel is changed. (This is due to the property that the conductivity changes when the semiconductor layer receives light and heat.)

In other words, when the backlight is turned off, the active layer existing in the amorphous silicon layer state is metallized by the light of the backlight when the backlight is turned on.

As described above, when the backlight is driven, the amorphous silicon layer is metallized, thereby affecting the data line 36a positioned on the amorphous silicon layer.

In addition, the data line 36a and the pixel electrode 39 are adjacent to each other, and there is a capacitance therebetween. As the amorphous silicon layer is metallized, data is turned on / off when the backlight is turned on or off. A difference also occurs in the capacitance value between the line 36a and the pixel electrode 39.

That is, a difference occurs in the capacitance value between the data line 36a and the pixel electrode 39, such as Cdp (backlight on)> Cdp (backlight off), resulting in a difference between the charge) is changed.

In addition, the backlight may be driven by receiving a signal from an inverter circuit, wherein the amorphous silicon layer is metallized even when the backlight is turned on or off according to the on / off of the inverter. A difference occurs in the capacitance value between the pixel electrodes, thereby changing the charge of the pixel electrode.

As a result, in the liquid crystal display device using the conventional four-mask process, the luminance is changed due to the potential change of the pixel electrode 39 according to the on / off period of the backlight, and the way in which the wavy lines continue to move upward on the screen. There is a problem in which a wavy noise phenomenon occurs.

The present invention has been made to solve the above problems, an object of the present invention is to prevent the capacitance value between the pixel electrode and the data line in accordance with the on / off period of the backlight to prevent the change of the wavy noise (wavy noise) An object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which are suitable for improving the image quality by preventing the occurrence.

Liquid crystal display device of the present invention for achieving the above object comprises a gate line formed in one direction on an insulating substrate; A first data line spaced apart from the gate line and formed in a direction perpendicular to the gate line; A second data line intersecting with the gate line on the same line as the first data line; A thin film transistor formed at an intersection of the gate line and the second data line; An active layer formed below the second data line, the source electrode and the drain electrode of the thin film transistor; A third data line electrically connecting the first and second data lines and crossing the gate line to define a pixel area; And a pixel electrode formed in the pixel region.

The first data line is formed of the same material on the same layer as the gate line.

The gate line and the first data line are formed of at least one of a conductive metal film such as chromium, aluminum, aluminum alloy (AlNd), tantalum, and molybdenum (Mo).

The first data line is formed adjacent to the pixel electrode.

A passivation layer is further provided on an entire surface of the insulating substrate including the second data line.

First, second and third contact holes may be formed in the passivation layer on both sides of the first data line, on both sides of the second data line, and on one region of the drain electrode.

The third data line electrically connects the first data line and the second data line through the first and second contact holes.

The thin film transistor may include: a source electrode protruding from the second data line; A drain electrode formed to be spaced apart from the source electrode at a predetermined interval; It includes a gate electrode protruding from one side of the gate line.

The source electrode overlaps an upper portion of one side of the gate electrode and has a '⊂' shape groove.

The drain electrode overlaps the upper portion of the other side of the gate electrode, and is formed to be spaced apart from the source electrode by a predetermined interval inside the '⊂'-shaped groove.

An ohmic contact layer is further formed on the active layer below the second data line, the source electrode, and the drain electrode except for the channel region.

The pixel electrode is formed on the same layer as the third data line.

The pixel electrode and the third data line are formed of a transparent electrode material of indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO).

The second data line has a structure in which an amorphous silicon layer, an n + amorphous silicon layer, and a metal layer are stacked.

In the method of manufacturing the liquid crystal display device according to the present invention having the above configuration, a gate line having a gate electrode on an insulating substrate and a first data line spaced apart from the gate line are formed in a direction perpendicular to the gate line. step; Forming a gate insulating film on the entire surface including the gate line and the first data line, and depositing a semiconductor layer and a conductive film in order; Patterning the semiconductor layer and the metal layer to form a second data line having source / drain electrodes on the same line as the first data line so as to cross the gate line; Forming a third data line to define a pixel area above the first and second data lines to electrically connect the first and second data lines; And forming a pixel electrode in the pixel region.

The first data line is simultaneously formed on the same layer as the gate line.

The gate line and the first data line are formed of at least one layer of a conductive metal film such as chromium, aluminum, aluminum alloy (AlNd), tantalum, and molybdenum (Mo).

The first data line is formed to be adjacent to the pixel electrode.

The source electrode, the drain electrode, and the second data line may include sequentially depositing first and second semiconductor layers and a conductive film on the gate insulating film; Forming a photoresist pattern on the conductive layer using a half-tone mask having a diffraction exposure portion over the channel region; Etching the conductive layer, the second and first semiconductor layers using the photoresist pattern; Removing the photoresist pattern by an ashing process so that the conductive film on the channel region is exposed; The conductive layer and the second semiconductor layer are etched so that the first semiconductor layer of the channel region is exposed to form the source electrode, the drain electrode, and the second data line, and the active except the channel region. Forming an ohmic contact layer on the layer; Removing the photoresist pattern.

The source electrode overlaps an upper portion of one side of the gate electrode and is formed to have a '⊂' shape groove.

The drain electrode overlaps the upper portion of the other side of the gate electrode, and is formed to be spaced apart from the source electrode by a predetermined distance inside the '⊂'-shaped groove.

A passivation layer is further formed on an entire surface of the insulating substrate including the second data line.

The protective layer is formed of one selected from an inorganic insulating material including a silicon nitride film or a silicon oxide film, and an organic insulating material containing benzocyclobutene (BCB), an acrylic resin, and the like.

First, second and third contact holes may be formed in the passivation layer on both sides of the first data line, on both sides of the second data line, and on one region of the drain electrode.

The third data line electrically connects the first data line and the second data line through the first and second contact holes.

The pixel electrode is formed on the same layer as the third data line.

The pixel electrode and the third data line are formed of a transparent electrode material of indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO).

Hereinafter, a liquid crystal display device and a manufacturing method thereof according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

First, the configuration of the liquid crystal display device according to the present invention will be described.

4 is an enlarged plan view of a unit pixel of the liquid crystal display device of the present invention, and FIG. 5 is a structural cross-sectional view of the liquid crystal display device according to the present invention on lines III-III 'and IV-IV' of FIG. 4.

In the liquid crystal display according to the present invention, as shown in FIGS. 4 and 5, a gate line 62 is formed in one direction on the lower substrate 61, and a gate electrode is formed on one side of the gate line 62. 62a) is formed. The first data line 62b is formed on the same layer as the gate line 62 and spaced apart from the gate line 62 in a direction perpendicular to the gate line 62.

A gate insulating layer 63 is formed on the lower substrate 61 including the gate line 62, and the gate line 62 is interposed between the first data line 62b on the gate insulating layer 63. The second data line 66a is formed to intersect.

A thin film transistor is formed at the intersection of the gate line 62 and the second data line 66a.

More specifically, the thin film transistor includes a source electrode 66b protruding from the second data line 66a, a drain electrode 66c spaced apart from the source electrode 66b by a predetermined distance, and the gate line 62. It consists of a gate electrode (62a) protruding from one side of.

The source electrode 66b protrudes to have a '⊂' shaped groove, and the drain electrode 66c is spaced apart from the source electrode 66b at a predetermined interval inside the '⊂' shaped groove. A channel region is formed in a '⊂' shape between the electrode 66b and the drain electrode 66c.

In the plan view, the first data line 62b is formed on the same line as the second data line 66a and spaced apart from the second data line 66a by a predetermined distance.

In addition, the first data line 62b is formed on the upper and lower portions of the second data line 66a in plan view.

The first data line 62b is adjacent to the pixel electrode 69 which will be described later.

The active layer 64a is formed on the gate insulating layer 63 including the upper portion of the gate electrode 62a. The active layer 64a is formed under the thin film transistor region and the second data line 66a. It is formed in a wider width than the two data lines 66a and is composed of an amorphous silicon layer.

An ohmic contact layer 65a made of n + amorphous silicon is formed on the active layer 64a under the second data line 66a, the source electrode 66b, and the drain electrode 66c except for the channel region.

The passivation layer 67 is formed on the entire lower substrate 61 including the second data line 66a.

The passivation layer 67 may have first to third contact holes 68a, 68b, and 68c so that both sides of the first data line 62b, both sides of the second data line 66a, and one region of the drain electrode 66c are exposed. ) Is formed.

The pixel electrode 69 is formed in the pixel region so as to contact the drain electrode 66c through the third contact hole 68c and the first data line through the first and second contact holes 68a and 68b. The third data line 69a is arranged on the same layer as the pixel electrode 69 in a direction orthogonal to the gate line 62 so that the second data line 66a and 62b are electrically connected to each other.

The third data line 69a defines a pixel area perpendicular to the gate line 62.

The pixel electrode 69 and the third data line 69a may be transparent electrodes such as indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO). Consists of matter.

As described above, since the first data line 62b and the second data line 66a are connected to the third data line 69a through the first and second contact holes 68a and 68b, the first data line 62b and the second data line 66a are connected to each other. The line 62b, the second data line 66a and the third data line 69a are combined to act as a substantial data line.

As described above, an active layer is not formed below the first data line 62b adjacent to the pixel electrode 69, and the first and third data lines 62b and 69a made of a metal and a transparent conductive material are formed. Therefore, the capacitance value Cdp between the pixel electrode 69 and the adjacent data lines (first and third data lines) is changed during the ON / OFF operation of the inverter for driving the backlight. Can be prevented.

The liquid crystal display device of the present invention having the above configuration is manufactured using four masks. Hereinafter, a manufacturing method of the liquid crystal display device using four masks will be described.

6A through 6H are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to the present invention, taken along lines III-III ′ and IV-IV ′ of FIG. 4.

In the method of manufacturing a liquid crystal display device according to the present invention, as shown in FIG. 6A, at least one of gate metals such as chromium, aluminum, aluminum alloy (AlNd), tantalum, and molybdenum (Mo) is deposited on the lower substrate 61. The first photoresist P / R1 is coated on the gate metal, and then exposed and developed using a first mask to form a gate line and a first data line. Form a pattern.

The gate line 62 and the gate electrode 62a protruding toward one side of the gate line 62 may be selectively removed by selectively removing the gate metal using the first photoresist (P / R1) pattern as a mask. The first data line 62b is simultaneously formed to be spaced apart from the gate line 62 in a direction perpendicular to the gate line 62. Thereafter, the first photoresist (P / R1) pattern is peeled off.

At this time, the first data line 62b is positioned on the plane at a predetermined interval above and below the same line as the second data line to be formed later.

Instead of forming a single layer, the gate metal is formed of two layers, a lower layer made of aluminum or aluminum-neodymium (AlNd) alloy and an upper layer made of molybdenum (Mo), or an upper layer made of chromium and an aluminum-neodymium alloy. It can also be formed from a double layer of.

When the double layer is formed in this manner, since the resistance of the aluminum-based metal used as the lower layer of the gate line and the first data line is small, the RC delay of the signal flowing through the gate line and the first data line can be reduced, and the upper layer is used. Since molybdenum has a high corrosion resistance to chemicals, there is an advantage that it is possible to prevent problems caused by disconnection due to erosion by the etching solution.

As shown in FIG. 6B, a gate insulating layer 63 is formed over the entire lower substrate 61 including the gate line 62 and the first data line 62b.

Thereafter, the first and second semiconductor layers 64 and 65 are sequentially deposited on the gate insulating layer 63, and then a data metal layer 66 such as chromium, tantalum, or titanium is deposited on the entire lower substrate 61.

In this case, the first and second semiconductor layers are composed of an amorphous silicon layer and an n + amorphous silicon layer.

Thereafter, the second photoresist P / R2 is applied on the data metal layer 66.

As shown in FIG. 6C, an exposure and development process using a second mask (half-tone mask) having a diffraction exposure portion over the data region on the data metal layer 66 is performed for the active layer pattern of the second data line and the thin film transistor. A second photoresist (P / R2) pattern is formed.

In the second mask (half-tone mask), a portion corresponding to the second data line is completely blocked, and a portion corresponding to the channel region of the thin film transistor is formed to irradiate a predetermined amount of light. Therefore, the developed second photoresist (P / R2) pattern maintains the deposited thickness in the second data line forming region, and the channel region of the thin film transistor is formed to be relatively thin.

Subsequently, the data metal layer 66 and the second and first semiconductor layers 65 and 64 are removed by a wet or dry process using a second photoresist (P / R2) pattern.

In this case, the data metal layer 66 on the first data line 62b is removed.

As shown in FIG. 6D, the second photoresist P / R2 pattern is ashed to remove the second photoresist P / R2 corresponding to the channel region of the thin film transistor.

At this time, the thickness of the second photoresist (P / R2) pattern is reduced and the width thereof is reduced. Therefore, the widths of the data lines and the source / drain electrodes formed later are different.

As shown in FIG. 6E, the data metal layer 66 and the second semiconductor layer 66 corresponding to the channel region of the thin film transistor are etched using the ashed second photoresist (P / R2) pattern as a mask. The thin film transistor including the second data line 66a, the source electrode 66b, and the drain electrode 66c is formed, and then the second photoresist (P / R2) pattern is peeled off.

Accordingly, the source electrode 66b and the drain electrode 66c are separated, and the first semiconductor layer 64 of the channel region is exposed to form an active layer 64a formed of the first semiconductor layer 64. An ohmic contact layer 65a is formed on the active layer 34a except for the region.

As the material of the gate insulating layer 63, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

As the data metal, molybdenum (Mo), titanium, tantalum, or molybdenum alloy (Mo alloy) is used.

In this case, the source electrode 66b is formed to overlap the upper portion of the gate electrode 62a so as to have a '⊂'-shaped groove, and the drain electrode 66c is overlapped on the other side of the gate electrode 62a to form the' k '. It is formed to be spaced apart from the source electrode 66b by a predetermined interval inside the groove.

By the above process, the channel region existing between the source electrode 66b and the drain electrode 66c has a '⊂' shape.

As shown in FIG. 6F, the passivation layer 67 is formed on the entire surface of the lower substrate 61 including the second data line 66a by a deposition method such as PECVD.

The passivation layer 67 is formed by depositing one selected from an inorganic insulating material including a silicon nitride film or a silicon oxide film, and an organic insulating material including benzocyclobutene (BCB) and an acrylic resin. do.

Thereafter, the third photoresist P / R3 is applied on the protective film 67. The third photoresist P may be exposed so that both sides of the first data line 62b and both sides of the second data line 66a and a portion of the drain electrode 66c are exposed through an exposure and development process using a third mask. / R3) pattern and selectively protects the passivation layer 37 and the gate insulating layer 63 by using the third photoresist (P / R3) pattern as a mask to form the first data line 62b. A first contact hole 68a is formed on both sides, a second contact hole 68b is formed on both sides of the second data line 66a, and a third contact hole 68c is formed in one region of the drain electrode 66c. . Then, the third photoresist (P / R3) pattern is peeled off.

As shown in FIG. 6G, the first data line 62b is contacted through the first contact hole 68a, and the second data line 66a is contacted through the second contact hole 68b. The transparent electrode material is deposited on the entire surface of the substrate to be in contact with the drain electrode 66c through the three contact holes 68c. The fourth photoresist (P / R4) is coated on the transparent electrode material, and a fourth photoresist (P / R4) pattern for patterning the pixel electrode and the third data line is formed by an exposure and development process using a fourth mask. Form.

Thereafter, the transparent electrode material is selectively removed using the fourth photoresist (P / R4) pattern as a mask to form the pixel electrode 69 in the pixel region as shown in FIG. 6H. The third data line 69a is formed to contact the first data line 62b and the second data line 66a through the second contact holes 68a and 68b.

Then, the fourth photoresist (P / R4) pattern is peeled off.

In this case, indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

In this case, the third data line 69a connects the first data line 62b and the second data line 66a through the first and second contact holes 68a and 68b.

Substantial data lines for transmitting signals are configured by combining first to third data lines 62b, 66a, and 69a.

As described above, the active layer formed of the amorphous silicon layer is not formed below the first and third data lines 62b and 69a adjacent to the pixel electrode 69 and is not formed to be adjacent to the pixel electrode 69. It is formed only under 66a and the source / drain electrodes 66b and 66c.

That is, an active layer made of an amorphous silicon layer is not formed below the first and third data lines 62b and 69a adjacent to the pixel electrode 69.

After fabricating the lower substrate (thin film transistor array substrate) by the above method, the alignment process for alignment of liquid crystal molecules, the sealing and spacing process, the upper and lower substrate bonding process, and the scribe & break process By completing the liquid crystal panel of the liquid crystal display device separated by cell unit.

Since most of the liquid crystal display devices manufactured as described above are light-receiving devices that display images by controlling the amount of light coming from the outside, a separate light source for irradiating light to the liquid crystal panel, that is, a back light, is necessarily required. .

The backlight generally receives a driving signal through an inverter and emits light to the liquid crystal panel.

As described above, since an active layer formed of an amorphous silicon layer is not formed below the first and third data lines 62b and 69a adjacent to the pixel electrode 69, the backlight is turned on as the inverter is turned on. Although light is generated and the active layer 64a composed of the amorphous silicon layer is metallized, the pixel electrode is not affected.

As described above, it is possible to prevent a phenomenon in which a capacitance value between the pixel electrode and the data line is changed when the backlight is turned on or off due to the on / off of the inverter.

The present invention is not limited to the above embodiments, and includes various forms that can be easily derived by those skilled in the art from the above embodiments.

The liquid crystal display of the present invention as described above and a manufacturing method thereof have the following effects.

By not forming an active layer composed of an amorphous silicon layer under the first and third data lines adjacent to the pixel electrode, the capacitance value between the pixel electrode and the data line is changed when the inverter is turned on / off for driving the backlight. Can be prevented.

This improves the quality of the wavy noise and improves the image quality.

1 is an enlarged plan view of a unit pixel of a conventional liquid crystal display device

FIG. 2 is a structural cross-sectional view of a conventional liquid crystal display device on the lines II ′ and II-II ′ of FIG. 1.

3A to 3H are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to the prior art on lines II ′ and II-II ′ of FIG. 1.

4 is an enlarged plan view of a unit pixel of a liquid crystal display of the present invention;

5 is a structural cross-sectional view of the liquid crystal display device according to the present invention along the III-III 'and IV-IV' line of FIG.

6A through 6H are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to the present invention, taken along lines III-III 'and IV-IV' of FIG. 4.

Explanation of symbols on the main parts of the drawings

61: lower substrate 62: gate line

62a: gate electrode 62b: first data line

63: gate insulating film 64a: active layer

65a: ohmic contact layer 66a: second data line

66b, 66c: source and drain electrodes 67: protective film

68a, 68b, and 68c: first, second and third contact holes

69 pixel electrode 69a third data line

Claims (27)

A gate line formed in one direction on the insulating substrate; A first data line spaced apart from the gate line and formed in a direction perpendicular to the gate line; A second data line intersecting with the gate line on the same line as the first data line; A thin film transistor formed at an intersection of the gate line and the second data line; An active layer formed below the second data line, the source electrode and the drain electrode of the thin film transistor; A third data line electrically connecting the first and second data lines and crossing the gate line to define a pixel area; And a pixel electrode formed in the pixel region. The method of claim 1, And the first data line is formed of the same material on the same layer as the gate line. The method of claim 1, And the gate line and the first data line are formed of at least one of a conductive metal film such as chromium, aluminum, aluminum alloy (AlNd), tantalum, and molybdenum (Mo). The method of claim 1, And the first data line is adjacent to the pixel electrode. The method of claim 1, And a passivation layer on the entire surface of the insulating substrate including the second data line. The method of claim 5, And a first contact hole, a second contact hole, and a third contact hole formed on both sides of the first data line, on both sides of the second data line, and on one region of the drain electrode. device. The method according to claim 1 or 6, And the third data line electrically connects the first data line and the second data line through the first and second contact holes. The method of claim 1, The thin film transistor may include: a source electrode protruding from the second data line; A drain electrode formed to be spaced apart from the source electrode at a predetermined interval; And a gate electrode protruding from one side of the gate line. The method of claim 8, The source electrode overlaps an upper portion of one side of the gate electrode, and has a '⊂' shape groove. The method of claim 8, And the drain electrode overlaps with an upper portion of the gate electrode and is spaced apart from the source electrode by a predetermined distance inside the '⊂'-shaped groove. The method of claim 8, And an ohmic contact layer is further formed on the active layer below the second data line, the source electrode, and the drain electrode except for the channel region. The method of claim 1, And the pixel electrode is formed on the same layer as the third data line. The method of claim 12, The pixel electrode and the third data line may be formed of a transparent electrode material of indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO). Liquid crystal display device. The method of claim 1, And the second data line has a structure in which an amorphous silicon layer, an n + amorphous silicon layer, and a metal layer are stacked. Forming a gate line having a gate electrode on the insulating substrate and a first data line spaced apart from the gate line in a direction perpendicular to the gate line; Forming a gate insulating film on the entire surface including the gate line and the first data line, and depositing a semiconductor layer and a conductive film in order; Patterning the semiconductor layer and the metal layer to form a second data line having source / drain electrodes on the same line as the first data line so as to cross the gate line; Forming a third data line to define a pixel area above the first and second data lines to electrically connect the first and second data lines; And forming a pixel electrode in the pixel region. The method of claim 15, And the first data line is formed on the same layer as the gate line at the same time. The method of claim 15, And the gate line and the first data line are formed of at least one of a conductive metal film such as chromium, aluminum, aluminum alloy (AlNd), tantalum, and molybdenum (Mo). The method of claim 15, And the first data line is adjacent to the pixel electrode. The method of claim 15, The source electrode, the drain electrode and the second data line, Sequentially depositing first and second semiconductor layers and a conductive film on the gate insulating film; Forming a photoresist pattern on the conductive layer using a half-tone mask having a diffraction exposure portion over the channel region; Etching the conductive layer, the second and first semiconductor layers using the photoresist pattern; Removing the photoresist pattern by an ashing process so that the conductive film on the channel region is exposed; The conductive layer and the second semiconductor layer are etched so that the first semiconductor layer of the channel region is exposed to form the source electrode, the drain electrode, and the second data line, and the active except the channel region. Forming an ohmic contact layer on the layer; And removing the photoresist pattern. The method of claim 19, The source electrode is overlapped on one side of the gate electrode, the manufacturing method of the liquid crystal display device characterized in that it is formed to have a '⊂' shape groove. The method of claim 19, The drain electrode overlaps with an upper portion of the other side of the gate electrode, and the liquid crystal display device, characterized in that formed in the '⊂' groove to be spaced apart from the source electrode by a predetermined interval. The method of claim 15, A protective film is formed on the entire surface of the insulating substrate including the second data line. The method of claim 22, The protective film is formed of one selected from an inorganic insulating material including a silicon nitride film or a silicon oxide film, and an organic insulating material containing benzocyclobutene (BCB), acrylic resin, and the like. Method of manufacturing a liquid crystal display device. The method of claim 22, And forming first, second and third contact holes on both sides of the first data line, on both sides of the second data line, and on one region of the drain electrode, respectively. Manufacturing method. The method of claim 24, And the third data line electrically connects the first data line and the second data line through the first and second contact holes. The method of claim 15, And the pixel electrode is formed on the same layer at the same time as the third data line. The method of claim 15, The pixel electrode and the third data line may be formed of a transparent electrode material of indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO). Method of manufacturing a liquid crystal display device.