KR101232166B1 - Liquid Crystal Display Device and method for fabricating the same - Google Patents

Abstract

The present invention is to provide a liquid crystal display device and a manufacturing method thereof suitable for preventing the light leakage phenomenon when the off state due to the step in the upper and lower boundary regions of the gate line, a liquid crystal display device for achieving the above object A first substrate and a second substrate facing each other at a predetermined interval; A first gate line and a data line formed vertically and horizontally on the first substrate to define a pixel area; A second gate line stacked on the first gate line and having a narrower width than the second gate line; A thin film transistor formed of a gate electrode, a source electrode, and a drain electrode at an intersection of the first gate line and the data line; And a pixel electrode formed on the pixel region in contact with the drain electrode.

Black light leak, gate line, step

Description

Liquid Crystal Display Device and method for fabricating the same

1 is an exploded perspective view showing a part of a typical TN liquid crystal display device

2 is an enlarged plan view illustrating a unit pixel of a lower substrate of a conventional LCD.

3A and 3B are structural cross-sectional views of a liquid crystal display according to the prior art, taken along lines II ′ and II-II ′ of FIG. 2.

4 is an enlarged plan view illustrating unit pixels of a lower substrate of a liquid crystal display according to a first exemplary embodiment of the present invention;

FIG. 5 is a cross-sectional view illustrating a liquid crystal display device according to the related art, taken along line III-III ′ and IV-IV ′ of FIG. 4; FIG.

6 is an enlarged plan view illustrating a unit pixel of a lower substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a liquid crystal display according to the related art, taken along lines V-V ′ and VI-VI ′ of FIG. 6.

8 is an enlarged plan view illustrating a unit pixel of a lower substrate of a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 9 is a cross-sectional view of a liquid crystal display according to the related art, taken along lines VII- ′ ′ and VIII- ′ of FIG. 8;

Explanation of symbols on the main parts of the drawings

40: lower substrate 41: first gate line, gate line

41a: first gate electrode and gate electrode

41b: second gate line 41c: second gate electrode

42: gate insulating film 42a, 46a: first contact hole

43: active layer 43a: ohmic contact layer

44: data wiring 44a: source electrode

44b: drain electrodes 44c and 47a: gate pattern

45: protective film 46: contact hole, second contact hole

47: pixel electrode 50: upper substrate

51: black matrix layer 52: color filter layer

53: common electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of manufacturing the same, which are suitable for preventing light leakage from being generated when the light is turned off due to a step in the upper and lower boundary regions of the gate line.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and vacuum fluorescent (VFD) have been developed. Various flat panel display devices have been studied, and some of them are already used as display devices in various devices.

Among them, the LCD is the most widely used in place of a CRT (Cathode Ray Tube) for the purpose of a portable image display device because of its excellent image quality, light weight, thinness and low power consumption. A television for receiving and displaying a broadcast signal, and a monitor for a computer.

As described above, although various technical advances have been made in order for the liquid crystal display device to serve as a screen display device in various fields, the task of improving the image quality as the screen display device has many advantages and disadvantages.

Therefore, in order for a liquid crystal display device to be used in various parts as a general screen display device, development of high quality images such as high definition, high brightness, and large area is maintained while maintaining the characteristics of light weight, thinness, and low power consumption. It can be said.

Such a liquid crystal display device may be broadly divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second glass substrates having a space and are bonded to each other; It consists of a liquid crystal layer injected between the said 1st, 2nd glass substrate.

The first glass substrate (TFT array substrate) may include a plurality of gate lines arranged in one direction at a predetermined interval, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, and A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing each gate line and data line, and a plurality of thin films that transmit signals of the data line to each pixel electrode by being switched by signals of the gate line The transistor is formed.

The second glass substrate (color filter substrate) includes a black matrix layer for blocking light in portions other than the pixel region, an R, G, B color filter layer for expressing color colors, and a common electrode for implementing an image. Is formed. Of course, the common electrode is formed on the first glass substrate in the transverse electric field type liquid crystal display device.

The first and second glass substrates are bonded by a sealing material having a predetermined space by a spacer and having a liquid crystal injection hole, and a liquid crystal is injected between the two substrates.

In this case, in the liquid crystal injection method, the liquid crystal is injected between the two substrates by osmotic pressure when the liquid crystal injection hole is immersed in the liquid crystal container by maintaining the vacuum state between the two substrates bonded by the reality. When the liquid crystal is injected as described above, the liquid crystal injection hole is sealed with a sealing material.

On the other hand, the driving principle of the liquid crystal display device as described above uses the optical anisotropy and polarization of the liquid crystal.

Since the liquid crystal is thin and long in structure, the liquid crystal has a direction in the arrangement of the molecules, and the direction of the molecular array can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light polarized by optical anisotropy may be arbitrarily modulated to express image information.

Such liquid crystals may be classified into positive liquid crystals having a positive dielectric anisotropy and negative liquid crystals having a negative dielectric anisotropy according to an electrical specific classification, and liquid crystal molecules having a positive dielectric anisotropy are long axes of liquid crystal molecules in a direction in which electric fields are applied. The liquid crystal molecules arranged in parallel and having negative dielectric anisotropy are arranged perpendicularly to the direction in which the electric field is applied and the major axis of the liquid crystal molecules.

1 is an exploded perspective view illustrating a part of a general TN liquid crystal display device.

As shown in FIG. 1, the lower substrate 1 and the upper substrate 2 bonded to each other with a predetermined space, and the liquid crystal layer 3 injected between the lower substrate 1 and the upper substrate 2 are composed of. It is.

More specifically, the lower substrate 1 has a plurality of gate lines 4 arranged in one direction at regular intervals to define the pixel region P, and in a direction perpendicular to the gate lines 4. A plurality of data lines 5 are arranged at regular intervals, and a pixel electrode 6 is formed in each pixel region P where the gate line 4 and the data line 5 intersect, and each gate line The thin film transistor T is formed at the portion where (4) and the data line 5 intersect.

The upper substrate 2 may include a black matrix layer 7 for blocking light in portions other than the pixel region P, an R, G, B color filter layer 8 for expressing color colors, The common electrode 9 for forming an image is formed.

The thin film transistor T may include a gate electrode protruding from the gate line 4, a gate insulating film (not shown) formed on the front surface, an active layer formed on the gate insulating film above the gate electrode, and the data. And a source electrode protruding from the line 5 and a drain electrode to face the source electrode.

The pixel electrode 6 uses a transparent conductive metal having a relatively high light transmittance, such as indium-tin-oxide (ITO).

In the liquid crystal display device configured as described above, the liquid crystal layer 3 positioned on the pixel electrode 6 is aligned by a signal applied from the thin film transistor T, and the liquid crystal layer 3 is aligned with the alignment degree of the liquid crystal layer 3. Accordingly, the image can be expressed by controlling the amount of light passing through the liquid crystal layer 3.

As described above, the liquid crystal panel drives the liquid crystal by an electric field applied up and down, and has excellent characteristics such as transmittance and aperture ratio, and the common electrode 9 of the upper substrate 2 serves as a ground to discharge static electricity. It is possible to prevent the destruction of the liquid crystal cell.

Hereinafter, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

2 is an enlarged plan view illustrating a unit pixel of a lower substrate of a conventional liquid crystal display, and FIGS. 3A and 3B show a structure of a liquid crystal display according to the prior art, taken along lines II ′ and II ′ of FIG. 2. It is a cross section.

As shown in FIGS. 2, 3A, and 3B, the liquid crystal display according to the related art is formed on the transparent lower substrate 20 vertically and horizontally so as to define the pixel area and the gate line 21 and the data line 24. A gate electrode 21a protruding from one side of the gate line 21, a gate insulating film 22 formed of a material such as SiNx or SiOx on the entire surface of the lower substrate 20 including the gate electrode 21a, and And an active layer 23 formed in an island shape on the gate insulating layer 22 on the gate electrode 21a and protruding from the data line 24 and overlapping an upper portion of one side of the active layer 23. The contact hole 26 is exposed to expose the source electrode 24a, the drain electrode 24b spaced apart from the source electrode 24a at a predetermined interval, and overlapped on the other side of the active layer 23, and the drain electrode 24b. Have a uniform thickness on the front of the lower substrate 20 to have a mold It is composed of a protective film 25 and the pixel electrode 27 formed on the pixel area such that the contact and the drain electrode (24b) via the contact hole 26.

Reference numeral 23a denotes an ohmic contact layer, 30 an upper substrate, 31 a black matrix layer, 32 a color filter layer, and 33 a common electrode.

The liquid crystal display according to the prior art has the following problems.

The pixel electrode 27 formed in the left and right pixel areas around the data line 24 does not form a large step with the passivation layer 25 formed between the data line 24 and the pixel electrode 27.

In the conventional LCD configured as described above, as shown in FIG. 3B, in the upper and lower boundary regions of the gate line 21, the thickness of the liquid crystal display device is equal to the thickness of 'T1' by bending according to the thickness of the gate line 21. A step occurs.

When the step T1 occurs as described above, when the screen is turned off (not in the black state), the liquid crystal adjacent to the gate line 21 is distorted, causing light leakage. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device suitable for preventing light leakage from occurring when the light is turned off due to a step in the upper and lower boundary regions of a gate line, and a manufacture thereof. To provide a method.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes: a first substrate and a second substrate facing each other at a predetermined interval; A first gate line and a data line formed vertically and horizontally on the first substrate to define a pixel area; A second gate line stacked on the first gate line and having a narrower width than the second gate line; A thin film transistor formed of a gate electrode, a source electrode, and a drain electrode at an intersection of the first gate line and the data line; And a pixel electrode formed on the pixel region in contact with the drain electrode.

According to another exemplary embodiment of the present invention, a liquid crystal display device includes: a first substrate and a second substrate facing each other at a predetermined interval; Gate lines and data lines formed vertically and horizontally on the first substrate to define pixel regions; A thin film transistor formed of a gate electrode, a source electrode, and a drain electrode at an intersection of the gate line and the data line; A gate pattern formed on the upper portion of the region of the gate line so as to be in contact with the gate line; It is characterized in that it comprises a pixel electrode formed on the pixel region in contact with the drain electrode.

A gate insulating layer having a first contact hole is further provided on the gate line to expose the gate line.

A passivation layer including a second contact hole is further disposed on the thin film transistor so that the drain electrode is exposed.

The gate pattern is formed on the same layer as the data line.

According to still another embodiment of the present invention, a liquid crystal display device includes: a first substrate and a second substrate facing each other at a predetermined interval; Gate lines and data lines formed vertically and horizontally on the first substrate to define pixel regions; A thin film transistor formed of a gate electrode, a source electrode, and a drain electrode at an intersection of the gate line and the data line; A pixel electrode formed on the pixel region in contact with the drain electrode; The gate pattern includes a gate pattern formed on the upper portion of the gate line so as to contact the gate line.

A passivation layer is further provided with first and second contact holes to expose the gate line and the drain electrode.

The gate pattern is formed on the same layer as the pixel electrode.

Next, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention includes the steps of forming a first gate line having a gate electrode on a substrate; Forming a second gate line to be stacked on the first gate line with a width narrower than this; Forming a gate insulating film on the substrate including the first and second gate lines; Forming an active layer on the gate electrode; Forming a data line intersecting with the first gate line to define a pixel area; Forming a source electrode and a drain electrode to overlap one side and the other side of the active layer; And forming a pixel electrode in the pixel region.

In addition, a method of manufacturing a liquid crystal display device according to another embodiment of the present invention, forming a gate line having a gate electrode on the substrate; Forming a gate insulating film having a first contact hole in one region of the gate line; Forming an active layer on the gate electrode; Forming a data line intersecting with the gate line to define a pixel area; Forming a source electrode and a drain electrode to overlap one side and the other side of the active layer; Forming a gate pattern having a narrower width on one region of the gate line to contact the gate line through the first contact hole; And forming a pixel electrode in the pixel region.

The gate pattern is formed simultaneously with the data line.

The gate pattern is arranged in the same direction as the gate line.

Next, a method of manufacturing a liquid crystal display device according to another embodiment of the present invention, forming a gate line having a gate electrode on the substrate; Forming a gate insulating film on the gate line; Forming an active layer on the gate electrode; Forming a data line intersecting with the gate line to define a pixel area; Forming a source electrode and a drain electrode to overlap one side and the other side of the active layer; Forming a passivation layer having first and second contact holes on the gate line and the drain electrode; Forming a pixel electrode in the pixel area to contact the drain electrode through the second contact hole; And forming a gate pattern having a narrower width on one region of the gate line to contact the gate line through the first contact hole.

The gate pattern is formed simultaneously with the pixel electrode.

The gate pattern is arranged in the same direction as the gate line.

Hereinafter, a liquid crystal display and a manufacturing method thereof according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First Embodiment

First, a liquid crystal display and a method of manufacturing the same according to the first embodiment of the present invention will be described.

4 is an enlarged plan view illustrating a unit pixel of a lower substrate of a liquid crystal display according to a first embodiment of the present invention, and FIG. 5 is a liquid crystal according to the prior art, taken along lines III-III ′ and IV-IV ′ of FIG. 4. A structure cross section showing a display device.

In the liquid crystal display according to the first exemplary embodiment of the present invention, as shown in FIGS. 4 and 5, the first gate line 41 is formed vertically and horizontally on the transparent lower substrate 40 to define the pixel region. And a narrower portion above the data line 44, the first gate electrode 41a protruding from one side of the first gate line 41, and the first gate line 41 and the first gate electrode 41a. SiNx or SiOx may be formed on the entire surface of the lower substrate 40 including the second gate line 41b and the second gate electrode 41c and the first and second gate electrodes 41a and 41c. A gate insulating layer 42 formed of a material, an active layer 43 formed in an island shape on the gate insulating layer 42 on the first and second gate electrodes 41a and 41c, and the data line 44. Source electrode 44a protruding from the upper surface of the active layer 43 and overlapping the upper portion of the active layer 43 A front surface of the lower substrate 40 to have a drain electrode 44b spaced apart from the switch electrode 44a by a predetermined interval and overlapping the other side of the active layer 43, and a contact hole 46 to expose the drain electrode 44b. And a pixel electrode 47 formed on the pixel region to be in contact with the drain electrode 44b through the contact hole 46.

Reference numeral 43a is an ohmic contact layer, 50 is an upper substrate, 51 is a black matrix layer, 52 is a color filter layer, and 53 is a common electrode.

As described above, the overall thicknesses of the first and second gate lines 41 and 41b are formed in the same manner as in the prior art, and the first gate line 41 is configured to have the maximum width that can be formed, and the first When the second gate line 41b having a narrower width is stacked on one region or the entire region of the gate line 41, as shown in FIG. 5, the image of the first and second gate lines 41 and 41b is formed. The step T2 at the lower boundary area is reduced.

As described above, when the step difference in the upper and lower boundary regions of the gate line is reduced, it is possible to prevent the generation of light leakage due to the liquid crystal distortion in the black state. That is, the black light leakage can be improved by reducing the step that causes light leakage in the black state.

In addition, even if the gate line and the gate electrode are formed in a double layer, if the entire thickness is configured in the same manner as before, the problem of increasing the resistance does not occur.

Next, a manufacturing method of the liquid crystal display device according to the first embodiment of the present invention having the above configuration will be described.

In the method of manufacturing the liquid crystal display according to the first embodiment of the present invention, as shown in FIGS. 4 and 5, the first conductive metal is deposited on the transparent lower substrate 40, and a photo and etching process is used. The conductive metal is patterned to form a first gate line 41 having one direction and a first gate electrode 41a protruding from the first gate line 41 in one direction. In this case, the first gate line 41 is formed wide to have the maximum width that can be formed.

Thereafter, a second conductive metal is deposited on the entire surface including the first gate line 41, and the second conductive metal is patterned by using a photo and etching process, thereby forming the first gate line 41 and the first gate electrode ( The second gate line 41b and the second gate electrode 41c are formed on the upper portion of the region or the upper region of the region 41a so as to have a narrower width.

Thereafter, the gate insulating layer 42 is formed on the entire surface of the lower substrate 40 on which the first and second gate electrodes 41a and 41c are formed.

The gate insulating layer 42 may use a silicon nitride layer (SiNx) or a silicon oxide layer (SiO ₂ ).

Thereafter, a semiconductor layer (amorphous silicon + impurity amorphous silicon) is formed on the gate insulating film 42.

Subsequently, the semiconductor layer is patterned by photo and etching processes to form an active layer 43 having an island shape on the first and second gate electrodes 41a and 41c.

Thereafter, a conductive metal is deposited on the entire surface of the lower substrate 40 on which the active layer 43 is formed, and patterned through photo and etching processes to cross the first and second gate lines 41 and 41b to form a pixel region. And a source pad (not shown) having a predetermined area at an end thereof, a source electrode 44a protruding from the data line 44 in one direction, and a source electrode. A drain electrode 44b isolated from 44a by a predetermined distance is formed.

When the source electrode 44a and the drain electrode 44b are formed, an amorphous silicon layer over the channel region is excessively etched to form a gap between the source electrode 44a and the active layer 43 and between the drain electrode 44b and the active layer. The ohmic contact layer 43a is formed in between.

Next, a passivation layer 45 is formed on the entire surface of the lower substrate 40 on which the data line 44 is formed.

The passivation layer 45 may be formed using at least one of acryl, polyimide, benzocyclobutene (BCB), oxide film, and nitride film.

Subsequently, the protective layer 45 is etched to expose one region of the drain electrode 44b to form a contact hole 46.

Thereafter, a transparent conductive film is deposited on the entire lower substrate 40, and then the transparent conductive film is patterned by photo and etching processes to form the pixel electrode 47 in the pixel region. In this case, the pixel electrode 47 is connected to the drain electrode 44b through the contact hole 46.

In the first embodiment, a TN mode liquid crystal display device is shown and illustrated. This is merely an example and is not intended to limit the present invention. The second gate line may be stacked to have a narrower width over the entire first gate line area. It is characterized by the fact that it can be applied to a liquid crystal display device of a transverse electric field system (IPS), VA, or other modes.

In addition, the manufacturing method is applied to the liquid crystal display device formed by using the conventional five masks, it is also applicable to the liquid crystal display device formed by the general three, four masks.

Second Embodiment

Next, a liquid crystal display and a manufacturing method thereof according to a second embodiment of the present invention will be described.

6 and 7, the liquid crystal display according to the second exemplary embodiment of the present invention has a gate line 41 and a data line formed vertically and horizontally on a transparent lower substrate 40 to define pixel regions. A gate insulating film formed of a material such as SiNx or SiOx on the entire surface of the lower substrate 40 including the gate electrode 41a protruding from one side of the gate line 41, and the gate electrode 41a. 42, an island shape on the first contact hole 42a formed in the gate insulating layer 42 so that a region of the gate line 41 is exposed, and the gate insulating layer 42 on the gate electrode 41a. An active layer 43 formed from the active layer 43, a source electrode 44a protruding from the data line 44, and overlapping an upper portion of one side of the active layer 43, and spaced apart from the source electrode 44a at a predetermined interval. A drain electrode 44b overlapping the other side of the layer 43, On the front surface of the lower substrate 40 to have a gate pattern 44c formed to have a narrower width above the one region of the gate line 41 and the second contact hole 46 to expose the drain electrode 44b. And a pixel electrode 47 formed on the pixel region to be in contact with the drain electrode 44b through the second contact hole 46.

Reference numeral 43a is an ohmic contact layer, 50 is an upper substrate, 51 is a black matrix layer, 52 is a color filter layer, and 53 is a common electrode.

The gate pattern 44c is to reduce the step difference in the boundary region of the gate line 41 and is formed in the same direction as the gate line 41.

As described above, the entire thicknesses of the gate line 41 and the gate pattern are formed in the same manner as in the prior art, and the gate line 41 is configured to have the maximum width that can be formed, and is formed on the same layer as the data line 44. If the gate pattern 44c having a narrower width is formed on one region of the gate line 41 in the above, the step T3 in the upper and lower boundary regions of the gate line 41 is reduced as shown in FIG. 7. do. At this time, the step T3 is a step corresponding to the thickness of the gate line 41, which is smaller than the step of the boundary region of the conventional gate line.

As described above, when the level difference in the upper and lower boundary regions of the gate line is reduced, the liquid crystal is distorted by the level difference in the black state, thereby preventing light leakage. That is, the black light leakage can be improved by reducing the step that causes light leakage in the black state.

In addition, the gate pattern 44c is formed on one region to be in contact with the gate line 41. The thickness of the gate pattern 44c is similar to that of the conventional gate line, thereby preventing a problem of increasing resistance.

Next, a manufacturing method of the liquid crystal display device according to the second embodiment of the present invention having the above configuration will be described.

In the method of manufacturing the liquid crystal display according to the second exemplary embodiment of the present invention, as illustrated in FIGS. 6 and 7, the first conductive metal is deposited on the transparent lower substrate 40, and a photo and etching process is used. The conductive metal is patterned to form a gate line 41 having one direction and a gate electrode 41a protruding from the gate line 41 in one direction. At this time, the gate line 41 is formed wide to have the maximum width that can be formed.

Thereafter, the gate insulating layer 42 is formed on the entire surface of the lower substrate 40 on which the gate electrode 41a is formed.

Next, a first contact hole 42a is formed in the gate insulating layer 42 so that one region of the gate line 41 is exposed.

The gate insulating layer 42 may use a silicon nitride layer (SiNx) or a silicon oxide layer (SiO ₂ ).

Thereafter, a semiconductor layer (amorphous silicon + impurity amorphous silicon) is formed on the gate insulating film 42.

Subsequently, the semiconductor layer is patterned by photo and etching processes to form an active layer 43 having an island shape on the gate electrode 41a.

Thereafter, a conductive metal is deposited on the entire surface of the lower substrate 40 on which the active layer 43 is formed, and patterned through photo and etching processes to cross the gate line 41 to define a pixel region 44. ) And a source electrode 44a protruding in one direction from the data line 44, and a drain electrode 44b separated from the source electrode 44a by a predetermined distance.

When the source electrode 44a and the drain electrode 44b are formed, the gate pattern 44c is formed on the region of the gate line 41 to have a narrower width than the source electrode 44a and the drain electrode 44b. In this case, the gate pattern 44c is in contact with the gate line 41 through the first contact hole 42a. The gate pattern 44c is to reduce the level difference between the upper and lower boundary regions of the gate line 41 and may be patterned in the same direction as the gate line 41.

In addition, when the source electrode 44a and the drain electrode 44b are formed, an amorphous silicon layer over the channel region is etched excessively, between the source electrode 44a and the active layer 43 and between the drain electrode 44b and the drain electrode 44b. An ohmic contact layer 43a is formed between the active layers.

Next, the passivation layer 45 is formed on the entire surface of the lower substrate 40 on which the data line 44 is formed.

The passivation layer 45 may be formed using at least one of acryl, polyimide, benzocyclobutene (BCB), oxide film, and nitride film.

Next, the passivation layer 45 is etched to expose one region of the drain electrode 44b to form a second contact hole 46.

Thereafter, a transparent conductive film is deposited on the entire lower substrate 40, and then the transparent conductive film is patterned by photo and etching processes to form the pixel electrode 47 in the pixel region. In this case, the pixel electrode 47 is connected to the drain electrode 44b through the second contact hole 46.

In the second embodiment, a TN mode liquid crystal display device is shown and illustrated. This is merely an example, and is not intended to limit the present invention. The gate pattern is formed to have a narrower width than that of the gate pattern. The gate pattern can be applied to a liquid crystal display device having an electric field system (IPS), a VA mode, or another mode.

In addition, the manufacturing method is applied to the liquid crystal display device formed by using the conventional five masks, it is also applicable to the liquid crystal display device formed by the general three, four masks.

Third Embodiment

Next, a liquid crystal display and a manufacturing method thereof according to a third embodiment of the present invention will be described.

In the liquid crystal display according to the third exemplary embodiment of the present invention, as shown in FIGS. 8 and 9, the gate line 41 and the data are formed vertically and horizontally on the transparent lower substrate 40 to define the pixel region. A gate insulating layer formed of a material such as SiNx or SiOx on the entire surface of the line 44, the gate electrode 41a protruding from one side of the gate line 41, and the lower substrate 40 including the gate electrode 41a. (42), an active layer (43) formed in an island shape on the gate insulating film (42) above the gate electrode (41a), and protruding from the data line (44) and one side of the active layer (43). On the source electrode 44a overlapping the upper portion, the drain electrode 44b spaced apart from the source electrode 44a at a predetermined interval, and overlapping the other side of the active layer 43, and on one region of the gate line 41. The first contact hole 46a has a second contact hole in the drain electrode 44b. A protective layer 45 formed on the front surface of the lower substrate 40 to have a 46b and a narrower portion above the one region of the gate line 41 to be in contact with the gate line 41 through the first contact hole 46a. A gate pattern 47a having a width and a pixel electrode 47 formed on the pixel region to be in contact with the drain electrode 44b through the second contact hole 46b.

In the above, the gate line 41 is formed wide to have the maximum width that can be formed.

In addition, the gate pattern 47a is made of the same material as the pixel electrode 47.

 The gate pattern 47a is to reduce the level difference between the upper and lower boundary regions of the gate line 41 and is formed in the same direction on the gate line 41.

Reference numeral 43a is an ohmic contact layer, 50 is an upper substrate, 51 is a black matrix layer, 52 is a color filter layer, and 53 is a common electrode.

The thickness of the sum of the gate line 41 and the gate pattern 47a is similar to that of the conventional gate line, so that a resistance problem does not occur. It is possible to improve the black light leakage caused by the step at the gate line boundary without increasing the.

The pixel electrode 47 is formed of a transparent conductive film. However, when applied to the transverse electric field method (IPS), the pixel electrode 47 may be formed of a single Ti layer having low resistance or a double layer of Mo / Ti.

Next, in the method of manufacturing the liquid crystal display device according to the third embodiment of the present invention, as shown in FIGS. 8 and 9, the first conductive metal is deposited on the transparent lower substrate 40, and photo and etching are performed. The conductive metal is patterned using a process to form a gate line 41 having one direction and a gate electrode 41a protruding from the gate line 41 in one direction. In the above, the gate line 41 is formed wide to have the maximum width that can be formed.

Thereafter, the gate insulating layer 42 is formed on the entire surface of the lower substrate 40 on which the gate electrode 41a is formed.

The gate insulating layer 42 may be formed using a silicon nitride layer (SiNx) or a silicon oxide layer (SiO ₂ ).

Thereafter, a semiconductor layer (amorphous silicon + impurity amorphous silicon) is formed on the gate insulating film 42.

Subsequently, the semiconductor layer is patterned by photo and etching processes to form an active layer 43 having an island shape on the gate electrode 41a.

Thereafter, a conductive metal is deposited on the entire surface of the lower substrate 40 on which the active layer 43 is formed, and patterned through photo and etching processes to cross the gate line 41 to define a pixel region 44. ) And a source electrode 44a protruding in one direction from the data line 44, and a drain electrode 44b separated from the source electrode 44a by a predetermined distance.

When the source electrode 44a and the drain electrode 44b are formed, an amorphous silicon layer over the channel region is excessively etched to form a gap between the source electrode 44a and the active layer 43 and between the drain electrode 44b and the active layer. The ohmic contact layer 43a is formed in between.

Next, a passivation layer 45 is formed on the entire surface of the lower substrate 40 on which the data line 44 is formed.

The passivation layer 45 may be formed using at least one of acryl, polyimide, benzocyclobutene (BCB), oxide film, and nitride film.

Subsequently, the passivation layer 45 is etched to expose one region of the gate line 41 to form a first contact hole 46a, and the passivation layer 45 to expose one region of the drain electrode 44b. Is etched to form a second contact hole 46b.

Thereafter, a transparent conductive film is deposited on the entire lower substrate 40, and then the transparent conductive film is patterned by photo and etching processes to form the pixel electrode 47 in the pixel region. In this case, the pixel electrode 47 is connected to the drain electrode 44b through the second contact hole 46b.

In addition, when the pixel electrode 47 is formed, the gate pattern 47a is formed together to have a narrower width above the one region of the gate line 41. In this case, the gate pattern 47a is in contact with the gate line 41 through the first contact hole 46a. The gate pattern 47a is to reduce the step difference between the upper and lower boundary regions of the gate line 41, and the gate pattern 47a may be formed in the same direction on the gate line 41.

As described above, since the first contact hole 46a and the gate pattern 47a are formed when the second contact hole 46b and the pixel electrode 47 are formed, an additional mask is not required.

In addition, the thickness of the sum of the gate line 41 and the gate pattern 47a is similar to the thickness of the conventional gate line, so that a resistance problem does not occur. It is possible to improve the black light leakage due to the step difference at the gate line boundary portion without increasing the resistance.

The pixel electrode 47 is formed of a transparent conductive film. However, when applied to the transverse electric field method (IPS), the pixel electrode 47 may be formed of a single Ti layer having low resistance or a double layer of Mo / Ti.

In the third embodiment, a TN mode liquid crystal display device is shown and shown. This is merely an example, and is not intended to limit the present invention. The TN mode liquid crystal display device is not limited to the present invention. The gate pattern is formed so as to have a narrow width, and it can be applied to a liquid crystal display device having an electric field system (IPS), a VA mode, or another mode.

In addition, the manufacturing method is applied to the liquid crystal display device formed by using the conventional five masks, it is also applicable to the liquid crystal display device formed by the general three, four masks.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention.

Accordingly, the technical scope of the present invention should not be limited to the contents described in the above embodiments, but should be determined by the claims.

The liquid crystal display according to the present invention as described above and a manufacturing method thereof have the following effects.

First, by forming the second gate line with a narrower width on the first gate line, the step difference in the upper and lower boundary regions of the gate line can be reduced, thereby improving light leakage caused by the liquid crystal distortion in the black state. have.

Second, when forming the data line, by forming a gate pattern having a narrower width above the one region of the gate line, the step difference in the upper and lower boundary regions of the gate line is reduced, so that the liquid crystal is warped in the black state Can improve light leakage.

Third, when the pixel electrode is formed, the gate pattern is formed on the upper portion of the gate line so as to have a narrower width, thereby reducing the step difference between the upper and lower boundary regions of the gate line. The light leakage caused by the phenomenon can be improved.

Fourth, since the thickness of the sum of the first and second gate lines and the thickness of the sum of the gate lines and the gate pattern are formed to be similar to those of the conventional gate line, the problem of increasing the gate resistance does not occur.

Claims (16)

delete A first substrate and a second substrate facing each other at a predetermined interval; A gate line formed in one direction on the first substrate; A gate electrode protruding from one side of the gate line on the first substrate; A gate insulating film formed on an entire surface of the first substrate including the gate line and the gate electrode; A data line formed on the gate insulating layer in another direction crossing the gate line to define a pixel region; A source electrode protruding from one side of the data line on the gate insulating film; A drain electrode formed on the gate insulating film and spaced apart from the source electrode; A gate pattern formed on the gate insulating layer to overlap at least a portion of the gate line and have a narrower width than the gate line; A passivation layer formed on an entire surface of the gate insulating layer including the data line, the source electrode, the drain electrode, and the gate pattern; And a pixel electrode formed on the passivation layer corresponding to the pixel area. The method of claim 2, A first contact hole penetrating the gate insulating layer to expose at least a portion of the gate line; And the gate pattern is in contact with the gate line through the first contact hole. The method of claim 2, A second contact hole penetrating the passivation layer to expose at least a portion of the drain electrode; And the pixel electrode is in contact with the drain electrode through the second contact hole. The method of claim 2, And the gate pattern is formed on the same layer as the data line. A first substrate and a second substrate facing each other at a predetermined interval; A gate line formed in one direction on the first substrate; A gate electrode protruding from one side of the gate line on the first substrate; A gate insulating film formed on an entire surface of the first substrate including the gate line and the gate electrode; A data line formed on the gate insulating layer in another direction crossing the gate line to define a pixel region; A source electrode protruding from one side of the data line on the gate insulating film; A drain electrode formed on the gate insulating film and spaced apart from the source electrode; A passivation layer formed on an entire surface of the gate insulating layer including the data line, the source electrode, and the drain electrode; A pixel electrode formed on the passivation layer corresponding to the pixel area; And a gate pattern formed on the passivation layer to overlap at least a portion of the gate line and have a narrower width than the gate line. The method of claim 6, A first contact hole penetrating the gate insulating layer and the passivation layer to expose at least a portion of the gate line; And A second contact hole penetrating the passivation layer to expose at least a portion of the drain electrode; The gate pattern is in contact with the gate line through the first contact hole, And the pixel electrode is in contact with the drain electrode through the second contact hole. The method of claim 6, And the gate pattern is formed on the same layer as the pixel electrode. delete Forming a gate line having a gate electrode on the substrate; Forming a gate insulating film having a first contact hole in one region of the gate line; Forming an active layer on the gate electrode; Forming a data line intersecting with the gate line to define a pixel area; Forming a source electrode and a drain electrode to overlap one side and the other side of the active layer; Forming a gate pattern having a narrower width on one region of the gate line to contact the gate line through the first contact hole; And forming a pixel electrode in the pixel region. 11. The method of claim 10, And the gate pattern is formed at the same time as the data line. 11. The method of claim 10, And the gate pattern is arranged in the same direction as the gate line. Forming a gate line having a gate electrode on the substrate; Forming a gate insulating film on the gate line; Forming an active layer on the gate electrode; Forming a data line intersecting with the gate line to define a pixel area; Forming a source electrode and a drain electrode to overlap one side and the other side of the active layer; Forming a passivation layer having first and second contact holes on the gate line and the drain electrode; Forming a pixel electrode in the pixel area to contact the drain electrode through the second contact hole; And forming a gate pattern having a narrower width on one region of the gate line to contact the gate line through the first contact hole. The method of claim 13, And the gate pattern is formed at the same time as the pixel electrode. The method of claim 13, And the gate pattern is arranged in the same direction as the gate line. 7. The method according to claim 2 or 6, And the gate pattern is arranged in the same direction as the gate line.

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