KR100943469B1 - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

The present invention provides a liquid crystal display device and a method of manufacturing the same, which can solve the reduction of the aperture ratio when the upper and lower substrates are bonded, form a light shielding film of the lower substrate, and increase the economic efficiency and facilitate the process application. The liquid crystal display device includes: a first substrate and a second substrate facing each other at predetermined intervals; Gate lines and data lines formed vertically and horizontally on the first substrate to define pixel regions; A first common wiring arranged in the gate line direction; A thin film transistor formed at an intersection of the gate line and the data line; An interlayer insulating film formed on the entire surface of the first substrate including the thin film transistor; A color filter layer formed in the pixel region; A planarization film formed on the first substrate including the common wiring and the common electrode; A light shielding film formed on the planarization film above the channel region of the thin film transistor; A second common line and a common electrode overlapping the gate line, the data line, the upper portion of the thin film transistor, and the light blocking layer and formed in one direction in the pixel area; And a pixel electrode contacted with the drain electrode of the thin film transistor and formed at a predetermined interval between the common electrodes.

Light shielding film, metal, common wiring, common electrode, aperture ratio, black matrix layer,

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

1 is an exploded perspective view showing a part of a typical TN liquid crystal display device

Figure 2 is a schematic cross-sectional view showing a liquid crystal display device of a typical transverse electric field (IPS)

3A to 3B are diagrams illustrating phase transitions of liquid crystals when voltage on / off is performed in IPS mode.

4A and 4B are perspective views showing the operation of the IPS mode LCD in the off and on states, respectively.

5 is a plan view of a liquid crystal display according to the related art.

FIG. 6 is a cross-sectional view taken along line II ′ and II ′ of FIG. 5.

7 is a plan view of a liquid crystal display according to another conventional technology

8 is a cross-sectional view taken along line III-III ′ and IV-IV ′ of FIG. 6.

9 is a plan view of a liquid crystal display according to another conventional technology

FIG. 10 is a cross-sectional view taken along line V-V ′ and VI-VI ′ of FIG. 9;

11 is a plan view of a liquid crystal display according to a first embodiment of the present invention.

12 is a cross-sectional view taken along line XVIII 'and XVIII-X' of FIG.                 

13A to 13C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention.

14 is a plan view of a liquid crystal display according to a second exemplary embodiment of the present invention.

15 is a cross-sectional view taken along line VII-VII 'and VIII-VII' of FIG.

16A through 16C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a second embodiment of the present invention.

17 is a plan view of a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 18 is a cross-sectional view taken along line II-XI 'and XII-XII' of FIG. 17; FIG.

19A to 19C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a third embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

110, 180: upper substrate 120, 190: lower substrate

121, 191: gate lines 121a, 191a: gate electrodes

121b and 191b: first common wiring 122 and 192: gate insulating film

123 and 193 active layer 124 and 194 data line

124a, 194a: source electrode 124b, 194b: drain electrode

124c and 194c: Storage electrodes 125 and 195: Interlayer insulating film

126, 196: color filter layer 127a, 197a: first contact hole

127b and 197b: second contact holes 128 and 198: planarization film

129 and 199: light shielding films 130a and 200a: second common wiring                 

130b: common electrode 130c, 200b: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method for manufacturing the same, which are suitable for solving the reduction of the aperture ratio due to the upper and lower plate bonding margins.

As the information society develops, the demand for display devices is increasing in various forms.In recent years, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and vacuum fluorescent display (VFD) have been developed. Various flat panel display devices have been studied, and some are already used as display devices in various devices.

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for the use of mobile image display device because of the excellent image quality, light weight, thinness, and low power consumption, and mobile type such as monitor of notebook computer. In addition, it is being developed in various ways, such as a television for receiving and displaying broadcast signals, and a monitor of a computer.

As described above, although various technical advances have been made in order for the liquid crystal display device to serve as a screen display device in various fields, the task of improving the image quality as the screen display device has many advantages and disadvantages.                         

Therefore, in order to use a liquid crystal display device in various parts as a general screen display device, the key to development is how much high definition images such as high definition, high brightness, and large area can be realized while maintaining the characteristics of light weight, thinness, and low power consumption. It can be said.

Such a liquid crystal display device may be broadly divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second glass substrates having a space and are bonded to each other; It consists of a liquid crystal layer injected between the said 1st, 2nd glass substrate.

The first glass substrate (TFT array substrate) may include a plurality of gate lines arranged in one direction at a predetermined interval, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, and A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing each gate line and data line, and a plurality of thin films that transmit signals of the data line to each pixel electrode by being switched by signals of the gate line The transistor is formed.

The second glass substrate (color filter substrate) includes a black matrix layer for blocking light in portions other than the pixel region, an R, G, B color filter layer for expressing color colors, and a common electrode for implementing an image. Is formed. Of course, the common electrode is formed on the first glass substrate in the transverse electric field type liquid crystal display device.

The first and second glass substrates are bonded by a sealing material having a predetermined space by a spacer and having a liquid crystal injection hole, and a liquid crystal is injected between the two substrates.

In this case, in the liquid crystal injection method, the liquid crystal is injected between the two substrates by osmotic pressure when the liquid crystal injection hole is immersed in the liquid crystal container by maintaining the vacuum state between the two substrates bonded by the reality. When the liquid crystal is injected as described above, the liquid crystal injection hole is sealed with a sealing material.

On the other hand, the driving principle of the liquid crystal display device as described above uses the optical anisotropy and polarization of the liquid crystal.

Since the liquid crystal is thin and long in structure, the liquid crystal has a direction in the arrangement of molecules, and the liquid crystal may be artificially applied to control the direction of the molecular arrangement.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light polarized by optical anisotropy may be arbitrarily modulated to express image information.

Such liquid crystals may be classified into positive liquid crystals having positive dielectric anisotropy and negative liquid crystals having negative dielectric anisotropy according to an electrical specific classification. The liquid crystal molecules arranged in parallel and having negative dielectric anisotropy are arranged perpendicularly to the direction in which the electric field is applied and the major axis of the liquid crystal molecules.

1 is an exploded perspective view illustrating a part of a general TN liquid crystal display device.

As shown in FIG. 1, the lower substrate 1 and the upper substrate 2 bonded to each other with a predetermined space, and the liquid crystal layer 3 injected between the lower substrate 1 and the upper substrate 2 are composed of. It is.

More specifically, the lower substrate 1 has a plurality of gate lines 4 arranged in one direction at regular intervals to define the pixel region P, and in a direction perpendicular to the gate lines 4. A plurality of data lines 5 are arranged at regular intervals, and a pixel electrode 6 is formed in each pixel region P where the gate line 4 and the data line 5 intersect, and each gate line The thin film transistor T is formed at the portion where (4) and the data line 5 intersect.

The upper substrate 2 includes a black matrix layer 7 for blocking light in portions other than the pixel region P, an R, G, and B color filter layer 8 for expressing color colors, and an image. The common electrode 9 is formed to implement the.

The thin film transistor T may include a gate electrode protruding from the gate line 4, a gate insulating film (not shown) formed on the front surface, an active layer formed on the gate insulating film above the gate electrode, and the data. And a source electrode protruding from the line 5 and a drain electrode to face the source electrode.

The pixel electrode 6 uses a transparent conductive metal having a relatively high light transmittance, such as indium-tin-oxide (ITO).

In the liquid crystal display device configured as described above, the liquid crystal layer 3 positioned on the pixel electrode 6 is aligned by a signal applied from the thin film transistor T, and the liquid crystal layer 3 is aligned with the alignment degree of the liquid crystal layer 3. Accordingly, the image can be expressed by controlling the amount of light passing through the liquid crystal layer 3.

As described above, the liquid crystal panel drives the liquid crystal by an electric field applied up and down, and has excellent characteristics such as transmittance and aperture ratio, and the common electrode 9 of the upper substrate 2 serves as a ground to discharge static electricity. It is possible to prevent the destruction of the liquid crystal cell.

However, the liquid crystal drive by the electric field applied up-down has a disadvantage that the viewing angle characteristics are not excellent.

Accordingly, in order to overcome the above disadvantages, a new technology, namely, a liquid crystal display device of IPS, has been proposed.

2 is a schematic cross-sectional view showing a liquid crystal display of a general IPS.

As shown in FIG. 2, the pixel electrode 12 and the common electrode 13 are formed on the lower substrate 11 on the same plane.

In addition, the liquid crystal layer 14 formed between the lower substrate 11 and the upper substrate 15 bonded to the lower substrate 11 may be disposed between the pixel electrode 12 and the common electrode 13 on the lower substrate 11. It works by electric field.

3A to 3B are diagrams illustrating phase transitions of liquid crystals when voltages are turned on and off in the IPS mode.

That is, FIG. 3A shows an off state in which no transverse electric field is applied to the pixel electrode 12 or the common electrode 13, so that the phase change of the liquid crystal layer 14 does not occur. For example, the pixel electrode 12 and the common electrode 13 are basically shifted by 45 ° in the horizontal direction.

FIG. 3B is an on state in which a transverse electric field is applied to the pixel electrode 12 and the common electrode 13, and a phase shift of the liquid crystal layer 14 occurs, and is about 45 ° compared to the off state of FIG. 3A. It can be seen that the horizontal direction of the pixel electrode 12 and the common electrode 13 and the twist direction of the liquid crystal have a twist angle.

As described above, in the liquid crystal display of the IPS, both the pixel electrode 12 and the common electrode 13 exist on the same plane.

An advantage of the transverse electric field method is that a wide viewing angle is possible.

That is, when the liquid crystal display device is viewed from the front, the liquid crystal display device may be visible in the about 70 ° direction in the up / down / left / right directions.

In addition, there is an advantage that the manufacturing process is simpler and the color shift according to the viewing angle is smaller than that of the liquid crystal display device.

However, since the common electrode 13 and the pixel electrode 12 are present on the same substrate, there is a disadvantage in that transmittance and aperture ratio due to light are reduced.

In addition, there is a disadvantage in that the response time due to the driving voltage must be improved and the cell gap is made uniform because the misalign margin of the cell gap is small.

That is, the transverse electric field type liquid crystal display device has the advantages and disadvantages as described above can be selected according to the user's use.

4A and 4B are perspective views showing the operation of the liquid crystal display of the IPS in the off state and the on state, respectively.

As shown in FIG. 4A, when no transverse electric field voltage is applied to the pixel electrode 12 or the common electrode 13, the alignment direction of the liquid crystal molecules 16 is the same as that of the initial alignment layer (not shown). Is arranged.

As shown in FIG. 4B, when the transverse electric field voltage is applied to the pixel electrode 12 and the common electrode 13, the alignment direction 16 of the liquid crystal molecules is arranged in the direction 17 to which the electric field is applied. Can be.

Hereinafter, a conventional liquid crystal display device will be described with reference to the accompanying drawings.

5 is a plan view of a liquid crystal display according to the prior art, and FIG. 6 is a cross-sectional view of the structure taken along lines II ′ and II ′ of FIG. 5.

FIG. 7 is a plan view of a liquid crystal display according to another conventional technology, and FIG. 8 is a cross-sectional view of the structure taken along line III-III ′ and IV-IV ′ of FIG. 6.

9 is a plan view of a liquid crystal display according to another conventional technology, and FIG. 10 is a cross-sectional view of the structure taken along lines VV 'and VIV' of FIG. 9.

5 and 6, the liquid crystal display according to the related art includes a gate line 61 and a data line 64 arranged vertically and horizontally on a transparent lower substrate 60 to define a pixel region, and the gate. The common wiring 61b formed in one direction in the upper and lower portions of the pixel area in a direction parallel to the line 61 and the pixel in a direction parallel to the data line 64 and integrally formed with the common wiring 61b. A plurality of common electrodes 61c formed in the region, a gate electrode 61a protruding from one side of the gate line 61, and a lower substrate 60 including the gate electrode 61a are formed on the front surface of the lower substrate 60, such as SiNx or SiOx. The gate insulating layer 62 formed of a material, the active layer 63 formed in an island shape on the gate insulating layer 62 on the gate electrode 61a, and the active layer 63 overlap each other. From the data line 64 The source electrode 64a and the drain electrode 64a which are spaced apart from the source electrode 64a and overlap the other side of the active layer 63, and extend from the drain electrode 64b to extend between the common electrode 61c. And a storage electrode 64c extending from the pixel electrode 64c and formed on the common wiring 61b.

In the above, the drain electrode 64b, the pixel electrode 64d and the storage electrode 64c are integrally formed on the same layer.

The upper substrate 50 corresponding to the lower substrate 60 having the above structure includes a black matrix layer 51 for preventing light leakage and a color filter layer of R, G, and B formed in a portion corresponding to the pixel region. It consists of 52.

In this case, the black matrix layer 51 formed on the upper substrate 50 extends between the data line 64 and the common electrode 61c arranged adjacent thereto. The data line 64, the gate line 61, The upper and lower bonding margins are widely formed in a region corresponding to the thin film transistor TFT.

Next, the liquid crystal display according to another conventional technology is arranged on the transparent lower substrate 80 vertically and horizontally as shown in FIGS. 7 and 8 to define the pixel region, the gate line 81 and the data line 84. And a common wiring 81b formed in one direction in the upper and lower portions of the pixel area in a direction parallel to the gate line 81 and integrally formed with the common wiring 81b and parallel to the data line 84. SiNx on the entire surface of the lower substrate 80 including the common electrode 81c formed in the pixel region in the direction, the gate electrode 81a protruding from one side of the gate line 81, and the gate electrode 81a. Or a gate insulating layer 82 formed of a material such as SiOx, an active layer 83 formed in an island shape on the gate insulating layer 82 on the gate electrode 81a, and the active layer 83 The data line 8 to overlap on one side A source electrode 84a protruding from 4), a drain electrode 84b spaced apart from the source electrode 84a, and overlapping the other side of the active layer 83; and an upper portion of the common wiring 81b. It is formed on the front surface of the lower substrate 80 including the storage electrode 84c and the source electrode 84a and the drain electrode 84b. The first and second contacts are respectively connected to the drain electrode 84b and the storage electrode 84c. The interlayer insulating film 85 having holes 87a and 87b and the drain electrode 84b and the storage electrode 84c are contacted through the first and second contact holes 87a and 87b and the common electrode 81c. It consists of the pixel electrode 86 formed in between.

In the above, the pixel electrode 86 is formed of a transparent conductive film.

Next, a liquid crystal display device according to another conventional technique will be described.

9 and 10, the liquid crystal display according to the related art has a gate line 101 arranged in one direction on the transparent lower substrate 100 and protrudes from one side of the gate line 101. A gate electrode 101a formed, a first common wiring 101b arranged in parallel on the same layer as the gate line 101 with the same material, and the gate electrode 101a and the first common wiring 101b. A gate insulating film 102 formed on the entire surface of the lower substrate 100, an active layer 103 formed in an island shape on the gate insulating film 102 on the gate electrode 101a, and the gate line 101. ), A data line 104 intersecting with each other to define a pixel region, a source electrode 104a protruding from the data line 104 and overlapping an upper portion of the active layer 103, and the source electrode 104a. ) And the other side of the active layer 103 spaced apart from the predetermined interval A lower substrate including a drain electrode 104b overlapping the first electrode, a storage electrode 104c formed on the first common wiring 101b, a data line 104, a source electrode 104a, and a drain electrode 104b. The planarization film 105 formed on the entire surface of the substrate 100, the contact hole 106 formed on the planarization film 105 so that one region of the drain electrode 104b is exposed, the source electrode 104a and the drain electrode. A second common wiring 107a formed on the planarization film 105 of the lower substrate 100 including the 104b, and an integral portion of the second common wiring 107a, and an upper portion of the data line 104; The common electrode 107b formed in one region of the pixel region, the pixel electrode 107c contacted with the drain electrode 104b through the contact hole 106 and spaced apart from the common electrode 107b by a predetermined interval. It consists of.

The upper substrate 90 corresponding to the lower substrate 100 having the above structure includes a black matrix layer 91 for preventing light leakage and a color filter layer of R, G, and B formed in a portion corresponding to the pixel region. It consists of 92.

In this case, the black matrix layer 91 formed on the upper substrate 90 is widely formed in the region corresponding to the thin film transistor TFT in consideration of the upper and lower bonding margins.

Although not shown in the drawing, the upper and lower substrates are bonded by a sealing material having a liquid crystal injection hole, wherein the sealing material is in contact with the organic insulating film.

As described above, the IPS liquid crystal display has a structure in which the common electrode and the pixel electrode are formed on the same substrate, and have a great advantage in improving the viewing angle.

However, the liquid crystal display of the conventional transverse electric field type (IPS) as described above has the following problems.

First, since the common wiring occupies one region of the pixel region separately from the gate line and the data line, the aperture ratio is lowered.

Second, since the black matrix layer formed on the upper substrate is designed in consideration of the upper and lower plate bonding margins, there is a problem that the opening ratio is lowered.

Third, since the color filter layer is formed on the upper substrate, a misalignment problem occurs between the pixel region and the color filter layer when the upper and lower substrates are bonded, and as the substrate becomes larger, the pixel region of the lower substrate and the color of the upper substrate corresponding thereto are increased. Positional deviation between filter layers becomes large.

In order to solve such a problem, it is necessary to design to cope with the misalignment problem, which causes a problem that the actual aperture ratio is lowered when the upper and lower substrates are bonded.

Fourth, although the sealing material for bonding the upper and lower substrates is in contact with the organic insulating film, the adhesion between the sealing material and the organic insulating film is poor and there is a possibility of poor liquid crystal injection and leakage.

The present invention has been made to solve the above problems, and in particular, an object of the present invention is to provide a liquid crystal display device and a manufacturing method thereof suitable for solving the reduction of the aperture ratio when the upper and lower substrates are bonded.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which may facilitate economical and process application by forming a light shielding film of a lower substrate with a metal.

The liquid crystal display device of the present invention for achieving the above object comprises a first substrate and a second substrate facing each other at a predetermined interval; Gate lines and data lines formed vertically and horizontally on the first substrate to define pixel regions; A first common wiring arranged in the gate line direction; A thin film transistor formed at an intersection of the gate line and the data line; An interlayer insulating film formed on the entire surface of the first substrate including the thin film transistor; A color filter layer formed in the pixel region; A planarization film formed on the first substrate including the common wiring and the common electrode; A light shielding film formed on the planarization film above the channel region of the thin film transistor; A second common line and a common electrode overlapping the gate line, the data line, the upper portion of the thin film transistor, and the light blocking layer and formed in one direction in the pixel area; And a pixel electrode contacted with the drain electrode of the thin film transistor and formed at a predetermined interval between the common electrodes.

The first common line may be formed on the same layer as the gate line.                     

A first contact hole is formed in one region of the drain electrode, and a second contact hole is further provided in one region of the first common wiring.

The drain electrode may be formed on the gate insulating layer on the first common line to form a storage electrode.

The planarization layer is characterized in that it is composed of at least one of photo acryl, polyimide, BCB (Benzo Cyclo Butene).

The light blocking film is formed of at least one metal of chromium (Cr), molybdenum (Mo), copper (Cu), tantalum (Ta), or aluminum (Al).

The surface of the light shielding film is characterized in that it further comprises an oxide film is provided to reduce the reflection of light.

The light shielding film may further include being formed to surround an outer portion of the liquid crystal panel.

The second common line may be formed along an upper portion of the gate line.

The common electrode may be integrally formed with the second common wiring, and may be formed on an upper portion of the data line and a region of the pixel region.

The common electrode on the data line is wider than the data line, and the common electrode of the pixel area is arranged in parallel with the data line.

The second common line is in contact with the first common line in the pixel area through the second contact hole.

The second common line may further include contacting the first common line outside the active area of the liquid crystal panel.

The second common wiring is characterized in that the power is supplied from the outside separately from the first common wiring.

The second common wiring, the common electrode, and the pixel electrode may be formed on the same layer.

The second common wiring, the common electrode, and the pixel electrode may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (Indium Tin). Zinc Oxide: ITZO).

The pixel electrode is in contact with the drain electrode through a first contact hole.

The thin film transistor may include a gate electrode protruding from one side of the gate line, a gate insulating film formed on an entire surface of the lower substrate including the gate electrode, an active layer formed in an island shape on the gate insulating film on the gate electrode; And a source electrode protruding from the data line and overlapping an upper portion of the active layer, and a drain electrode spaced apart from the source electrode at a predetermined interval and overlapping the other side of the active layer.

The color filter layer is partially overlapped with both sides of the data line.

In addition, the liquid crystal display according to another embodiment of the present invention includes a first substrate and a second substrate facing each other at a predetermined interval; Gate lines and data lines formed vertically and horizontally on the first substrate to define pixel regions; A first common wiring arranged in the gate line direction; A thin film transistor formed at an intersection of the gate line and the data line; An interlayer insulating film formed on the entire surface of the first substrate including the thin film transistor; A color filter layer formed in the pixel region; A planarization film formed on the first substrate including the common wiring and the common electrode; A light blocking film formed on the channel region of the thin film transistor and the planarization film on the data line and the gate line; A second common line and a common electrode overlapping the gate line, the data line, the upper portion of the thin film transistor, and the light blocking layer and formed in one direction in the pixel area; And a pixel electrode contacted with the drain electrode of the thin film transistor and formed at a predetermined interval between the common electrodes.

In addition, the liquid crystal display according to another embodiment of the present invention comprises a first substrate and a second substrate facing each other at a predetermined interval; Gate lines and data lines formed vertically and horizontally on the first substrate to define pixel regions; A first common wiring arranged in the gate line direction; A thin film transistor formed at an intersection of the gate line and the data line; An interlayer insulating film formed on the entire surface of the first substrate including the thin film transistor; A color filter layer formed in the pixel region; A planarization film formed on the first substrate including the common wiring and the common electrode; A light shielding film formed on the planarization film above the channel region of the thin film transistor; A second common wiring covering the light blocking film and formed in the gate line direction; And a pixel electrode formed in the pixel region.

Method of manufacturing a liquid crystal display device of the present invention having the above configuration comprises the steps of forming a gate line having a gate electrode on one side on a substrate; Forming a first common line in parallel with the gate line; Forming a gate insulating film on the substrate including the gate line; Forming an active layer on the gate electrode; Forming a data line intersecting with the gate line to define a pixel area; Forming a source electrode and a drain electrode to overlap one side and the other side of the active layer; Forming an interlayer insulating film on the entire surface including the data line; Forming a color filter layer in the pixel region; Forming a planarization film on the substrate including the color filter layer; Forming a light shielding film on the planarization film above the channel region of the thin film transistor; Forming a second common wiring and a common electrode on the light blocking layer including the gate line, the data line, and an upper portion of the channel region and overlapping the pixel region in one direction; The pixel electrode may be formed in the pixel area to have a predetermined interval between the common electrodes.

The first common line may be formed on the same layer as the gate line.

The method may further include forming a storage electrode extending from the drain electrode on the first common line.                     

The planarization layer is formed using at least one of photoacryl, polyimide, and benzocyclobutene (BCB).

Etching the color filter layer and the interlayer insulating layer to expose one region of the drain electrode, and forming a contact hole to expose one region of the drain electrode; and etching the planarization layer on the contact hole to drain the drain. The first contact hole is formed through the second process of forming the contact hole in one region of the electrode.

And forming a second contact hole by sequentially etching the planarization layer, the color filter layer, the interlayer insulating layer, and the gate insulating layer so that one region of the first common wiring is exposed.

The light shielding film may include depositing a metal layer on the planarization layer, and patterning the metal layer by photo and photo etching so as to remain only on an upper portion of a channel region of the thin film transistor.

The metal layer is characterized in that at least one of chromium (Cr), molybdenum (Mo), copper (Cu), tantalum (Ta) or aluminum (Al).

The method may further include forming an oxide film through a heat treatment process to reduce reflection of light on the surface of the light shielding film.

The second common wiring, the common electrode, and the pixel electrode may include depositing a transparent conductive layer on the planarization layer including the light blocking layer, and selectively removing the transparent conductive layer through a photo and etching process. It features.

The oxide film on the surface of the light shielding film may further include depositing a transparent conductive film for forming the common electrode and the pixel electrode in an oxygen atmosphere.

The transparent conductive film may be formed using indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). It is characterized by forming.

The second common line may be formed to overlap the gate line and the thin film transistor.

The common electrode may be formed integrally with the second common line, overlap the upper portion of the second common line in a wider width than the data line, and extend from the second common line to be arranged in one direction in the pixel area. .

The light shielding film may be formed on the planarization film on the gate line and the data line as well as the channel region.

In addition, a method of manufacturing a liquid crystal display device according to another embodiment of the present invention comprises the steps of forming a gate line having a gate electrode on one side on a substrate; Forming a first common line in parallel with the gate line; Forming a gate insulating film on the substrate including the gate line; Forming an active layer on the gate electrode; Forming a data line intersecting with the gate line to define a pixel area; Forming a source electrode and a drain electrode to overlap one side and the other side of the active layer; Forming an interlayer insulating film on the entire surface including the data line; Forming a color filter layer in the pixel region; Forming a planarization film on the substrate including the color filter layer; Forming a light shielding film on the planarization film above the channel region of the thin film transistor; Forming a second common line to overlap the light blocking layer including the gate line and an upper portion of the channel region; The pixel electrode may be formed in the pixel region.

Hereinafter, a liquid crystal display and a method of manufacturing the same according to embodiments of the present invention will be described with reference to the accompanying drawings.

First embodiment

A first embodiment of the present invention is a transverse electric field type liquid crystal display device in which a common electrode is arranged on a lower substrate, and has a color filter on TFT array (COT) structure in which a color filter layer is formed on a lower substrate.

In addition, in the COT structure, a light shielding film (black matrix layer) is formed in the channel region of the TFT of the lower substrate, wherein the light shielding film is characterized by using metal instead of resin.

First, a liquid crystal display according to a first embodiment of the present invention will be described.

FIG. 11 is a plan view of a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 12 is a cross-sectional view of the structure of FIG.

The liquid crystal display according to the first exemplary embodiment of the present invention is a transverse electric field type liquid crystal display in which a common electrode is formed on a lower substrate. The liquid crystal display according to the first embodiment of the present invention is illustrated in FIGS. 11 and 12. A gate line 121 arranged in a row, a gate electrode 121a protruding from one side of the gate line 121, and a first common line arranged in parallel with the same material on the same layer as the gate line 121 ( 121b), a gate insulating layer 122 formed of a material such as SiNx or SiOx on the entire surface of the lower substrate 120 including the gate electrode 121a and the first common wiring 121b, and an upper portion of the gate electrode 121a. An active layer 123 formed in an island shape on the gate insulating layer 122, a data line 124 intersecting with the gate line 121 to define a pixel region, and from the data line 124. One side of the active layer 123 protrudes A source electrode 124a overlapped with a portion, a drain electrode 124b spaced apart from the source electrode 124a by a predetermined interval, and overlapped on the other side of the active layer 123, a data line 124, and a source electrode 124a. And an interlayer insulating film 125 formed on the entire surface of the lower substrate 120 including the drain electrode 124b, color filter layers 126 of R, G, and B formed in each pixel region of the lower substrate 120, and The planarization layer 128 formed on the lower substrate 120 including the color filter layer 126 to have the first contact hole 127a in one region of the drain electrode 124b, the gate electrode 121a and the source electrode. A light blocking film 129 formed above the channel region of the thin film transistor TFT including the 124a and the drain electrode 124b and a planarization film 128 formed on the lower substrate 120 including the light blocking film 129. The second common line 130a and the second common line 130a and are integrally formed with each other. And the common electrode 130b formed in one region of the pixel region, the pixel electrode contacted with the drain electrode 124b through the first contact hole 127a and spaced apart from the common electrode 130b by a predetermined interval. 130c.                     

Although not shown in the drawing, an alignment film (not shown) made of polyimide is formed on the entire surface of the lower substrate 120.

The color filter layer 126 partially overlaps both sides of the data line 124.

The planarization layer 128 has a thickness of about 3 μm in order to prevent a delay of a signal of the gate line 121 and the data line 124 by the second common line 130a and the common electrode 130b. At least one of photoacryl, polyimide, and BCB (Benzo Cyclo Butene) having a low dielectric constant organic insulating film is formed.

In addition, the light blocking film 129 is not formed of resin, but formed of metal.

The light blocking film 129 is not formed of resin, but is formed of metal. Resin is expensive in material, has low resistivity, and has poor electrical characteristics. There is a problem of contamination and particle source, because metal does not cause problems such as resin.

In this case, at least one of chromium (Cr), molybdenum (Mo), copper (Cu), tantalum (Ta), or aluminum (Al) is used as the metal constituting the light blocking film 129.

In addition, an oxide film may be further provided on the surface of the light blocking film 129 to reduce reflection of light.

Although not shown in the drawing, the light blocking film 129 may be formed to surround the outer portion of the liquid crystal panel to serve as a light blocking film that prevents light leakage from the backlight formed under the liquid crystal panel.

The second common line 130a is formed along the upper portion of the gate line 121.

The common electrode 130b is completely overlapped on the data line 124 to drive the lateral electric field together with the adjacent pixel electrode 130c and is formed to have a width wider than that of the data line 124. 130b) is arranged parallel to the data line 124.

In addition, in the second common wiring 130a and the common electrode 130b, a second contact hole 127b is formed to expose the first common wiring 121b, as shown in FIG. 11, so that the first common wiring 121b is formed inside the pixel area. ) Can be contacted.

In addition to the above, the second common wiring 130a and the common electrode 130b may be in contact with the first common wiring 121b outside the active area of the panel, or may be externally supplied with power from the first common wiring 121b. .

The drain electrode 124b extends on the gate insulating layer 122 on the first common wiring 121b to form a storage electrode 124c. As described above, the first embodiment of the present invention has a storage on common structure.

The second common wiring 130a, the common electrode 130b, and the pixel electrode 130c are formed on the same layer, and are indium tin oxide (ITO), tin oxide (TO), and indium zinc. It is composed of Indium Zinc Oxide (IZO) or Indium Tin Zinc Oxide (ITZO).                     

In addition, on the upper substrate 110 corresponding to the lower substrate 120 formed as described above, only the orientation (not shown) is provided without the color filter layer and the black matrix layer.

In the upper substrate 110, the second common wiring 130a, the common electrode 130b, and the light blocking layer 129 formed on the gate line 121, the data line 124, and the channel region of the thin film transistor are disposed in a black matrix. It will be omitted because it acts as a layer.

Although not shown in the drawing, the upper and lower substrates are bonded by a sealing material having a liquid crystal injection hole. At this time, since the light shielding film is formed on the outer side of the lower substrate on which the sealing material is formed, the sealing material is in contact with the light blocking film.

Since the seal material has better contact with the light shielding film than the organic insulating film, it is possible to prevent the occurrence of poor liquid crystal injection and liquid crystal leakage due to a poor contact with the organic insulating film of the seal material in the prior art.

Next, a manufacturing method of the liquid crystal display device according to the first embodiment of the present invention will be described so as to have the above configuration.

13A to 13C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention.

In the manufacturing method of the liquid crystal display according to the first exemplary embodiment of the present invention, first, a conductive metal is deposited on a transparent lower substrate 120 as shown in FIG. 13A, and the conductive metal is patterned by using a photo and etching process. Thus, a gate pad (not shown) having one end widened to a predetermined area, a gate line 121 extending in one direction from the gate pad, and a gate electrode 121a protruding in one direction from the gate line 121. ).

In addition, a first common wiring 121b is formed on the same layer as the gate line 121 so as to be arranged in a direction parallel to the gate line 121.

Thereafter, the gate insulating layer 122 is formed on the entire surface of the lower substrate 120 on which the gate line 121 and the first common wiring 121b are formed.

The gate insulating layer 122 may use a silicon nitride layer (SiNx) or a silicon oxide layer (SiO ₂ ).

Thereafter, a semiconductor layer (amorphous silicon + impurity amorphous silicon) is formed on the gate insulating layer 122.

Subsequently, the semiconductor layer is patterned by photo and etching processes to form an active layer 123 having an island shape on the gate electrode 121a.

Subsequently, a conductive metal is deposited on the entire surface of the lower substrate 120 on which the active layer 123 is formed, and patterned through photo and etching processes to intersect the gate line 121 to define a pixel region 124. ), A source pad (not shown) having a predetermined area at an end thereof, a source electrode 124a protruding in one direction from the data line 124, and a drain electrode separated from the source electrode 124a at a predetermined interval. 124b is formed.

In this case, the storage electrode 124c is formed on the first common wiring 121b to extend from the drain electrode 124b. The storage structure is a storage on common structure.                     

Subsequently, as shown in FIG. 13B, an interlayer insulating layer 125 is formed on the entire surface of the lower substrate 120 on which the data line 124 is formed.

The interlayer insulating layer 125 is formed of an oxide film or a nitride film serving as a protective film.

Thereafter, R, G, and B color filter layers 126 are formed in each pixel region. In this case, the color filter layer 126 is formed to overlap the data line 124.

Next, the color filter layer 126 and the interlayer insulating layer 125 are etched to form a first contact hole 127a to expose one region of the drain electrode 124b.

Next, as shown in FIG. 13C, the planarization film 128 is formed on the color filter layer 126.

In this case, the planarization layer 128 may be formed using at least one of photoacryl, polyimide, and benzocyclobutene (BCB).

Next, the planarization layer 128 on the first contact hole 127a is etched to form a contact hole so that one region of the drain electrode 124b is exposed. At this time, the planarization layer 128, the color filter layer 126, the interlayer insulating layer 125, and the gate insulating layer 122 are sequentially etched so that one region of the first common wiring 121b is exposed to form a second contact hole 127b. do.

Subsequently, a metal layer is deposited on the planarization layer 128 and patterned through photo and photolithography to form a light blocking layer 129 on the channel region of the thin film transistor.

In this case, the light blocking film 129 may be formed using at least one of chromium (Cr), molybdenum (Mo), copper (Cu), tantalum (Ta), or aluminum (Al).                     

The light shielding film 129 may further include a process of forming an oxide film to reduce reflection of light on the surface. In this case, the process of forming the oxide film may be performed by heat treatment after patterning the metal layer.

In addition, the oxide film on the surface of the light blocking film 129 may be formed when a transparent conductive film for forming the common electrode and the pixel electrode is subsequently deposited in an oxygen atmosphere.

Thereafter, after the transparent conductive film is deposited on the planarization film 128 including the light blocking film 129, the transparent conductive film is selectively removed through a photo and etching process, thereby forming the second common wiring 130a, the common electrode 130b, and The pixel electrode 130c is formed.

In this case, the second common wiring 130a is formed to overlap the gate line 121 and the thin film transistor.

The common electrode 130b is connected to the second common line 130a and is formed to overlap the upper portion of the common line 130a with a width wider than that of the data line 124. The common electrode 130b extends from the second common line 130a and extends in one direction to the pixel area. Are arranged. In this case, the second common electrode 130b formed in the pixel area is arranged in parallel with the data line 124, and one end of the second common electrode 130b overlaps the upper portion of the first common line 121b.

The pixel electrode 130c and the drain electrode 124b are connected to each other through the first contact hole 127a.

The transparent conductive film may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). Can be formed.                     

Although not shown in the drawings, an alignment layer made of polyimide or photo-alignment material is formed on the entire surface of the lower substrate 120 including the second common wiring 130a, the common electrode 130b, and the pixel electrode 130c. Form.

Here, the alignment layer made of polyimide is determined by mechanical rubbing, and the photoreactive material made of polyvinylcinnamate based material or polysiloxane based material is oriented by irradiation with light such as ultraviolet rays. This is determined.

At this time, the orientation direction is determined by the irradiation direction of the light or the property of the irradiated light, that is, the polarization direction.

Thereafter, the upper substrate 110 is prepared, and a sealing material (not shown) for bonding the lower substrate 120 and the upper substrate 110 is formed on the lower substrate 120 or the upper substrate 120.

Subsequently, the upper substrate 110 and the lower substrate 120 are bonded to each other.

Although not shown in the drawing, an alignment layer of the same material as the lower substrate 120 is formed on the front surface of the upper substrate 110.

Second embodiment

A second embodiment of the present invention is a transverse electric field type liquid crystal display device in which a common electrode is arranged on a lower substrate, and has a color filter on TFT array (COT) structure in which a color filter layer is formed on a lower substrate.

In the COT structure, a light shielding film (black matrix layer) is formed on the lower substrate, wherein the light shielding film is formed not only in the TFT region but also in the upper portion of the gate line and the data line. It is characteristic to use.

That is, the same as in the first embodiment of the present invention except for the configuration of the light shielding film.

FIG. 14 is a plan view of a liquid crystal display according to a second exemplary embodiment of the present invention, FIG. 15 is a cross-sectional view of a cross-sectional view taken along lines 'V' and '-V' in FIG. 14, and FIGS. 16A to 16C illustrate the present invention. A process cross-sectional view showing the manufacturing method of the liquid crystal display device according to the second embodiment.

Hereinafter, a liquid crystal display according to a second embodiment of the present invention will be described.

As shown in FIGS. 14 and 15, the gate line 121 arranged in one direction on the transparent lower substrate 120, the gate electrode 121a protruding from one side of the gate line 121, and the gate line SiNx or SiOx on the entire surface of the lower substrate 120 including the first common wiring 121b arranged in parallel with the same material on the same layer as the 121 and the gate electrode 121a and the first common wiring 121b. The gate insulating layer 122 formed of the same material as the material, the active layer 123 formed in an island shape on the gate insulating layer 122 on the gate electrode 121a, and the gate line 121 intersecting with each other. A data line 124 defining a pixel area, a source electrode 124a protruding from the data line 124 and overlapping an upper portion of the active layer 123, and a predetermined distance from the source electrode 124a And overlap the other side of the active layer 123 An interlayer insulating film 125 formed on the entire surface of the lower substrate 120 including the phosphorus electrode 124b, the data line 124, the source electrode 124a, and the drain electrode 124b, and each of the lower substrate 120. On the lower substrate 120 including the color filter layer 126 having R, G, and B color filter layers 126a formed in the pixel region and the first contact hole 127a in one region of the drain electrode 124b. The gate line 121 and the data line 124 as well as an upper portion of the channel region of the TFT including the planarization layer 128 formed on the planarization layer 128, the gate electrode 121a, the source electrode 124a, and the drain electrode 124b. ) A light blocking film 129 extending upwardly, a second common wiring 130a formed on the planarization film 128 of the lower substrate 120 including the light blocking film 129, and the second common wiring 130a. A common electrode 130b formed integrally with the data line 124 and formed in one region of the pixel region; First through a contact hole (127a) and the drain contact electrode (124b) is composed of a pixel electrode (130c) spaced apart a predetermined interval between said common electrode (130b).

Although not shown in the drawing, an alignment film (not shown) made of polyimide is formed on the entire surface of the lower substrate 120.

The planarization layer 128 has a thickness of about 3 μm in order to prevent a delay of a signal of the gate line 121 and the data line 124 by the second common line 130a and the common electrode 130b. At least one of photoacryl, polyimide, and BCB (Benzo Cyclo Butene) having a low dielectric constant organic insulating film is formed.

In addition, the light blocking film 129 is not formed of resin, but formed of metal.

The light blocking film 129 is not formed of resin, but is formed of metal. Resin is expensive in material, has low resistivity, and has poor electrical characteristics. There is a problem of impurity contamination and particle source, since metal does not cause problems such as resin.

In this case, at least one of chromium (Cr), molybdenum (Mo), copper (Cu), tantalum (Ta), or aluminum (Al) is used as the metal constituting the light blocking film 129.

In addition, an oxide film may be further provided on the surface of the light blocking film 129 to reduce reflection of light.

Although not shown in the drawing, the light blocking film 129 may be formed to surround the outer portion of the liquid crystal panel so as to serve as a light blocking film that prevents light leakage from the backlight formed under the liquid crystal panel.

The second common line 130a is formed along the upper portion of the gate line 121.

The common electrode 130b is completely overlapped on the data line 124 to drive the lateral electric field together with the adjacent pixel electrode 130c and is formed to have a width wider than that of the data line 124. 130b is arranged in parallel with the data line 124.

In addition, in the second common wiring 130a and the common electrode 130b, a second contact hole 127b is formed to expose the first common wiring 121b, as shown in FIG. 11, so that the first common wiring 121b is formed inside the pixel area. ) Can be contacted.

In addition to the above configuration, the second common wiring 130a and the common electrode 130b may be brought into contact with the first common wiring 121b outside the active area of the panel, or separately supplied from the first common wiring 121b. It may be.

The drain electrode 124b extends on the gate insulating layer 122 on the first common wiring 121b to form a storage electrode 124c. As such, the storage capacitor has a storage on common structure.

The second common wiring 130a, the common electrode 130b, and the pixel electrode 130c may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (Indium Zinc Oxide). IZO) or Indium Tin Zinc Oxide (ITZO).

In addition, on the upper substrate 110 corresponding to the lower substrate 120 formed as described above, only the orientation (not shown) is provided without the color filter layer and the black matrix layer.

In the upper substrate 110, the second common wiring 130a, the common electrode 130b, and the light blocking layer 129 formed on the gate line 121, the data line 124, and the channel region of the thin film transistor are disposed in a black matrix. It will be omitted because it acts as a layer.

Hereinafter, a method of manufacturing a liquid crystal display device according to a second embodiment of the present invention will be described.

In the method of manufacturing the liquid crystal display according to the second exemplary embodiment of the present invention, as shown in FIGS. 16A through 16C, the light blocking film 129 may not only have a channel region of the thin film transistor, but also a gate line 121 and a data line 124. Except for extending the upper portion, since it is formed by the same method as the manufacturing method of the first embodiment of the present invention, it will be omitted below.                     

Third embodiment

A third embodiment of the present invention is a TN mode liquid crystal display adopting a storage on common structure, and has a color filter on TFT array (COT) structure in which a color filter layer is formed on a lower substrate.

In addition, in the COT structure, a light blocking film (black matrix layer) is formed in the channel region of the TFT of the lower substrate, wherein the light blocking film is formed of metal instead of resin.

Hereinafter, a liquid crystal display according to a third embodiment of the present invention will be described.

17 and 18, a gate line 191 arranged in one direction on the transparent lower substrate 190, a gate electrode 191a protruding from one side of the gate line 191, and the gate SiNx or on the front surface of the lower substrate 190 including the first common wiring 191b and the gate electrode 191a and the first common wiring 191b arranged in parallel on the same layer as the line 191. The gate insulating film 192 formed of a material such as SiOx, the active layer 193 formed in an island shape on the gate insulating film 192 on the gate electrode 191a, and the gate line 191 intersecting with each other. A data line 194 defining a pixel area, a source electrode 194a protruding from the data line 194 and overlapping an upper portion of the active layer 193, and a predetermined distance from the source electrode 194a. Spaced and overlapping the other side of the active layer 193 An interlayer insulating film 195 formed on the entire surface of the lower substrate 190 including the phosphorus electrode 194b, the data line 194, the source electrode 194a, and the drain electrode 194b, and the lower substrate 190. The lower substrate 190 including the color filter layer 196 having R, G, and B color filter layers 196 formed in each pixel region and the first contact hole 197a in one region of the drain electrode 194b. The planarization film 198 formed thereon, the light shielding film 199 formed on the channel region of the TFT including the gate electrode 191a, the source electrode 194a, and the drain electrode 194b, and the light shielding film ( A second common wiring 200a formed on the planarization film 198 to cover 199 and a pixel electrode 200b formed on the pixel region to contact the drain electrode 194b through the first contact hole 197a. It is composed of

Although not shown in the drawing, an alignment layer (not shown) made of polyimide is formed on the entire surface of the lower substrate 190.

The planarization film 198 has a thickness of about 3 μm in order to prevent a delay of signals of the gate line 191 and the data line 194 due to the second common line 200a and the common electrode 190b. At least one of photoacryl, polyimide, and BCB (Benzo Cyclo Butene) having a low dielectric constant organic insulating film is formed.

In addition, the light blocking film 199 is not formed of resin, but formed of metal.

In this case, at least one of chromium (Cr), molybdenum (Mo), copper (Cu), tantalum (Ta), or aluminum (Al) is used as the metal constituting the light shielding film 199.

In addition, an oxide film may be further provided on the surface of the light blocking film 199 to reduce reflection of light.                     

Although not shown in the drawing, the light blocking film 199 may be formed to surround the outer portion of the liquid crystal panel to serve as a light blocking film that prevents light leakage from the backlight formed under the liquid crystal panel.

The second common wiring 200a covers the light blocking film 199 and is formed in the direction of the gate line 191 so as to partially overlap the gate line 191.

As described above, since the second common wiring 200a covers the light blocking film 199 and is connected to each other, the light blocking film 199 may serve to block light without affecting the thin film transistor.

In addition, as shown in FIG. 17, since the second contact hole 197b is formed to expose the first common wiring 191b, the second common wiring 200a may be in contact with the first common wiring 191b in the pixel area. can do.

In addition to the above configuration, the second common wiring 200a may be in contact with the first common wiring 191b outside the active area of the panel, or may be externally supplied with power from the first common wiring 191b.

The drain electrode 194b extends on the gate insulating layer 192 on the first common wiring 191b to form the storage electrode 194c. As such, the storage capacitor has a storage on common structure.

The second common wiring 200a and the pixel electrode 200b may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc. It may be formed using an oxide (Indium Tin Zinc Oxide: ITZO).

In addition, a black matrix layer 181 is formed on a portion corresponding to the gate line, the data line, and the thin film transistor without the color filter layer on the upper substrate 180 corresponding to the lower substrate 190 formed as described above. (180) Only an orientation (not shown) is comprised in the front surface.

Hereinafter, a method of manufacturing a liquid crystal display device according to a third embodiment of the present invention will be described.

The manufacturing method of the liquid crystal display according to the third exemplary embodiment of the present invention is the present invention except that the position and shape of forming the second common wiring 200a and the pixel electrode 200b are different without forming a common electrode. Proceeds in the same manner as the manufacturing method of the liquid crystal display device according to the first embodiment of the invention.

That is, FIGS. 19A and 19B proceed in the same manner as described in FIGS. 13A and 13B, respectively.

Hereinafter, a part different from the first embodiment of the present invention will be described. As shown in FIG. 19C, the planarization film 198 is formed on the color filter layer 196.

In this case, the planarization layer 198 may be formed using at least one of photoacryl, polyimide, and benzocyclobutene (BCB).

Next, the planarization layer 198 on the first contact hole 197a is etched to form a contact hole so that one region of the drain electrode 194b is exposed. At this time, the planarization film 198, the color filter layer 196, the interlayer insulation film 195, and the gate insulating film 192 are sequentially etched so that one region of the first common wiring 191b is exposed, and the second contact hole 197b is also etched. Form.

Subsequently, a metal layer is deposited on the planarization layer 198 and patterned through photo and photolithography to form a light shielding film 199 on the channel region of the thin film transistor.

In this case, the light blocking film 199 may be formed using at least one of chromium (Cr), molybdenum (Mo), copper (Cu), tantalum (Ta), or aluminum (Al).

The light shielding film 199 may further include a process of forming an oxide film in order to reduce reflection of light on the surface. In this case, the process of forming the oxide film may be performed by heat treatment after patterning the metal layer.

In addition, the oxide film on the surface of the light shielding film 199 may be formed when a transparent conductive film for forming the common electrode and the pixel electrode is subsequently deposited in an oxygen atmosphere.

Thereafter, a transparent conductive film is deposited on the planarization film 198 including the light blocking film 199, and then the transparent conductive film is selectively removed through a photolithography and etching process to remove the second common wiring 200a and the pixel electrode 200b. Form.

In this case, the second common wiring 200a covers the light blocking film 199 and overlaps the gate line 191 so as to be arranged in the direction of the gate line 191.

The pixel electrode 200b and the drain electrode 194b are connected to each other through the first contact hole 197a.

The transparent conductive film may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). Can be formed.                     

Subsequently, although not shown in the drawing, an alignment layer made of polyimide or a photo-alignment material is formed on the entire surface of the lower substrate 190 including the second common wiring 200a and the pixel electrode 200b.

Here, the alignment layer made of polyimide is determined by mechanical rubbing, and the photoreactive material made of polyvinylcinnamate based material or polysiloxane based material is oriented by irradiation with light such as ultraviolet rays. This is determined.

At this time, the orientation direction is determined by the irradiation direction of the light or the property of the irradiated light, that is, the polarization direction.

Thereafter, the upper substrate 180 is prepared, and a sealing material (not shown) for bonding the lower substrate 190 and the upper substrate 180 is formed on the lower substrate 190 or the upper substrate 180.

Subsequently, the upper substrate 180 and the lower substrate 190 are bonded to each other.

Although not shown in the drawing, an alignment layer of the same material as the lower substrate 190 is formed on the front surface of the upper substrate 180.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the above embodiments, but should be defined by the claims.

The liquid crystal display of the present invention as described above and a manufacturing method thereof have the following effects.

First, since the color filter layer is formed on the lower substrate, and the light shielding film completely covers the channel region of the TFT, it is possible to solve the problem that the aperture ratio is reduced by the upper / lower substrate bonding margin.

Second, since the light shielding film is formed of metal instead of resin, price competitiveness and electrical characteristics can be improved.

Third, since the common wiring and the common electrode overlap each other on the gate line, the data line, and the channel region to serve as a black matrix layer, it is possible to prevent the misalignment problem caused by the upper and lower substrate bonding.

Fourth, since the sealing material is in contact with the light shielding film, the adhesion of the sealing material is improved as compared with the prior art, and it is possible to prevent the occurrence of poor liquid crystal injection and liquid crystal leakage due to poor adhesion.

Claims (37)

A first substrate and a second substrate facing each other at intervals; Gate lines and data lines formed vertically and horizontally on the first substrate to define pixel regions; A first common wiring arranged in the gate line direction; A thin film transistor formed at an intersection of the gate line and the data line; An interlayer insulating film formed on the entire surface of the first substrate including the thin film transistor; A color filter layer formed in the pixel region; A planarization film formed on the first substrate including the common wiring and the common electrode; A light shielding film formed on the planarization film above the channel region of the thin film transistor; A second common line and a common electrode overlapping the gate line, the data line, the upper portion of the thin film transistor, and the light blocking layer and formed in one direction in the pixel area; A pixel electrode in contact with the drain electrode of the thin film transistor and having a predetermined interval between the common electrodes and formed on the same layer as the common electrode, And the drain electrode is formed on the gate insulating layer on the first common line to form a storage electrode. The method of claim 1, And the first common line is formed on the same layer as the gate line. The method of claim 1, And a second contact hole in one region of the drain electrode and a second contact hole in one region of the first common wiring. delete The method of claim 1, And the planarization layer is formed of at least one of photoacryl, polyimide, and benzocyclobutene (BCB). The method of claim 1, The light blocking film is formed of at least one metal of chromium (Cr), molybdenum (Mo), copper (Cu), tantalum (Ta) or aluminum (Al). The method of claim 1, The surface of the light shielding film further comprises an oxide film is provided to reduce the reflection of light. The method of claim 1, And the light blocking film is formed to surround an outer portion of the liquid crystal panel. The method of claim 1, And the second common line is formed along an upper portion of the gate line. The method of claim 1, And the common electrode is integrally formed with the second common line, and is formed on an upper portion of the data line and a region of the pixel region. The method of claim 10, The width of the common electrode above the data line is wider than the width of the data line, and the common electrode of the pixel area is arranged in parallel with the data line. The method of claim 3, wherein And the second common line is in contact with the first common line in the pixel area through the second contact hole. The method of claim 1, And the second common line is in contact with the first common line outside the active area of the liquid crystal panel. The method of claim 1, And the second common line is supplied with power from the outside separately from the first common line. The method of claim 1, And the second common wiring, the common electrode and the pixel electrode are formed on the same layer. The method of claim 1, The second common wiring, the common electrode, and the pixel electrode may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (Indium Tin). Liquid crystal display characterized by consisting of Zinc Oxide (ITZO). The method of claim 3, wherein And the pixel electrode is in contact with the drain electrode through a first contact hole. The method of claim 1, The thin film transistor may include a gate electrode protruding from one side of the gate line; A gate insulating film formed on an entire surface of the lower substrate including the gate electrode; An active layer formed in an island shape on the gate insulating layer on the gate electrode; A source electrode protruding from the data line and overlapping an upper portion of one side of the active layer; And a drain electrode spaced apart from the source electrode at a predetermined interval and overlapping the other side of the active layer. The method of claim 1, And the color filter layer overlaps both sides of the data line. A first substrate and a second substrate facing each other at intervals; Gate lines and data lines formed vertically and horizontally on the first substrate to define pixel regions; A first common wiring arranged in the gate line direction; A thin film transistor formed at an intersection of the gate line and the data line; An interlayer insulating film formed on the entire surface of the first substrate including the thin film transistor; A color filter layer formed in the pixel region; A planarization film formed on the first substrate including the common wiring and the common electrode; A light blocking film formed on the channel region of the thin film transistor and the planarization film on the data line and the gate line; A second common line and a common electrode overlapping the gate line, the data line, the upper portion of the thin film transistor, and the light blocking layer and formed in one direction in the pixel area; A pixel electrode in contact with the drain electrode of the thin film transistor and having a predetermined interval between the common electrodes and formed on the same layer as the common electrode, And the drain electrode is formed on the gate insulating layer on the first common line to form a storage electrode. A first substrate and a second substrate facing each other at intervals; Gate lines and data lines formed vertically and horizontally on the first substrate to define pixel regions; A first common wiring arranged in the gate line direction; A thin film transistor formed at an intersection of the gate line and the data line; An interlayer insulating film formed on the entire surface of the first substrate including the thin film transistor; A color filter layer formed in the pixel region; A planarization film formed on the first substrate including the common wiring and the common electrode; A light shielding film formed on the planarization film above the channel region of the thin film transistor; A second common wiring covering the light blocking film and formed in the gate line direction; A pixel electrode formed in the pixel region of the same layer as the common electrode; And the light shielding film is further formed to surround an outer portion of the first substrate. Forming a gate line having a gate electrode on one side of the substrate; Forming a first common line in parallel with the gate line; Forming a gate insulating film on the substrate including the gate line; Forming an active layer on the gate electrode; Forming a data line intersecting with the gate line to define a pixel area; Forming a source electrode and a drain electrode to overlap one side and the other side of the active layer; Forming an interlayer insulating film on the entire surface including the data line; Forming a color filter layer in the pixel region; Forming a planarization film on the substrate including the color filter layer; Forming a light shielding film on the planarization film so as to surround an upper portion of a channel region of the thin film transistor and an outer portion of the substrate; Forming a second common wiring and a common electrode on the light blocking layer including the gate line, the data line, and an upper portion of the channel region and overlapping the pixel region in one direction; And forming a pixel electrode in the pixel area of the same layer as the common electrode with a predetermined interval between the common electrodes. The method of claim 22, And the first common line is formed on the same layer as the gate line. The method of claim 22, And forming a storage electrode extending from the drain electrode on the first common line. The method of claim 22, And the planarization film is formed using at least one of photoacryl, polyimide, and benzocyclobutene (BCB). The method of claim 22, A first process of forming a contact hole to expose one region of the drain electrode by etching the color filter layer and the interlayer insulating layer to expose one region of the drain electrode; And forming a first contact hole by etching the planarization layer over the contact hole to form a contact hole in one region of the drain electrode. The method of claim 22, And forming a second contact hole by sequentially etching the planarization layer, the color filter layer, the interlayer insulating layer, and the gate insulating layer so that one region of the first common wiring is exposed. Way. The method of claim 22, The light shielding film is a process of depositing a metal layer on the planarization film; And patterning the metal layer by photo and photo etching so as to remain only in an upper portion of the channel region of the thin film transistor. 29. The method of claim 28, The metal layer is at least one of chromium (Cr), molybdenum (Mo), copper (Cu), tantalum (Ta) or aluminum (Al). The method of claim 22, And forming an oxide film by a heat treatment process to reduce reflection of light on the surface of the light shielding film. The method of claim 22, Depositing a transparent conductive film on the second common wiring, the common electrode, and the pixel electrode on the planarization film including the light blocking film; And removing the transparent conductive film selectively through a photo and an etching process. 32. The method of claim 30 or 31 wherein The oxide film on the surface of the light shielding film may further be formed by depositing a transparent conductive film for forming the common electrode and the pixel electrode in an oxygen atmosphere. The method of claim 31, wherein The transparent conductive film may be formed using indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). Forming a liquid crystal display device. The method of claim 22, And the second common line is formed to overlap the gate line and the thin film transistor. The method of claim 22, The common electrode may be formed integrally with the second common line, overlap the upper portion of the second common line in a wider width than the data line, and extend from the second common line to be arranged in one direction in the pixel area. Method of manufacturing a liquid crystal display device. The method of claim 22, And the light shielding layer is formed on the planarization layer above the gate line and the data line as well as the channel region. Forming a gate line having a gate electrode on one side of the substrate; Forming a first common line in parallel with the gate line; Forming a gate insulating film on the substrate including the gate line; Forming an active layer on the gate electrode; Forming a data line intersecting with the gate line to define a pixel area; Forming a source electrode and a drain electrode to overlap one side and the other side of the active layer; Forming an interlayer insulating film on the entire surface including the data line; Forming a color filter layer in the pixel region; Forming a planarization film on the substrate including the color filter layer; Forming a light shielding film on the planarization film so as to surround an upper portion of a channel region of the thin film transistor and an outer periphery of the substrate; Forming a second common line and a common electrode to overlap the light blocking layer including the gate line and the upper portion of the channel region; Forming a pixel electrode in the pixel region of the same layer as the common electrode; And forming a storage electrode extending from the drain electrode on the first common line.

Images