KR20070072116A - Liquid crystal display device and fabricating method - Google Patents

Abstract

An LCD(Liquid Crystal Display) and a manufacturing method thereof are provided to effectively prevent generation of an optical current between a source electrode and a drain electrode in a gate off state by forming an light block layer under an active layer and manufacturing a thin film transistor array substrate with use of three photomasks. Gate lines and data lines are disposed on a substrate to define a plurality of pixels. A semiconductor layer(203) is formed on the substrate to form an active layer pattern, and source and drain electrodes(205,206) are formed on the semiconductor layer. A gate insulating layer is formed on the source and drain electrodes, and a gate insulating layer is patterned to have the same shape as a gate electrode(208) and a common electrode(209). The gate electrode is formed on the gate insulating layer, and is formed at a predetermined portion on the semiconductor layer. The common electrode is formed on the gate insulating layer. A pixel electrode(210) overlaps a predetermined portion of the drain electrode, and is electrically connected to the drain electrode. A light block layer is formed under the semiconductor layer.

Description

Liquid crystal display device and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND FABRICATING METHOD}

1 is a plan view showing a liquid crystal display device according to the prior art

Figure 2 is a cross-sectional view showing a liquid crystal display device according to the prior art (A-A 'cross section of Figure 1)

3A to 3D are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to the prior art, step by step using a cross-sectional view taken along the line AA ′ of FIG. 1.

4 is a plan view showing a liquid crystal display device of the present invention.

5 is a cross-sectional view showing a liquid crystal display device according to the present invention (A-A 'cut section of Figure 4)

6A to 6E are cross-sectional views showing the manufacturing method of the liquid crystal display device of the present invention step by step using a cross-sectional view taken along the line AA ′ of FIG. 4.

** Explanation of symbols for main parts of drawings **

202: light blocking layer

203, 204: active layer, ohmic contact layer

205: source electrode

206: drain electrode

207: gate leading layer

208: gate electrode

209: common electrode

210: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-plane switch type liquid crystal display device and a manufacturing method thereof, and more particularly, to a structure of a liquid crystal display device capable of reducing the number of process masks and a method of manufacturing the same.

A liquid crystal display device is a display device that displays an image by adjusting the light transmittance of the liquid crystal using an electric field generated by a voltage applied to a predetermined electrode, and is a vertical electric field and a horizontal electric field in accordance with the direction of the electric field driving the liquid crystal. It is divided into switch type.

In the vertical field type liquid crystal display device, the common electrode formed on the upper substrate and the pixel electrode formed on the lower substrate are disposed to face each other to drive the liquid crystal of TN (Twisted Nemastic) mode by a vertical electric field formed therebetween. Such a vertical field type liquid crystal display device has an advantage of having a large aperture ratio while having a narrow viewing angle of about 90 degrees.

In contrast, the in-plane switch type liquid crystal display device drives the liquid crystal by a horizontal electric field formed between the pixel electrode and the common electrode arranged side by side on the lower substrate. Such an in-plane switch type liquid crystal display device has a wide viewing angle of about 160 degrees. Hereinafter, an in-plane switch type liquid crystal display device will be described in detail.

An in-plane switch type liquid crystal display device is composed of a thin film transistor array substrate (lower substrate), a color filter substrate (upper substrate), and liquid crystals filled between the substrates bonded to each other. The thin film transistor array substrate includes a plurality of signal wirings for forming a horizontal electric field in each unit pixel, a thin film transistor, and an alignment layer coated for liquid crystal alignment. The color filter substrate is composed of a color filter for color implementation, a black matrix for preventing light leakage, and an alignment film coated for liquid crystal alignment.

The photolithography technique is used to manufacture the thin film transistor array substrate constituting the liquid crystal display device, and the application of the photolithography technique to a manufacturing process requires a large manufacturing cost and difficult yield management. In order to solve the above problems, a 'low mask' process to be applied to a method of manufacturing a thin film transistor array substrate has been actively studied, and a manufacturing method of reducing the total number of process masks to four has recently emerged.

FIG. 1 is a plan view illustrating a thin film transistor array substrate of an in-plane switch type liquid crystal display device using four mask processes according to the prior art, and FIG. 2 is a thin film taken along the line A-A 'of FIG. A cross-sectional view showing a transistor array substrate.

As shown in FIGS. 1 and 2, the thin film transistor array substrate of the in-plane switch type liquid crystal display device according to the related art has a gate wiring 115 and a data wiring formed on the lower substrate 101. 116 and common wiring 117, a thin film transistor formed in each pixel region, and a pixel electrode 114 and a common electrode 107 formed to form a horizontal electric field in each pixel region. In addition to the above components, a storage capacitor (not shown) may be formed at an overlapping portion of the pixel electrode 114 and the common wiring 117.

First, the wirings for supplying signals to the respective wirings will be described. The gate wiring 115 supplies a gate signal to the gate electrode 104 of the thin film transistor, and the data wiring 116 connects the drain electrode 112 of the thin film transistor. The pixel signal is supplied to the pixel electrode 114, and the common wiring 117 supplies a reference voltage for driving the liquid crystal to the common electrode 107 with the pixel region interposed therebetween.

Next, the thin film transistor serves to keep the pixel signal of the data line 116 charged and maintained in the pixel electrode 114 in response to the gate signal of the gate line 115. ), The gate electrode 104 electrically connected to the gate electrode 104, the source electrode 111 electrically connected to the data wiring 116, the drain electrode 112 electrically connected to the pixel electrode 114, the gate electrode 104 and the gate insulating layer. The active layer 109 forms a channel between the source electrode 111 and the drain electrode 112 while overlapping the gap 108. In this case, the active layer 109 is formed to overlap the data line 116, the data pad lower electrode (not shown) and the storage electrode (not shown), and the data line 116 on the active layer 109. A source electrode 111, a drain electrode 112, a data pad lower electrode (not shown), a storage electrode (not shown), and an ohmic contact layer 110 for ohmic contact are further formed.

Next, referring to the remaining components including the pixel electrode, the pixel electrode 114 is electrically connected to the drain electrode 112 of the thin film transistor through a contact hole penetrating through the passivation layer 113 and formed in the pixel region. The electrode 107 is electrically connected to the common wiring 117 to be formed in the pixel area.

Accordingly, a horizontal electric field is formed between the pixel electrode 114 to which the pixel signal is applied through the thin film transistor and the common electrode 107 to which the reference voltage is applied through the common wiring 117. The horizontal electric field causes the liquid crystal molecules arranged in the horizontal direction between the thin film transistor array substrate and the color filter array substrate to rotate by dielectric anisotropy, so that the light transmittance that passes through the pixel region varies depending on the degree of rotation of the liquid crystal molecules. As a result, an image is realized.

However, one of the problems of the thin film transistor array substrate of the liquid crystal display device according to the related art is that light incident from the backlight may reach the active layer constituting the thin film transistor of the liquid crystal display device, thereby generating a photocurrent. When the photocurrent occurs, the off current of the thin film transistor is increased to cause mura on the screen display, thereby degrading the performance of the liquid crystal display.

Referring to FIGS. 3A to 3D, a manufacturing method using a four mask process among the manufacturing methods of a thin film transistor array substrate according to the related art having the above configuration is as follows.

First, as shown in FIG. 3A, a gate electrode 104 and a gate pad electrode (not shown) are formed on an insulating substrate 101 using a first mask process.

In detail, the first metal layer 102 and the second metal layer 103 are sequentially deposited on the insulating substrate 101 using a deposition method such as a sputtering method to form a metal layer forming a double layer. Subsequently, the metal layers are patterned by a photolithography process using a first mask and an etching process using a photoresist pattern to form a gate electrode 104 and a common electrode 107. In this case, an aluminum-based metal is mainly used as the first metal layer 102, and a metal such as chromium (Cr) or molybdenum (Mo) is mainly used as the second metal layer 103.

As shown in FIG. 3B, the gate insulating layer 108 is formed on the insulating substrate 101 on which the gate electrode 104 and the common electrode 107 are formed. The semiconductor pattern including the active layer 109 and the ohmic contact layer 110, the source electrode 111, and the drain electrode 112 are formed on the gate insulating layer 108 using the second mask process.

In detail, the plasma enhanced chemical vapor deposition (PECVD) or sputtering is performed on the insulating substrate 101 on which the gate electrode 104 and the common electrode 107 are formed. The gate insulating layer 108, the active layer 109, the ohmic contact layer 110, and the source and drain electrode layers are sequentially formed through the deposition method. In this case, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the gate insulating layer 108, and amorphous silicon without doping impurities is used as the active layer 109, and the ohmic contact layer 110 is used. For the formation, amorphous silicon doped with N-type or P-type impurities is used. Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy) and the like are used to form the source and drain electrode layers.

Subsequently, a photoresist pattern is formed on the source and drain electrode layers by a photolithography process using a second mask. In this case, the photoresist pattern of the channel region constituting the active layer has a lower thickness than the photoresist pattern of the other region by using a diffraction mask having a diffraction exposure portion in the channel portion of the thin film transistor as the second mask. To form.

The source electrode 111 and the drain electrode 112 are formed through a wet etching process using photoresist patterns having different heights of the channel region as masks. Subsequently, the active layer 109 and the ohmic contact layer 110 are simultaneously patterned by a dry etching process using the same photoresist pattern to form an active layer pattern and an ohmic contact layer pattern, and a partial ashing process is performed on the channel region. After removing the photoresist pattern having a relatively low height, the source and drain electrode layers and the ohmic contact layer 110 on the channel region are etched by a dry etching process. Next, the photoresist pattern remaining in the strip process is removed.

In the next step, as shown in FIG. 3C, the protective layer 113 including the contact hole is formed on the substrate on which the source and drain electrodes 111 and 112 are formed by using a third mask process.

In detail, the protective layer 113 is formed on the substrate on which the source and drain electrodes are formed by a deposition method such as PECVD. Subsequently, the protective layer 113 is patterned by a photolithography process using a third mask and an etching process using a photoresist pattern to form contact holes. The contact hole is formed on the drain electrode of the protective layer 113 to expose the drain electrode 112. In this case, an inorganic insulating material such as the gate insulating layer 108 or an acryl-based organic compound having a low dielectric constant may be used as the material of the protective layer 113.

As a next step, the pixel electrode 114 is formed on the passivation layer 113 using a fourth mask process as shown in FIG. 3D.

In detail, the transparent conductive layer is deposited on the protective layer 113 by a deposition method such as sputtering. Subsequently, the pixel electrode 114 is formed by patterning the transparent conductive layer through a photolithography process using a fourth mask and an etching process using a photoresist pattern. The pixel electrode 114 is electrically connected to the drain electrode 112 through the contact hole 13. In this case, indium tin oxide (ITO), tin oxide (TO: Tin Oxide), or the like is used as a material of the transparent conductive layer.

As described above, the horizontal field-applied thin film transistor array substrate and its manufacturing method according to the prior art have reduced manufacturing costs by employing four mask processes but still have high manufacturing costs due to the excessive number of processes. Yield management has a difficult problem.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

The present invention has been made to solve the above-mentioned problem, and the lateral field (In Plane Switch) type liquid crystal display device according to the present invention forms a light blocking layer patterned in the same form as the active layer pattern under the active layer by the light generated in the backlight. An object of the present invention is to effectively prevent photocurrent from being generated between a source electrode and a drain electrode in a gate-off state.

In the method of manufacturing the in-plane switch type liquid crystal display device, in forming a source electrode, a drain electrode, an active layer pattern, and a light blocking layer, a diffraction mask is used to proceed to one photomask, and a gate electrode is used. And the common electrode are simultaneously formed of one photomask, and the gate insulating layer is also etched together during the etching for the gate electrode patterning so that the pixel electrode and the drain electrode are electrically connected without forming a contact hole. It aims at manufacturing a board | substrate using three masks.

In order to achieve the above object, a structure of an in-plane switch type liquid crystal display device according to an embodiment of the present invention includes a gate wiring disposed on a substrate 201 to define a plurality of pixels as illustrated in FIGS. 4 and 5. 212 and data wiring 213; An active layer 203 formed on the substrate to form an active region, and source and drain electrodes 205 and 206 formed on the active layer; A gate insulating layer 207 formed on the source and drain electrodes and patterned in the same shape as the gate electrode 208 and the common electrode 209; A gate electrode 208 formed on the gate insulating layer and formed at a predetermined portion on the active layer, and a common electrode 209 formed on the gate insulating layer 207; And a pixel electrode 210 overlapping a predetermined portion of the drain electrode 206 and electrically connected to the drain electrode 206.

Hereinafter, the structure of the liquid crystal display device according to the present invention will be described in detail with reference to FIG. 5.

First, the semiconductor layers 203 and 204 are formed on the insulating substrate 201, and the semiconductor layer may include an active layer 203 composed of pure silicon layers and an ohmic contact layer 204 composed of silicon layers doped with impurities. have. In this case, a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced chemical vapor deposition (PECVD) method is generally used for the deposition of the semiconductor layer, and the ohmic contact layer ( 204 serves to bring the active layer 203 into contact with the source electrode 205 and the drain electrode 206 with low contact resistance.

Although not shown in FIG. 5, before forming the semiconductor layers 203 and 204 on the insulating substrate 201, a buffer layer such as a silicon oxide film (SiO 2) (not shown) is formed to form an insulating substrate in a subsequent process. Impurities such as sodium (Na) contained therein may be prevented from penetrating upwards.

In addition, a light blocking layer 202 patterned in the same shape as the active region may be formed under the active layer 203. The light blocking layer 202 may be formed using an insulating black resin, and may be formed by sequentially depositing a metal layer and an insulating layer that reflect light well, such as chromium (Cr). When the method of forming the light blocking layer 202 is a method of forming a light blocking layer by sequentially depositing a metal layer and an insulating layer, the light generated from the backlight is reflected from the metal layer and then reflected back to the liquid crystal panel by re-reflection. Since it can be induced, the brightness of the liquid crystal display can be increased .

In the structure of the liquid crystal display device, the gate electrode 208 and the common electrode 209 are formed on the same stacked structure. Therefore, as will be mentioned in the manufacturing method to be described later, it can be formed at the same time using one photomask.

In addition, in the liquid crystal display, in order to represent an image, the pixel electrode 210 must be electrically connected to the drain electrode 206 to have a predetermined potential on the pixel electrode 210 by a signal applied to the data line 213. . In the structure of the liquid crystal display according to the present invention, in order to electrically connect the drain electrode 206 and the pixel electrode 210, the contact hole is not formed as in the conventional art, and the etching process is performed to form the gate electrode 208. The gate insulating layer 207 is also etched together to expose a portion of the drain electrode 206, and then a pixel electrode 210 is formed directly on the drain electrode to electrically connect the two electrodes.

Following the description of the structure of the liquid crystal display device according to the present invention described above, the manufacturing method of the liquid crystal display device will be described in detail through a preferred embodiment as follows.

6A through 6E are cross-sectional views of process steps illustrating a method of manufacturing a liquid crystal display device according to the preferred embodiment.

In the first step, the light blocking layer 202, the semiconductor layers 203 and 204, and the metal layer 215 are deposited on a substrate 201 made of a transparent insulating material such as glass, as shown in FIG. 6A, and diffraction. Photolithography using a mask is applied to form a photoresist pattern 214 having a predetermined step. In this case, in order to prevent impurities such as sodium (Na) contained in the insulating substrate 201 from penetrating upward, depositing a buffer layer such as silicon oxide layer (SiO 2) prior to the deposition of the layers (not shown). It may be included.

The light blocking layer 202 may be formed by forming a single layer having a layer of insulating property such as black resin and blocking light, and a metal layer such as chromium (Cr) having a property of reflecting light well. And the insulating layer may be sequentially deposited.

In the photoresist pattern 214 formed by the diffraction mask used in the above process, the thickness of the photoresist applied on the source electrode 205, the drain electrode 206 and the data wiring 213 is the channel region of the active layer. It is thicker than the thickness of the photoresist applied thereon, and the remaining portions except for the region are completely exposed.

As a next step, as shown in FIG. 6B, the source electrode 205, the drain electrode 206, and the active layer pattern 203 are formed using the photoresist pattern 214 using the diffraction mask as a mask. .

In the forming of the source electrode 205, the drain electrode 206, and the active layer pattern 203, the photoresist is patterned by using a photolithography technique using a single diffraction mask, and the photo patterned by the photolithography technique. The conductive layer 215 forming the source electrode 205 and the drain electrode 206 and the active layer 203 under the conductive layer are etched using the resist as a mask, and the photoresist remaining after the etching step is partially etched. the conductive layer 215 forming the source electrode 205 and the drain electrode 206 formed on a portion of the active layer using partial photoresist and the photoresist pattern remaining after the partial ashing as a mask. It is made by etching.

In this case, the partial ashing of the photoresist described above, the photoresist applied on the source electrode 205 and the drain electrode 206 maintains a predetermined thickness after the partial ashing step. And remain, and the photoresist applied over the area forming the channel of the active layer 203 has to be completely removed after the partial ashing step.

As a result, the source electrode 205, the drain electrode 206, and the active layer pattern 203 may be simultaneously formed using the first photomask.

In the next step, the gate insulating layer 207 is formed on the entire surface of the substrate, as shown in FIG. 6C. As the material of the gate insulating layer 207, a silicon oxide film (SiO 2) or a silicon nitride film (SiO x) having excellent insulation may be used.

In the next step, as shown in FIG. 6D, a conductive layer is deposited on the gate insulating layer 207 and the gate electrode 208 and the common electrode 209 are formed through a predetermined patterning process. In this case, a photoresist pattern is formed on the conductive layer by using photolithography to form the gate electrode 208 and the common electrode 209, and the photoresist pattern is used as the conductive layer and the gate insulating layer. 207). By etching a part of the gate insulating layer 207 at the time of forming the gate electrode 208 and the common electrode 209 as described above, a process of forming a contact hole is unnecessary when the pixel electrode 210 to be described later is formed. As a result, the gate electrode 208 and the common electrode 209 may be formed by using the second photomask.

As shown in FIG. 6E, the pixel electrode 210 is formed on the substrate on which the gate electrode 208 and the common electrode 209 are formed. The pixel electrode 210 is formed by depositing a transparent metal oxide layer, such as indium tin oxide (ITO) or tin oxide (TO), through a predetermined patterning process. In this case, the patterning is performed by leaving the transparent conductive layer only in the region where the pixel electrode and the common electrode are to be formed and removing the remaining portions. As a result, an upper portion of the drain electrode 206 may be electrically connected to the pixel electrode 210, and a transparent conductive layer 211 may be formed on the metal layer constituting the common electrode to protect the metal layer. . This completes the process using the third photomask and completes the manufacturing process of the thin film transistor array substrate.

As described above, the manufacturing method of the liquid crystal display device according to the present invention requires three photomasks as a whole, thereby reducing the number of photomasks.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

As described above, the in-plane switch type liquid crystal display device according to the present invention forms a light blocking layer patterned in the same shape as the active layer pattern under the active layer, and the source electrode in the gate-off state by the light generated in the backlight. Photoelectric current can be effectively prevented between the drain electrodes.

In the method of manufacturing the in-plane switch type liquid crystal display device, the source electrode, the drain electrode, the active layer pattern, and the light blocking layer are formed in one mask by using a diffraction mask and are common to the gate electrode. The electrode is also formed simultaneously with one mask, and the gate insulating layer is also etched during the etching for the gate electrode patterning so that the pixel electrode and the drain electrode are electrically connected without forming a contact hole, thereby forming a liquid crystal display device. A thin film transistor array substrate can be manufactured using three photomasks. Therefore, the manufacturing cost of the liquid crystal display device can be reduced due to the reduction of the photomask required for the process, and the production yield can be easily managed.

Claims (12)

A gate wiring and a data wiring disposed on the substrate to define a plurality of pixels; A semiconductor layer formed on the substrate to form an active layer pattern, and source and drain electrodes formed on the semiconductor layer; A gate insulating layer formed on the source and drain electrodes and patterned in the same shape as the gate electrode and the common electrode; A gate electrode formed on the gate insulating layer and formed at a predetermined portion on the semiconductor layer, and a common electrode formed on the gate insulating layer; And And a pixel electrode overlapping a predetermined portion of the drain electrode and electrically connected to the drain electrode. The method of claim 1, The light blocking layer is formed under the semiconductor layer. The method of claim 2, The light blocking layer is a liquid crystal display device comprising a black resin. The method of claim 2, The light blocking layer is a liquid crystal display device, characterized in that the metal layer having a high reflectance to light, and the insulating layer is sequentially stacked. Forming a semiconductor layer on the insulating substrate; Forming a conductive layer on the active layer; Patterning the semiconductor layer and the conductive layer to form an active layer pattern, a source electrode and a drain electrode; Forming a gate insulating layer on a substrate including the active layer pattern, a source electrode and a drain electrode; Depositing a conductive layer on the gate insulating layer; Forming a gate electrode and a common electrode on the conductive layer and the gate insulating layer formed on the gate insulating layer through a predetermined patterning process; And depositing a conductive layer on a substrate on which the gate electrode and the common electrode are formed, and forming a pixel electrode electrically connected to the drain electrode through a predetermined patterning process. The method of claim 5, And forming a light blocking layer prior to forming the semiconductor layer. The method of claim 5, Forming the active layer pattern, the source electrode and the drain electrode, Patterning the photoresist using a photolithography technique using one diffraction mask; Etching a conductive layer forming a source electrode and a drain electrode using a photoresist patterned by the photolithography mask and a semiconductor layer below the conductive layer; A partial ashing step after the etching step; And etching the conductive layer forming the source electrode and the drain electrode formed on the partial region of the active layer by using the photoresist pattern remaining after the partial ashing as a mask. Manufacturing method. The method of claim 6, Forming the active layer pattern, the source electrode and the drain electrode, Patterning the photoresist using a photolithography technique using one diffraction mask; Etching a conductive layer forming a source electrode and a drain electrode using a photoresist patterned by the photolithography mask and a semiconductor layer below the conductive layer; A partial ashing step after the etching step; And etching the conductive layer forming a source electrode and a drain electrode formed on a portion of the semiconductor layer using the photoresist pattern remaining after the partial ashing as a mask. Method of manufacturing the device. The method of claim 6, The forming of the light blocking layer is performed by forming a black resin. The method of claim 6, Forming the light blocking layer is a method of manufacturing a liquid crystal display device, characterized in that by forming a metal layer, such as Cr (chromium), and an insulating layer in sequence. The method according to claim 7 or 8, The photoresist pattern formed by the diffraction mask is, The thickness of the photoresist applied on the source electrode and the drain electrode is thicker than the thickness of the photoresist applied on the region forming the channel of the semiconductor layer, and the remaining portion including the pixel electrode region is completely exposed. Method of manufacturing the device. The method according to claim 7 or 8, The partial ashing step, The photoresist applied on the source electrode and the drain electrode remains with a predetermined thickness after the partial ashing step, and the photoresist applied on the region forming the channel of the semiconductor layer is partially ashed ( Method of manufacturing a liquid crystal display device characterized in that completely removed after the partial ashing) step.

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