KR20070072115A - Liquid crystal display device and fabricating method - Google Patents

Abstract

An LCD(Liquid Crystal Display) and a manufacturing method are provided to reduce an optical current and the number of photomasks to be used by forming a light blocking layer under an active layer and manufacturing a thin film transistor array substrate with use of two masks. Gate lines and data lines are disposed on a substrate to define a plurality of pixels. A semiconductor layer(203,204) is formed on the substrate to form an active layer pattern, source and drain electrodes(205,206) are formed on the semiconductor layer, and a pixel electrode(210) is formed on the same stacked structure as the source and drain electrodes. A gate insulating layer(207) is formed on the substrate including the source and drain electrodes, and is opened at a data pad area. A gate electrode is formed on the gate insulating layer, and is formed at a predetermined portion on the active layer. A common electrode(209) is formed on the same stacked structure as the gate electrode.

Description

Liquid crystal display device and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND FABRICATING METHOD}

1 is a plan view showing a liquid crystal display device according to the prior art

Figure 2 is a cross-sectional view showing a liquid crystal display device according to the prior art (A-A 'cross section of Figure 1)

3A to 3D are cross-sectional views showing a method of manufacturing a liquid crystal display device according to the prior art, step by step, using the cut line A-A 'of FIG.

4 is a plan view showing a liquid crystal display device of the present invention.

5 is a cross-sectional view showing a liquid crystal display device according to the present invention (A-A 'cut section of Figure 4)

FIG. 6 is a cross-sectional view of a shadow mask and a data pad part used in depositing a gate insulating layer during a manufacturing process of a liquid crystal display device according to the present invention. FIG.

7A to 7D are cross-sectional views showing the manufacturing method of the liquid crystal display device of the present invention step by step using the cut line A-A 'of FIG.

** Explanation of symbols for main parts of drawings **

202: light blocking layer

203, 204: active layer, ohmic contact layer

205 and 206: source electrode and drain electrode

210: pixel electrode

207: gate insulating layer

208: gate electrode

209: common electrode

214: shadow mask

215: data pad

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-plane switch type liquid crystal display device and a manufacturing method thereof, and more particularly, to a structure of a liquid crystal display device capable of reducing the number of process masks and a method of manufacturing the same.

A liquid crystal display device is a display device that displays an image by adjusting the light transmittance of the liquid crystal using an electric field generated by a voltage applied to a predetermined electrode, and is a vertical electric field and a horizontal electric field in accordance with the direction of the electric field driving the liquid crystal. It is divided into switch type.

In the vertical field type liquid crystal display device, the common electrode formed on the upper substrate and the pixel electrode formed on the lower substrate are disposed to face each other to drive the liquid crystal of TN (Twisted Nemastic) mode by a vertical electric field formed therebetween. The vertical field type liquid crystal display device has a large aperture ratio, but has a narrow viewing angle of about 90 degrees.

In contrast, the in-plane switch type liquid crystal display device drives the liquid crystal by a horizontal electric field formed between the pixel electrode and the common electrode arranged side by side on the lower substrate. Such an in-plane switch type liquid crystal display device has a wide viewing angle of about 160 degrees. Hereinafter, an in-plane switch type liquid crystal display device will be described in detail.

An in-plane switch type liquid crystal display device is composed of a thin film transistor array substrate (lower substrate), a color filter substrate (upper substrate), and liquid crystals filled between the substrates bonded to each other. The thin film transistor array substrate includes a plurality of signal wirings for forming a horizontal electric field in each unit pixel, a thin film transistor, and an alignment layer coated for liquid crystal alignment. The color filter substrate is composed of a color filter for color implementation, a black matrix for preventing light leakage, and an alignment film coated for liquid crystal alignment.

The photolithography technique is used to manufacture the thin film transistor array substrate constituting the liquid crystal display device, and the application of the photolithography technique to a manufacturing process requires a large manufacturing cost and difficult yield management. In order to solve the above problems, a 'low mask' process to be applied to a method of manufacturing a thin film transistor array substrate has been actively studied, and a manufacturing method of reducing the total number of process masks to four has recently emerged.

FIG. 1 is a plan view illustrating a thin film transistor array substrate of an in-plane switch type liquid crystal display device using four mask processes according to the prior art, and FIG. 2 is a planar view of a thin film transistor array substrate showing AA ′ cutting planes of FIG. 1. It is a cross section.

1 and 2, the thin film transistor array substrate of the in-plane switch type liquid crystal display device according to the related art includes a gate wiring 115 and a data wiring (crossed over an insulating substrate 101). 116 and the common wiring 117, a thin film transistor formed in each pixel region, a pixel electrode 114 and a common electrode 107 formed to form a horizontal electric field in each pixel region. In addition to the above components, a storage capacitor (not shown) may be formed at an overlapping portion of the pixel electrode 114 and the common wiring 117.

First, the wirings for supplying signals to the respective wirings will be described. The gate wiring 115 supplies a gate signal to the gate electrode 104 of the thin film transistor, and the data wiring 116 connects the drain electrode 112 of the thin film transistor. The pixel signal is supplied to the pixel electrode 114, and the common wiring 117 supplies a reference voltage for driving the liquid crystal to the common electrode 107 with the pixel region interposed therebetween.

Next, the thin film transistor serves to keep the pixel signal of the data line 116 charged and maintained in the pixel electrode 114 in response to the gate signal of the gate line 115. ), The gate electrode 104 electrically connected to the gate electrode 104, the source electrode 111 electrically connected to the data wiring 116, the drain electrode 112 electrically connected to the pixel electrode 114, the gate electrode 104 and the gate insulating layer. It is composed of an active layer 109 overlapping with the gap 108 therebetween to form a channel between the source electrode 111 and the drain electrode 112. In this case, the active layer 109 is formed to overlap the data line 116, the data pad lower electrode (not shown), and the storage electrode (not shown), and the data line 116, on the active layer 109. A source electrode 111, a drain electrode 112, a data pad electrode (not shown) and a storage electrode (not shown) and an ohmic contact layer 110 for ohmic contact are further formed.

Next, referring to the remaining components including the pixel electrode, the pixel electrode 114 is electrically connected to the drain electrode 112 of the thin film transistor through a contact hole penetrating through the passivation layer 113 and formed in the pixel region. The electrode 107 is electrically connected to the common wiring 117 to be formed in the pixel area.

Accordingly, a horizontal electric field is formed between the pixel electrode 114 supplied with the pixel signal through the thin film transistor and the common electrode 107 supplied with the reference voltage through the common wiring 117. The horizontal electric field causes the liquid crystal molecules arranged in the horizontal direction between the thin film transistor array substrate and the color filter array substrate to rotate by dielectric anisotropy, so that the light transmittance that passes through the pixel region varies depending on the degree of rotation of the liquid crystal molecules. As a result, an image is realized.

However, one of the problems of the thin film transistor array substrate of the liquid crystal display device according to the related art is that light incident from the backlight reaches an active layer constituting the thin film transistor of the liquid crystal display device, so that photocurrent may be generated. When the photocurrent occurs, the off current of the thin film transistor is increased to cause mura on the screen display, thereby degrading the performance of the liquid crystal display.

Referring to FIGS. 3A to 3D, a manufacturing method using a four-mask process among the manufacturing methods of a thin film transistor array substrate according to the related art having the above configuration will be described below.

First, as shown in FIG. 3A, a gate electrode 104 and a gate pad electrode (not shown) are formed on an insulating substrate 101 using a first mask process.

In detail, the first metal layer 102 and the second metal layer 103 are sequentially deposited on the insulating substrate 101 using a deposition method such as a sputtering method to form a metal layer forming a double layer. Subsequently, the metal layers are patterned by a photolithography process using a first mask and an etching process using a photoresist pattern to form a gate electrode 104 and a common electrode 107. In this case, an aluminum-based metal is mainly used as the first metal layer 102, and a metal such as chromium (Cr) or molybdenum (Mo) is mainly used as the second metal layer 103.

As shown in FIG. 3B, the gate insulating layer 108 is formed on the insulating substrate 101 on which the gate electrode 104 and the common electrode 107 are formed. The semiconductor pattern including the active layer 109 and the ohmic contact layer 110, the source electrode 111, and the drain electrode 112 are formed on the gate insulating layer 108 using the second mask process.

In detail, the plasma enhanced chemical vapor deposition (PECVD), sputtering, or the like is formed on the lower substrate 101 on which the gate electrode 104 and the common electrode 107 are formed. The gate insulating layer 108, the active layer 109, the ohmic contact layer 110, the source electrode and the drain electrode layer are sequentially formed through the deposition method of. In this case, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the gate insulating layer 108, and amorphous silicon without doping impurities is used as the active layer 109, and the ohmic contact layer 110 is used. Amorphous silicon doped with silver impurities is used. Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy) and the like are used for the source and drain electrode layers.

Subsequently, a photoresist pattern is formed on the source and drain electrode layers by a photolithography process using a second mask. In this case, by using a diffraction mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel region is formed to have a thickness lower than that of the other region.

The source electrode 111 and the drain electrode 112 are formed through a wet etching process using photoresist patterns having different heights of the channel region. Subsequently, the first and second semiconductor layers 109 and 110 are simultaneously patterned by a dry etching process using the same photoresist pattern to form the active layer 109 and the ohmic contact layer 110, and partial ashing. After the photoresist pattern having the relatively low height of the channel region is removed by the process, the source and drain electrode layers and the ohmic contact layer 110 on the channel region are etched by the dry etching process. Next, the photoresist pattern remaining in the strip process is removed.

In the next step, as shown in FIG. 3C, the protective layer 113 including the contact hole is formed on the substrate on which the source and drain electrodes 111 and 112 are formed by using a third mask process.

In detail, the protective layer 113 is formed on the substrate on which the source and drain electrodes 111 and 112 are formed by a deposition method such as PECVD. Subsequently, the protective layer 113 is patterned by a photolithography process using a third mask and an etching process using a photoresist pattern to form contact holes. The contact hole is formed on the protective layer 113 to expose a portion of the drain electrode 112. In this case, an inorganic insulating material such as the gate insulating layer 108 or an acryl-based organic compound having a low dielectric constant may be used as the material of the protective layer 113.

As a next step, the pixel electrode 114 is formed on the passivation layer 113 using a fourth mask process as shown in FIG. 3D.

In detail, the transparent conductive layer is deposited on the protective layer 113 by a deposition method such as sputtering. Subsequently, the pixel electrode 114 is formed by patterning the transparent conductive layer through a photolithography process using a fourth mask and an etching process using a photoresist pattern. The pixel electrode 114 is electrically connected to the drain electrode 112 through the contact hole 13. In this case, indium tin oxide (ITO), tin oxide (TO: Tin Oxide), or the like is used as a material of the transparent conductive layer.

As described above, the transverse electric field type thin film transistor array substrate and its manufacturing method according to the prior art have reduced manufacturing costs by employing four mask processes but still have a large number of processes, resulting in high manufacturing costs and yield management. Has a difficult problem.

Other objects and features of the present invention will be described in the configuration and claims of the invention to be described later.

The present invention has been made to solve the above-mentioned problem, and the lateral field (In Plane Switch) type liquid crystal display device according to the present invention forms a light blocking layer patterned in the same form as the active layer pattern under the active layer by the light generated in the backlight. An object of the present invention is to effectively prevent photocurrent from being generated between a source electrode and a drain electrode in a gate-off state.

In addition, as a method of manufacturing the in-plane switch type liquid crystal display device, in forming a source electrode, a drain electrode, a pixel electrode, an active layer pattern, and a light blocking layer, a diffraction mask is used to proceed to one photomask. In addition, the gate electrode and the common electrode are simultaneously formed with one photomask, and when the gate insulating layer is deposited, a thin film transistor array is prevented from depositing the gate insulating layer on the data pad area by using a shadow mask. It is an object to manufacture a substrate using two masks.

In order to achieve the above object, a structure of an in-plane switch type liquid crystal display device according to an embodiment of the present invention includes a gate wiring and a data wiring disposed on a substrate to define a plurality of pixels as shown in FIGS. 4 and 5. ; An active layer formed on the substrate to form an active layer pattern, source and drain electrodes formed on the active layer, and pixel electrodes formed on the same stacked structure as the source and drain electrodes; A gate insulating layer formed on the substrate on which the source and drain electrodes are formed, and the data pad region being open; And a gate electrode formed on the gate insulating layer and formed at a predetermined portion on the active layer, and a common electrode formed on the same stacked structure as the gate electrode.

Hereinafter, the structure of the liquid crystal display device according to the present invention will be described in detail with reference to FIG. 5.

First, a semiconductor layer is formed on an insulating substrate 201, and the semiconductor layer is formed of an active layer 203 made of pure silicon layer and an ohmic contact layer 204 made of silicon layer doped with impurities. In this case, a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced chemical vapor deposition (PECVD) method is generally used for the deposition of the semiconductor layer, and the ohmic contact layer 204 is used. ) Serves to bring the active layer 203 into contact with the source electrode 205 and the drain electrode 206 with low contact resistance.

Although not shown in FIG. 5, before forming the semiconductor layers 203 and 204 on the insulating substrate 201, a buffer layer such as a silicon oxide film (SiO 2) (not shown) is formed to form an insulating substrate in a subsequent process. Impurities such as sodium (Na) contained in 201 may be prevented from penetrating upward.

In addition, a light blocking layer 202 patterned in the same shape as the active layer pattern may be formed under the active layer 203. The light blocking layer 202 may be formed using an insulating black resin, and may be formed by sequentially depositing a metal layer and an insulating layer that reflect light well, such as chromium (Cr). When the method of forming the light blocking layer 202 is a method of forming a light blocking layer by sequentially depositing a metal layer and an insulating layer, the light generated from the backlight is reflected from the metal layer and then reflected back to the liquid crystal panel by re-reflection. Since it can be induced, the brightness of the liquid crystal display can be increased.

In the structure of the liquid crystal display device, the source electrode 205, the drain electrode 206, and the pixel electrode 210 are formed on the same stacked structure. In this case, a data pad 215 is formed at the end of the data line 212 electrically connected to the source electrode 205 and receives a data signal from a drive IC (not shown) connected outside the panel. In addition, the gate electrode 208 and the common electrode 209 may be formed on the same stacked structure, and may be simultaneously formed using one photomask.

In addition, as will be described later in the manufacturing method which will be described later with reference to FIG. 6, in order to prevent the gate insulating layer 207 from being deposited on the data pad 215, the area of the data pad 215 is formed when the gate insulating layer 207 is deposited. A hidden shadow mask 214 is used.

In this case, the gate electrode 208 and the common electrode 209 may be formed of a transparent conductive layer such as indium tin oxide (ITO) or tin oxide (TO: tin oxide), and have high conductivity (Cu). ) Or a metal layer such as aluminum (Al) and a conductive layer such as indium tin oxide (ITO) or tin oxide (TO: Tin Oxide) may be formed as a multilayer. The reason for depositing a conductive layer such as ITO on a metal layer such as copper (Cu) or aluminum (Al) is that a pad terminal (not shown) formed on the outer side of the pixel portion of the thin film transistor array panel has an FPC (Flexible Printed). After the electrical connection with the circuit) and thermocompression bonding, it is to fall without damage to the pad terminal (not shown in the drawing) during rework due to the failure.

Following the description of the structure of the liquid crystal display device according to the present invention described above, the manufacturing method of the liquid crystal display device will be described in detail through a preferred embodiment as follows.

7A to 7D are cross-sectional views of process steps illustrating a method of manufacturing a liquid crystal display device according to the preferred embodiment.

First, as illustrated in FIG. 7A, the light blocking layer 202, the semiconductor layers 203 and 204, and the metal layer 217 are deposited on a substrate 201 made of a transparent insulating material such as glass, and then photoetched using a diffraction mask. The technique is applied to form the photoresist pattern 216 having a predetermined step. In this case, in order to prevent impurities such as sodium (Na) contained in the insulating substrate 201 from penetrating upward, depositing a buffer layer such as silicon oxide layer (SiO 2) prior to the deposition of the layers (not shown). It may be included.

The light blocking layer 202 may be formed by blocking light and forming an insulating layer as a single layer, such as black resin, and a metal layer and an insulating layer, such as chromium (Cr), having a property of reflecting light well. It may consist of depositing in turn.

The photoresist pattern 216 formed by the diffraction mask used in the above process is a photoresist applied on the source electrode 205, the drain electrode 206, the pixel electrode 210 and the data wiring 212. The thickness is thicker than the thickness of the photoresist applied over the region forming the channel of the active layer, and the remaining portions except for the region are completely exposed.

In the next step, as shown in FIG. 7B, the source electrode 205, the drain electrode 206, the pixel electrode 210 and the active layer pattern may be formed using the photoresist pattern 216 using the diffraction mask as a mask. Form.

In the forming of the source electrode 205, the drain electrode 206, the pixel electrode 210, and the active layer pattern, the photoresist is patterned using a photolithography technique using one diffraction mask, and the photoresist is patterned. Using the photoresist as a mask, the conductive layer 217 forming the source electrode 205, the drain electrode 206, and the pixel electrode 210 and the semiconductor layers 203 and 204 under the conductive layer 217 are etched. And a partial ashing of the photoresist after the etching step, and using the photoresist pattern remaining after the partial ashing as a mask on the partial region of the semiconductor layer; The conductive layer 217 forming the drain electrode 206 is etched.

In this case, the partial ashing of the photoresist described above is performed after the partial ashing step of the photoresist applied on the source electrode 205, the drain electrode 206, and the pixel electrode 210. The photoresist applied over the area forming the channel of the semiconductor layers 203 and 204, which remains at a predetermined thickness in, must be completely removed after the partial ashing step.

As a result, the source electrode 205, the drain electrode 206, the pixel electrode 210, and the active layer pattern may be simultaneously formed using the first photomask.

In the next step, the gate insulating layer 207 is formed on the entire surface of the substrate, as shown in FIG. 7C. In this case, since the data signal must be applied to the data pad (not shown) constituting the end of the data line 212 through an external drive IC, the gate insulating layer 207 should not be deposited.

In order to prevent the gate insulating layer 207 from being deposited on the data pad as described above, the area of the data pad 215 is covered by the shadow mask 214 when the gate insulating layer 207 is deposited as shown in FIG. 6. You must lose.

As a next step, as shown in FIG. 7D, a conductive layer is deposited on the gate insulating layer 207 and patterned to form the gate electrode 208 and the common electrode 209. In this case, as the conductive layer, a transparent metal oxide layer such as indium tin oxide (ITO) or tin oxide (TO: Tin Oxide) may be used, and in this case, it has an advantageous effect in terms of aperture ratio. In addition, the conductive layer may be composed of a multilayer of a metal layer such as copper (Cu) or aluminum (Al) and a metal oxide layer such as indium tin oxide (ITO) or tin oxide (TO).

A second photomask is used in the process of patterning the conductive layer to form the gate electrode 208 and the common electrode 209. Therefore, the manufacturing method of the liquid crystal display device according to the present invention requires two photomasks as a whole can greatly reduce the number of photomasks compared to the prior art.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

As described above, the in-plane switch type liquid crystal display device according to the present invention forms a light blocking layer patterned in the same shape as the active layer pattern under the active layer, and the source electrode in the gate-off state by the light generated in the backlight. Photoelectric current can be effectively prevented between the drain electrodes.

In addition, in the method of manufacturing the in-plane switch type liquid crystal display device, the source electrode, the drain electrode, the pixel electrode, the active layer pattern, and the light blocking layer are formed using a diffraction mask and proceed with one mask. The electrode and the common electrode may be simultaneously formed with one mask, and when the gate insulating layer is deposited, a shadow mask may be prevented from being deposited on the data pad region by using a shadow mask. Therefore, since the thin film transistor array substrate can be manufactured using two photomasks, the manufacturing cost of the liquid crystal display device can be reduced and the production yield can be easily managed.

Claims (29)

A gate wiring and a data wiring disposed on the substrate to define a plurality of pixels; A semiconductor layer formed on the substrate to form an active layer pattern, source and drain electrodes formed on the semiconductor layer, and a pixel electrode formed on the same stacked structure as the source and drain electrodes; A gate insulating layer formed on the substrate on which the source and drain electrodes are formed, and the data pad region being open; And And a common electrode formed on the gate insulating layer and formed on a predetermined portion of the active layer, and a common electrode formed on the same stacked structure as the gate electrode. The method of claim 1, The light blocking layer is formed under the semiconductor layer. The method of claim 1, The gate electrode is a liquid crystal display device, characterized in that composed of a transparent conductive material such as indium tin oxide (Indium Tin Oxide). The method of claim 1, The gate electrode is a liquid crystal display device comprising a metal layer and a layer made of a transparent conductive material such as indium tin oxide or tin oxide are sequentially stacked. The method of claim 1, The semiconductor layer is a liquid crystal display device characterized in that the pure silicon layer and the impurity doped silicon layer is formed by sequentially stacked.       The method of claim 2, The light blocking layer is a liquid crystal display device comprising a black resin. The method of claim 2, The light blocking layer is a liquid crystal display device comprising a metal layer such as chromium (Cr) having a high reflectance of light and an insulating layer are sequentially stacked. Forming a semiconductor layer on the substrate; Forming a conductive layer on the semiconductor layer; Patterning the semiconductor layer and the conductive layer to form an active layer pattern, a source electrode, a drain electrode, and a pixel electrode; Forming a gate insulating layer by opening a data pad region on a substrate including the active layer pattern, a source electrode, a drain electrode, and a pixel electrode; And Forming a conductive layer on the gate insulating layer, and forming a gate electrode and a common electrode through patterning. The method of claim 8, A method of manufacturing a liquid crystal display device comprising the step of forming a buffer layer on the substrate. The method of claim 8, Forming a light blocking layer on the substrate, characterized in that it comprises a liquid crystal display device. The method of claim 8, Forming the source electrode, the drain electrode, the pixel electrode and the active layer pattern, Forming a photoresist pattern using one diffraction mask; Etching a conductive layer forming a source electrode, a drain electrode, and a pixel electrode with the photoresist pattern and a semiconductor layer below the conductive layer; Partial ashing step; And And forming a source electrode and a drain electrode with the photoresist pattern remaining after the partial ashing. The method of claim 9, Forming the source electrode, the drain electrode, the pixel electrode and the active layer pattern, Forming a photoresist pattern using one diffraction mask; Etching a conductive layer forming a source electrode, a drain electrode, and a pixel electrode with the photoresist pattern and a semiconductor layer below the conductive layer; Partial ashing step; And And forming a source electrode and a drain electrode with a photoresist pattern remaining after the partial ashing. The method of claim 10, Forming the source electrode, the drain electrode, the common electrode, the active layer pattern and the light blocking layer, Forming a photoresist pattern using one diffraction mask; Etching the conductive layer forming the source electrode, the drain electrode, and the pixel electrode using the photoresist pattern, the semiconductor layer and the light blocking layer below the conductive layer; Partial ashing step; And And forming a source electrode and a drain electrode with a photoresist pattern remaining after the partial ashing. The method of claim 10, The light blocking layer is a manufacturing method of a liquid crystal display device, characterized in that the black resin. The method of claim 10, The light blocking layer is a method of manufacturing a liquid crystal display device, characterized in that the metal layer, such as chromium (Cr), and the insulating layer is sequentially stacked. The method according to any one of claims 8 to 15, The step of forming a gate insulating layer by opening a data pad region on a substrate including the active layer pattern, the source electrode, the drain electrode, and the pixel electrode, A method of manufacturing a liquid crystal display device, wherein the gate pad region is covered and deposited by using a shadow mask when the gate insulating layer is deposited. The method according to any one of claims 11 to 13, The photoresist pattern formed by the diffraction mask is, The thickness of the photoresist applied on the source electrode, the drain electrode, and the pixel electrode is thicker than the thickness of the photoresist applied on the region forming the channel of the semiconductor layer, and the remaining region including the common electrode region is completely exposed. Method of manufacturing a liquid crystal display device. The method of claim 17, The step of forming a gate insulating layer by opening a data pad region on a substrate including the active layer pattern, the source electrode, the drain electrode, and the pixel electrode, A method of manufacturing a liquid crystal display device, wherein the gate pad region is covered and deposited by using a shadow mask when the gate insulating layer is deposited. The method according to any one of claims 11 to 13, The partial ashing step, The photoresist applied on the source electrode, the drain electrode, and the pixel electrode remains at a predetermined thickness after the partial ashing step, and the photoresist applied on the region forming the channel of the semiconductor layer is partially A method of manufacturing a liquid crystal display device, characterized in that completely removed after the ashing (partial ashing) step. The method of claim 19, The step of forming a gate insulating layer by opening a data pad region on a substrate including the active layer pattern, the source electrode, the drain electrode, and the pixel electrode, A method of manufacturing a liquid crystal display device, wherein the gate pad region is covered and deposited by using a shadow mask when the gate insulating layer is deposited. The method according to any one of claims 8 to 15, Forming the gate electrode and the common electrode, A transparent conductive layer such as indium tin oxide or tin oxide is formed on the gate insulating layer, and the gate layer and the common electrode are simultaneously formed by patterning the conductive layer using one photomask. Method for manufacturing a liquid crystal display device, characterized in that. The method of claim 21, The step of forming a gate insulating layer by opening a data pad region on a substrate including the active layer pattern, the source electrode, the drain electrode, and the pixel electrode, A method of manufacturing a liquid crystal display device, wherein the gate pad region is covered and deposited by using a shadow mask when the gate insulating layer is deposited. The method according to any one of claims 8 to 15, Forming the gate electrode and the common electrode, A metal layer and a transparent conductive layer such as indium tin oxide or tin oxide are sequentially formed on the gate insulating layer, and the metal layer and the transparent conductive layer are patterned using one photomask to form a gate electrode. And a common electrode are formed at the same time. The method of claim 23, wherein The step of forming a gate insulating layer by opening a data pad region on a substrate including the active layer pattern, the source electrode, the drain electrode, and the pixel electrode, A method of manufacturing a liquid crystal display device, wherein the gate pad region is covered and deposited by using a shadow mask when the gate insulating layer is deposited. The method of claim 17, Forming the gate electrode and the common electrode, A transparent conductive layer such as indium tin oxide or tin oxide is formed on the gate insulating layer, and the gate layer and the common electrode are simultaneously formed by patterning the conductive layer using one photomask. Method for manufacturing a liquid crystal display device, characterized in that. The method of claim 17, Forming the gate electrode and the common electrode, A metal layer and a transparent conductive layer such as indium tin oxide or tin oxide are sequentially formed on the gate insulating layer, and the metal layer and the transparent conductive layer are patterned using one photomask to form a gate electrode. And a common electrode are formed at the same time. The method of claim 18, Forming the gate electrode and the common electrode, A transparent conductive layer such as indium tin oxide or tin oxide is formed on the gate insulating layer, and the gate layer and the common electrode are simultaneously formed by patterning the conductive layer using one photomask. Method for manufacturing a liquid crystal display device, characterized in that. The method of claim 18, Forming the gate electrode and the common electrode, A transparent conductive layer such as indium tin oxide or tin oxide is formed on the gate insulating layer, and the gate layer and the common electrode are simultaneously formed by patterning the conductive layer using one photomask. Method for manufacturing a liquid crystal display device, characterized in that. The method according to any one of claims 25 to 28, The step of forming a gate insulating layer by opening a data pad region on a substrate including the active layer pattern, the source electrode, the drain electrode, and the pixel electrode, A method of manufacturing a liquid crystal display device, wherein the gate pad region is covered and deposited by using a shadow mask when the gate insulating layer is deposited.

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