KR20070062534A - 저밀도 패리티 체크(ldpc) 디코더 - Google Patents
저밀도 패리티 체크(ldpc) 디코더 Download PDFInfo
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- KR20070062534A KR20070062534A KR1020077007394A KR20077007394A KR20070062534A KR 20070062534 A KR20070062534 A KR 20070062534A KR 1020077007394 A KR1020077007394 A KR 1020077007394A KR 20077007394 A KR20077007394 A KR 20077007394A KR 20070062534 A KR20070062534 A KR 20070062534A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1168—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices wherein the sub-matrices have column and row weights greater than one, e.g. multi-diagonal sub-matrices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Multimedia (AREA)
- Algebra (AREA)
- Computing Systems (AREA)
- Error Detection And Correction (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US61541804P | 2004-10-01 | 2004-10-01 | |
| US60/615,418 | 2004-10-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20070062534A true KR20070062534A (ko) | 2007-06-15 |
Family
ID=35414744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020077007394A Ceased KR20070062534A (ko) | 2004-10-01 | 2005-09-19 | 저밀도 패리티 체크(ldpc) 디코더 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20080104474A1 (enExample) |
| EP (1) | EP1800408A1 (enExample) |
| JP (1) | JP2008515342A (enExample) |
| KR (1) | KR20070062534A (enExample) |
| CN (1) | CN101032084B (enExample) |
| BR (1) | BRPI0515948A (enExample) |
| WO (1) | WO2006055086A1 (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101477925B1 (ko) * | 2013-10-08 | 2014-12-30 | 세종대학교산학협력단 | Ldpc 복호기를 이용한 데이터 경로 설정 방법 및 이를 위한 ldpc 복호기 |
| KR102857926B1 (ko) * | 2024-04-15 | 2025-09-15 | 한국과학기술원 | Ldpc 코드의 경판정 성질을 활용한 dvb-s2 표준 ldpc 반복 복호의 종료 기준 설계 방법 및 시스템 |
Families Citing this family (56)
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| KR101196917B1 (ko) * | 2005-12-01 | 2012-11-05 | 톰슨 라이센싱 | 저밀도 패리티 체크 코딩된 신호를 디코딩하기 위한 장치및 방법 |
| JP4807063B2 (ja) * | 2005-12-20 | 2011-11-02 | ソニー株式会社 | 復号装置、制御方法、およびプログラム |
| KR101154995B1 (ko) * | 2006-07-14 | 2012-06-15 | 엘지전자 주식회사 | Ldpc 부호화를 수행하는 방법 |
| US7895500B2 (en) * | 2006-07-28 | 2011-02-22 | Via Telecom Co., Ltd. | Systems and methods for reduced complexity LDPC decoding |
| JP4283829B2 (ja) * | 2006-08-17 | 2009-06-24 | 株式会社モバイルテクノ | 低密度パリティチェック符号復号装置 |
| WO2008034289A1 (en) * | 2006-09-18 | 2008-03-27 | Juntan Zhang | Bit mapping scheme for an ldpc coded 32apsk system |
| US20110173509A1 (en) * | 2006-09-18 | 2011-07-14 | Availink, Inc. | Bit mapping scheme for an ldpc coded 16apsk system |
| US8359522B2 (en) | 2007-05-01 | 2013-01-22 | Texas A&M University System | Low density parity check decoder for regular LDPC codes |
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| JP5120862B2 (ja) * | 2008-02-18 | 2013-01-16 | サムスン エレクトロニクス カンパニー リミテッド | 低密度パリティ検査符号を使用する通信システムのチャネル符号化装置及びその方法 |
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| CN102077471B (zh) * | 2008-07-04 | 2014-03-12 | 三菱电机株式会社 | 校验矩阵生成装置、校验矩阵生成方法、校验矩阵生成程序、发送装置、接收装置以及通信系统 |
| US8219873B1 (en) | 2008-10-20 | 2012-07-10 | Link—A—Media Devices Corporation | LDPC selective decoding scheduling using a cost function |
| KR101733506B1 (ko) * | 2009-01-23 | 2017-05-10 | 엘지전자 주식회사 | 신호 송수신 장치 및 방법 |
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| CN102594365B (zh) * | 2012-02-29 | 2015-02-18 | 中山大学 | 一种ldpc码的动态异步bp译码方法 |
| CN103684474B (zh) * | 2012-08-31 | 2016-08-17 | 中国科学院上海高等研究院 | 一种高速ldpc译码器的实现方法 |
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| US20150227419A1 (en) * | 2014-02-12 | 2015-08-13 | Kabushiki Kaisha Toshiba | Error correction decoder based on log-likelihood ratio data |
| CN104124980B (zh) * | 2014-07-16 | 2018-04-20 | 上海交通大学 | 适合连续变量量子密钥分发的高速秘密协商方法 |
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| KR102287625B1 (ko) * | 2015-02-16 | 2021-08-10 | 한국전자통신연구원 | 길이가 64800이며, 부호율이 2/15인 ldpc 부호어 및 4096-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
| KR102287627B1 (ko) * | 2015-02-16 | 2021-08-10 | 한국전자통신연구원 | 길이가 64800이며, 부호율이 4/15인 ldpc 부호어 및 4096-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
| KR102287623B1 (ko) * | 2015-02-16 | 2021-08-10 | 한국전자통신연구원 | 길이가 64800이며, 부호율이 4/15인 ldpc 부호어 및 1024-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
| KR102287620B1 (ko) * | 2015-02-16 | 2021-08-10 | 한국전자통신연구원 | 길이가 64800이며, 부호율이 2/15인 ldpc 부호어 및 1024-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
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| US7178080B2 (en) * | 2002-08-15 | 2007-02-13 | Texas Instruments Incorporated | Hardware-efficient low density parity check code for digital communications |
| US7162684B2 (en) * | 2003-01-27 | 2007-01-09 | Texas Instruments Incorporated | Efficient encoder for low-density-parity-check codes |
| KR100996029B1 (ko) * | 2003-04-29 | 2010-11-22 | 삼성전자주식회사 | 저밀도 패리티 검사 코드의 부호화 장치 및 방법 |
| JP4225163B2 (ja) * | 2003-05-13 | 2009-02-18 | ソニー株式会社 | 復号装置および復号方法、並びにプログラム |
| KR100809619B1 (ko) * | 2003-08-26 | 2008-03-05 | 삼성전자주식회사 | 이동 통신 시스템에서 블록 저밀도 패러티 검사 부호부호화/복호 장치 및 방법 |
| US7260763B2 (en) * | 2004-03-11 | 2007-08-21 | Nortel Networks Limited | Algebraic low-density parity check code design for variable block sizes and code rates |
| US7281192B2 (en) * | 2004-04-05 | 2007-10-09 | Broadcom Corporation | LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing |
| US7165205B2 (en) * | 2004-05-14 | 2007-01-16 | Motorola, Inc. | Method and apparatus for encoding and decoding data |
| US7143333B2 (en) * | 2004-08-09 | 2006-11-28 | Motorola, Inc. | Method and apparatus for encoding and decoding data |
-
2005
- 2005-09-19 EP EP05798137A patent/EP1800408A1/en not_active Ceased
- 2005-09-19 JP JP2007534638A patent/JP2008515342A/ja not_active Withdrawn
- 2005-09-19 WO PCT/US2005/033342 patent/WO2006055086A1/en not_active Ceased
- 2005-09-19 KR KR1020077007394A patent/KR20070062534A/ko not_active Ceased
- 2005-09-19 BR BRPI0515948-2A patent/BRPI0515948A/pt not_active IP Right Cessation
- 2005-09-19 US US11/662,565 patent/US20080104474A1/en not_active Abandoned
- 2005-09-19 CN CN2005800328231A patent/CN101032084B/zh not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101477925B1 (ko) * | 2013-10-08 | 2014-12-30 | 세종대학교산학협력단 | Ldpc 복호기를 이용한 데이터 경로 설정 방법 및 이를 위한 ldpc 복호기 |
| KR102857926B1 (ko) * | 2024-04-15 | 2025-09-15 | 한국과학기술원 | Ldpc 코드의 경판정 성질을 활용한 dvb-s2 표준 ldpc 반복 복호의 종료 기준 설계 방법 및 시스템 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1800408A1 (en) | 2007-06-27 |
| WO2006055086A1 (en) | 2006-05-26 |
| CN101032084B (zh) | 2010-05-05 |
| BRPI0515948A (pt) | 2008-08-12 |
| CN101032084A (zh) | 2007-09-05 |
| JP2008515342A (ja) | 2008-05-08 |
| US20080104474A1 (en) | 2008-05-01 |
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