KR20070051077A - Device and method for video signal format decision of video apparatus - Google Patents

Abstract

The present invention relates to an apparatus and method for determining a signal format of a video device, and more particularly, to determine a format of a received video signal by counting the number of counting clocks corresponding to a width of an input sync pulse. An apparatus and method for determining a signal format of a device are provided.

The apparatus for determining a signal format of a video device of the present invention includes an input switch for selecting a video signal input from the outside, an AD converter for digitally converting the video signal selected by the input switch and generating a counting clock. And a counter for detecting the number of counting clocks corresponding to the sync pulse widths of the video signal, and a controller for determining the format of the video signal according to the number of counting clocks detected.

Video signal format, counting clock, positive sync pulse, negative sync pulse, adaptive count clock generator

Description

Apparatus and method for determining signal format of video device

1 is a block diagram schematically illustrating an apparatus for determining a signal format of a video device according to the prior art.

2 is a block diagram schematically illustrating an apparatus for determining a signal format of a video device according to the present invention.

3 is a view for explaining a counter of the apparatus for determining a signal format of a video device according to the present invention.

4 is a block diagram schematically illustrating an adaptive counting clock generator of a signal format determination apparatus of an imaging apparatus according to the present invention.

5 is a flowchart illustrating a signal format determination method of a video device according to the present invention.

<Description of the symbols for the main parts of the drawings>

210: video switch 220: AD converter

230: scaler 240: EPLD

250: counter 260: control unit

310: Positive_Sync 320: Negative_Sync

320, 340: counting clock

The present invention relates to a video apparatus signal format determination apparatus and method for determining the format of a received video signal by counting the number of counting clocks corresponding to the input sync pulse width.

Recently, in the age of multimedia, the field of video devices has been required to process and display video signals of various formats.

In particular, the television device determines the format of the video signal input from the PC and various video devices as well as the analog broadcast such as NTSC, PAL, SECAM, and digital broadcast such as ATSC, ISDB, DVB, and the like. There is a demand for a function to perform image processing with a sampling clock suitable for the format of the corresponding input video signal.

The signal format determination apparatus will be described with reference to FIG.

1 is a block diagram schematically illustrating an apparatus for determining a signal format of a video device according to the prior art.

As shown, the signal format determination apparatus digitally converts an image switch 110 (or a video switch) for selecting an image signal input from the outside and an image signal selected by the image switch 110. The AD converter 120 for converting the signal to the digital signal and the horizontal and vertical synchronizing signals H and V of the RGB signal are input to compensate for the signal distortion, or the EPLD (Erasable for separating the synchronizing signal included in the component signal). Programmable Logic Device (140), and a scaler 130 for signal processing a digitally converted video signal to fit a predetermined screen format.

That is, when the image signal selected by the image switch 110 is input to the AD converter 120, the AD converter 120 receives the horizontal and vertical synchronization signals H, whose signal distortion is compensated by the EPLD 140. V) is input, the frequency of the horizontal and vertical synchronizing signals (H, V) is determined, and the analog video signal is converted to digital with an appropriate sampling clock. The scaler 130 receives the digital video signal and displays the screen. It is configured to allow signal processing suitable for the format.

However, according to the prior art as described above, for image signals having a similar frequency of the synchronization signal, such as, for example, the RGB 640 * 350 mode and the RGB 720 * 400 mode, the input is performed by simply determining the frequency of the synchronization signal. There is a problem in that the format of the video signal cannot be determined.

Accordingly, the present invention solves the above-described problem, and can determine the format of the video signal having a similar frequency of the synchronization signal, while reducing the noise by using an adaptively variable counting clock signal It is intended to provide a format determination apparatus and a control method.

Signal format determination apparatus of the video device of the present invention for achieving the above object is an input switch for selecting a video signal input from the outside, and converts the video signal selected by the input switch to a digital, counting clock A counter for detecting the number of counting clocks corresponding to the synchronous pulse width of the video signal, and a controller for determining the format of the video signal according to the number of detected counting clocks. Characterized in that.

In this case, the controller may be configured to determine the format of the video signal according to which of the number of counting clocks in the high section and the number of counting clocks in the low section is greater.

The clock generator for generating the counting clock may be an adaptive clock generator that generates a clock having a variable frequency in proportion to the sync pulse frequency of the video signal.

On the other hand, the signal format determination method of the video device of the present invention for achieving the above object is the step of selecting and receiving a video signal input from the outside, generating a counting clock, and of the received video signal Detecting the number of counting clocks corresponding to the sync pulse width; determining the format of the video signal according to the detected clock number; and processing the video signal according to the format of the video signal. It is characterized by including.

In the determining of the format of the video signal, it may be preferable to compare which of the counting clocks in the high section and the counting clock in the low section is more.

In addition, in the generating of the counting clock, it may be desirable to generate a clock having a variable frequency in proportion to the sync pulse frequency of the video signal.

Hereinafter, an apparatus and a control method of determining a signal format of a video device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram schematically illustrating an apparatus for determining a signal format of a video device according to the present invention, FIG. 3 is a diagram for explaining a counter of the apparatus for determining a signal format of a video device according to the present invention, and FIG. 4 is an AD converter. Figure 2 shows a schematic diagram of an adaptive counting clock generator.

First, as shown in FIG. 2, the apparatus for determining a signal format of a video device according to an exemplary embodiment of the present invention includes an image switch 210, an AD converter 220, an EPLD 240, and a scaler 230. ), A counter 250, a controller 260, and the like.

The image switch 210 is for allowing a user to select an image input from an external device such as a PC. For example, the red signal R, the green signal G, the blue signal B, the horizontal synchronization signal H, An RGB signal in which all the vertical synchronization signals V are separated and transmitted, or a signal type in which the brightness signals Y and the color signals Cb and Cr are transmitted separately, and the horizontal and vertical synchronization signals are the brightness signals Y. Allows you to select one of the component signals included in the.

The AD converter 220 converts the analog RGB or component signal selected by the image switch 210 into digital and preprocesses the signal to a predetermined screen format, and synchronizes the pulses at the counter 250 to be described later. It is to generate a counting clock for detecting the pulse width of the high section and the low section of.

The EPLD 240 receives horizontal and vertical sync signals of an RGB signal to compensate for signal distortion or separate sync signals included in a component signal. That is, when signal distortion occurs in the sync pulse of the received RGB signal, it is possible to input the intact sync pulse to the AD converter 220 by compensating for it, and also the horizontal and vertical sync signals included in the brightness signal Y. Is to be able to input to the AD converter 220 by separating (sync slicing).

The scaler 230 is for signal processing a digitally converted video signal to fit a predetermined screen format, and performs the video signal processing suitable for various screen formats.

The counter 250 receives the counting clock from the AD converter 220 to detect the number of counting pulses corresponding to the width of the sync pulse. The counter 250 is a high section and a low section of the video signal sync pulse as shown in FIG. 3. It is configured to compare.

For example, an image signal having a 640 * 350 format input from a PC may have a pulse width of a lower period than a high period with the sync pulse 310 having a positive polarity (positive_sync) as shown in FIG. There is this wider characteristic.

Accordingly, the pulse widths of the high and low periods are compared with the counting clock 320 input from the AD converter 220, and the number of counting clocks 320 corresponding to the pulse widths of the high and low periods is counted. As the number of counting clocks corresponding to the detected high and low intervals is provided to the controller 260, the input sync pulse 310 may determine that the input sync pulse 310 is for an image signal having a 640 * 350 format.

That is, as shown in the image signal having a format of 640 * 350, since the sync pulse 310 is composed of a high period corresponding to four counting clocks and a low period corresponding to ten counting clocks, the controller 260 ) Determines that the number of counting clocks in the low period is greater than the number of counting clocks in the high period, and thus may be determined as an image signal having a format of 640 * 350 among the sync pulses having similar frequencies.

As another similar example, the sync pulse 330 of an image signal having a 720 * 400 format input from a PC has a sync pulse of negative polarity (negative_sync) as shown in FIG. Since the pulse width of the high section is wider than that of the low section, the counting clock 340 corresponding to the pulse width of the high section and the low section is counted and provided to the controller 260 to input the sync pulse 330. ) Can be determined for an image signal having a 720 * 400 format.

The controller 260 not only performs the overall control function of the video device but also receives the number of the counting clocks 320 and 340 detected as described above to determine the format of the input video signal. For this purpose, although not shown, the controller 260 includes a predetermined counting clock comparison unit.

Accordingly, since the counter 250 determines the format of the video signal by counting a counting clock corresponding to the width of the sync pulse differently from the prior art, the number of lines per frame similar to each other (such as 640 * 350 and 720 * 400) The format of the video signals having a line per frame or horizontal scanning frequency can be determined.

On the other hand, it is preferable that the switching frequency of the counting clock is at least twice higher than the switching frequency of the sync pulse to detect the more effective counting clock, and furthermore, the switching frequency of the counting clock is adapted according to the frequency of the input sync pulse. It will be desirable to vary them.

Such an adaptive counting clock generator will be described with reference to FIG. 4.

4 is a block diagram schematically illustrating a counting clock generator of a signal format determination apparatus of an imaging apparatus according to the present invention.

As shown, the counting clock generator (FIG. 4) of the AD converter 220 provides the counter 250 with a counting clock that is adaptively variable according to the frequency change of the input sync pulse, thereby providing a more effective counting clock. To be detected.

For example, a phase comparator 221 for comparing the frequency of the received sync pulse with the internally generated sync pulse, and a low pass filter (LPF) for converting the sync signal output from the phase comparator 221 into a DC value ( 222 and a phase locked loop (PLL) 224 for generating a counting clock according to the output signals of the voltage controlled oscillator (VCO) 223 and the voltage adjusted oscillator 223 whose oscillation frequency is varied according to the magnitude of the DC voltage. And the like.

The adaptive pulse generating means for generating such a counting clock is a general configuration known from Korean Patent Laid-Open No. 2001-93934, and so on, so a detailed description thereof will be omitted.

An adaptive counting clock generator (FIG. 4) allows the counting clock switching frequency to be changed according to the frequency of the input video signal, thereby making it possible to detect the number of counting clocks corresponding to the width of the more effective sync pulse, and having a lower input frequency. In this case, the switching frequency of the counting clock is also lowered to reduce the noise generated by the high frequency signal to the peripheral device.

Hereinafter, a signal format determination method of a video device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5 is a flowchart illustrating a signal format determination method of a video device according to the present invention.

As shown in the drawing, when an image signal selected by switching of the image switch 210 is first received (S401), horizontal and vertical sync pulses of the image signal are detected (S402) and input to the AD converter 220.

When the sync pulse is input, a predetermined counting clock is generated according to the switching frequency of the sync pulse (S403). It has already been mentioned above that the switching frequency of the counting clock is preferably at least twice higher than the switching frequency of the sync pulse.

When a counting clock occurs (S403), the counter 250 receives the counting clock and detects the number of counting clocks corresponding to the low and high section pulse widths of the sync pulse (S404) and outputs the counting clock to the controller 260. .

The controller 260 compares the counting clock count in the low section with the counting clock count in the high section to determine the format of the video signal (S405).

As a result of the comparison, if the number of counting clocks for the low period is larger than the number of counting clocks for the high period, it is determined as a positive polarity sync pulse (S408). For example, as described above, the format is 640 * 350. Signal processing (S409).

On the other hand, if the number of counting clocks for the high period is greater than the number of counting clocks for the low period, it is determined as a negative polarity sync pulse (S406), the signal processing (720) 400 format in S407.

Subsequently, it is determined whether or not the system of the imaging device is terminated (S410) to terminate the system or repeat the above-described processes.

The apparatus and method for determining a signal format of a video device according to an exemplary embodiment of the present invention have been described above. However, it will be apparent that the present invention is not limited to the above-described embodiments, and may include other specific forms that can be implemented by those skilled in the art without changing the technical spirit or essential features. .

According to the apparatus and method for determining a signal format of a video device according to the present invention as described above, as the number of counting clocks corresponding to the width of the sync pulse is counted to determine the format of the received video signal, the input video having a similar frequency For the signal, the format determination characteristic can be improved, and the noise can be reduced by adaptively varying the counting clock.

Claims (6)

An input switch for selecting a video signal input from the outside; An AD converter for digitally converting the video signal selected by the input switch and generating a counting clock; A counter for detecting the number of counting clocks corresponding to a sync pulse width of the video signal; And A controller for determining a format of the video signal according to the number of counting clocks detected Apparatus for determining a signal format of a video device comprising a. The method of claim 1, The controller is configured to determine the format of the video signal according to which of the number of counting clocks in the high section and the number of counting clocks in the low section of the sync pulse is greater. Device for determining the signal format of the device. The method according to claim 1 or 2, And a clock generator for generating the counting clock is an adaptive clock generator for generating a clock having a variable frequency in proportion to the sync pulse frequency of the video signal. Selecting and receiving an image signal input from an external source; Generating a counting clock; Detecting the number of counting clocks corresponding to a sync pulse width of the received video signal; Determining a format of the video signal according to the detected clock number; And Signal processing the video signal according to the format of the video signal Signal format determination method of a video device comprising a. The method of claim 4, wherein The determining of the format of the video signal may include comparing which of the number of counting clocks in the high section and the number of counting clocks in the low section is greater than that of the sync pulse. The method according to claim 4 or 5, The generating of the counting clock may include generating a clock having a variable frequency in proportion to a sync pulse frequency of the video signal.

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