KR20070045628A - Mode converting, device mode converting method, and display device having the same - Google Patents

Abstract

Disclosed are a mode converting apparatus, a method thereof, and a display device having the same, which prevent an image defect due to an external display mode change. The present invention discloses a comparator for comparing clock frequencies according to a display mode change, a plurality of clock signal generators for generating a clock signal corresponding to the compared result, and a noise generated from each clock signal generator. It characterized in that it comprises a plurality of filters for.

The present invention is provided with a comparator or recognition unit, a plurality of signal generators, and a plurality of filters, thereby improving image quality due to a sudden change in driving frequency of an external display mode change.

Display mode change, recognition unit, mode conversion device, connecting means, filter unit

Description

MODE CONVERTING, DEVICE MODE CONVERTING METHOD, AND DISPLAY DEVICE HAVING THE SAME}

1 is a view showing a driving device of a liquid crystal display device according to the present invention;

2 shows a graphics card of the first embodiment of FIG.

3 shows a timing controller of the first embodiment of FIG.

4 is a view of a second embodiment showing a driving device of a liquid crystal display device according to the present invention;

Fig. 5 is a view of a third embodiment showing a drive device of a liquid crystal display device according to the present invention.

* Description of the symbols for the main parts of the drawings *

100, 300, 400: liquid crystal panel 112, 312, 412: gate driver

114, 314, 414: data driver 120: graphics card

121 and 321: comparator 123: first clock signal generator

124: second clock signal generator 131, 133, 333: first filter

132, 134, 334: second filter 140, 340, 440: timing controller

143 and 343: first control signal generator 144 and 344: second control signal generator

150: common voltage generator 423: recognition unit

431: filter unit 443: control signal generator

451: connection means

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a mode converting device, a method thereof, and a display device having the same, which can reduce a decrease in image quality when a display mode is changed.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes (CRT). Such flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs) and electro luminescence (EL) displays. Device and the like.

The liquid crystal display device controls each pixel in a liquid crystal panel including a plurality of pixels arranged in a matrix and a plurality of control switches for controlling a video signal supplied to each of the pixels, that is, thin film transistors (TFTs). By controlling the transmission amount of light supplied from the backlight unit, a desired image is displayed on the screen.

The liquid crystal display device is supplied with a data signal, a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable (DE) signal and a clock signal to a timing controller.

The timing controller generates a gate control signal for controlling a gate driver using signals supplied from the graphics card, and generates a data control signal for controlling the data driver.

The gate control signal and the data control signal are applied to the liquid crystal panel to display an image.

The timing controller includes a filter for removing noise of the gate control signal and the data control signal.

In general, the liquid crystal display supports various display modes. In this case, when the external display mode is changed by the user, the vertical synchronization signal, the horizontal synchronization signal, the data enable signal and the clock signal are changed, and the changed vertical synchronization signal, the horizontal synchronization signal, the data enable signal and the clock are changed. The signal is supplied to the timing controller.

For example, when the frequency signal of 27Mhz is set in the 16: 9 mode, and the 42Mhz frequency signal is set in the 4: 3 mode, the user can change the 27Mhz of the signal to 4: 3 mode from the 16: 9 mode. The frequency signal is rapidly changed to a 42 Mhz frequency signal and applied to the timing controller. The timing controller transmits a gate control signal and a data control signal reflecting the changed frequency signal to the gate driver and the data driver.

In the conventional case, a filter is designed for a frequency according to a specific mode. For example, the filter is designed only for a frequency signal of 27 MHz according to the 16: 9 mode. In this case, when changing to 4: 3 mode, the frequency is changed to 42Mhz. Accordingly, since the filter is designed to remove noise only for a frequency signal of 27 MHz, the filter cannot be removed for 42 MHz according to 4: 3 mode, thereby preventing a desired image from being obtained by the removed noise. This has a problem of deterioration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a mode conversion device, a method thereof, and a display device having the same, which can suppress noise caused by a change of a display mode to prevent deterioration of image quality.

In order to achieve the above object, the mode conversion device according to the first embodiment of the present invention,

A comparator for comparing clock frequencies according to display mode changes;

A plurality of clock signal generators for generating clock signals corresponding to the comparison results; And

A plurality of filters for removing noise generated from each clock signal generator; Characterized in that it comprises a.

Mode conversion method according to a second embodiment of the present invention,

Comparing clock frequencies according to display mode changes;

Generating a corresponding clock signal according to the recognized clock frequency;

And removing the noise of the clock signal.

Mode conversion apparatus according to a third embodiment of the present invention,

A comparator for comparing clock signals according to display mode changes;

A plurality of control signal generators for generating a control signal using a clock signal corresponding to the comparison result; And

A plurality of filters for removing noise with respect to the generated control signal; Characterized in that it comprises a.

Mode conversion method according to a fourth embodiment of the present invention,

Comparing a clock signal according to a display mode change;

Generating a corresponding control signal according to the compared clock signal;

And removing the noise of the control signal.

In the display device according to the fifth embodiment of the present invention,

A first mode converter configured to compare clock frequencies according to display mode changes, generate a clock signal according to the comparison result, and remove noise of the clock signal;

A second mode converter configured to generate a control signal using the clock signal from which the noise is removed, and to remove noise of the control signal; And

And a display panel for displaying predetermined data according to the control signal.

In a display device according to a sixth embodiment of the present invention,

A mode converter configured to compare a clock signal according to a display mode change, generate a control signal using a clock signal corresponding to the comparison result, and remove noise of the control signal; And

And a display panel displaying a predetermined data signal according to the control signal.

Mode conversion apparatus according to a seventh embodiment of the present invention,

A recognition unit for recognizing a display mode corresponding to a predetermined clock signal;

A control signal generator for generating a control signal according to the recognized display mode;

A plurality of filters for removing noise on the generated control signal;

Connecting means for selecting the control signal to be input to any one of the plurality of filters; Characterized in that it comprises a.

Mode conversion method according to an eighth embodiment of the present invention,

Recognizing a clock signal according to a display mode change;

Generating a control signal using the clock signal;

Connecting to a filter for removing noise of the control signal;

Removing noise of the control signal; Characterized in that it comprises a.

In a display device according to a ninth embodiment of the present invention,

A mode converter configured to recognize a clock signal according to a display mode change, generate a predetermined control signal, and remove noise of the generated control signal;

A display panel displaying predetermined data according to the control signal; Characterized in that it comprises a.

Hereinafter, a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing a driving device of a liquid crystal display according to the present invention.

As shown in FIG. 1, the liquid crystal display of the present invention includes a liquid crystal panel 100 in which a plurality of gate lines GL0 to GLn and data lines DL1 to DLm are arranged, and an image is displayed, and the gate line ( A gate driver 112 for driving GL0 to GLn, a data driver 114 for driving the data lines DL1 to DLm, and a common voltage Vcom which is a reference voltage of the liquid crystal panel 100 is generated. The common voltage generator 160 is included.

In the liquid crystal panel 100, a plurality of gate lines GL0 to GLn and data lines DL1 to DLm are arranged, and a thin film transistor TFT which is a switching element is formed at an intersection thereof. In addition, the liquid crystal panel 100 includes two glass substrates and a liquid crystal filled on the glass substrate. The liquid crystal is driven by a potential difference between the common voltage Vcom and the data voltages supplied through the data lines DL1 to DLm to display an image on the liquid crystal panel 100.

The thin film transistor TFT is electrically connected to the gate lines GL0 to GLn as a switching element. When the scan signal, that is, the gate high voltage VGH is supplied to the gate lines GL0 to GLn, the thin film transistor TFT is turned on. When the gate is turned on and the gate low voltage VGL is supplied to the gate lines GL0 to GLn, the gate line is turned off.

When the thin film transistor TFT is turned on, a data voltage is supplied to the pixel electrode connected to the drain electrode of the thin film transistor TFT through the data lines DL1 to DLm. When the thin film transistor TFT is turned off, the pixel electrode becomes the next frame until the thin film transistor TFT is turned on, that is, the gate high voltage VGH. The data voltage is maintained until it is supplied.

The gate driver 112 sequentially supplies a scan signal, that is, a gate high voltage VGH, to the gate lines GL0 to GLn according to the gate control signal generated from the timing controller 140. When the gate high voltage VGH is supplied to the gate lines GL0 to GLn, as described above, the thin film transistor TFT is turned on.

The data driver 114 supplies a data voltage to the data lines DL1 to DLm according to a data control signal generated from the timing controller 140. The data driver 114 converts the R, G, and B data signals supplied from the timing controller 140 into analog voltages corresponding to the R, G, and B data signals, and supplies them to the data lines DL1 to DLm. do.

The timing controller 140 controls the gate driver 112 by using the vertical / horizontal synchronization signals Vsync and Hsync, the data enable signal DE, and the clock signal DCLK supplied from the graphics card 120. A gate control signal is generated and a data control signal for controlling the data driver 114 is generated. In addition, the timing controller 140 receives the R, G, and B data signals from the graphic card 120, and arranges the horizontal data by one horizontal line to the data driver 114.

The common voltage generator 160 generates a common voltage Vcom which becomes a reference voltage of the liquid crystal injected on the liquid crystal panel 100 by using the power voltage Vdd supplied from a power supply unit (not shown). . The common voltage Vcom is supplied to a common electrode not shown on the liquid crystal panel 100 to become a reference voltage of the liquid crystal.

2 and 3 are diagrams showing a graphics card and a timing controller of the first embodiment of the present invention.

As shown in FIGS. 1 and 2, the graphics card 120 includes a comparator 121 for comparing a driving frequency changed according to a sudden change of an external display mode, and the vertical / horizontal synchronization signals Vsync, First and second clock signal generators 123 and 124 for generating Hsync, a data enable signal DE and a clock signal DCLK, and the first and second clock signal generators 123 and 124. And first and second filters 131 and 132 for removing noise of a signal generated by the N-type.

The graphics card 120 supplies the vertical / horizontal synchronization signals Vsync and Hsync, the data enable signal DE, the clock signal DCLK, and the like to the timing controller 140.

The comparison unit 121 has a reference frequency of 35 MHz, a driving frequency higher than 35 MHz is supplied to the first clock signal generator 123 line, and a driving frequency lower than 35 MHz is the second clock signal generator 124. Supplied to the line.

The reference frequency of the comparator 121 is set to 35 MHz because the frequency is changed from 27 Mhz to 42 Mhz according to the change of the general external display mode.

The driving frequency according to the display mode change is compared by the comparator 121 inside the graphic card 120 and supplied to the first clock signal generator 123 or the second clock signal generator 124. The clock signal DCLK is generated.

The first clock signal generator 123 generates a clock signal DCLK having a frequency signal higher than 35 MHz as compared with the comparator 121, and the second clock signal generator 124 generates the comparator 121. ), A clock signal DCLK of a frequency signal lower than 35 Mhz is generated.

In this case, the signal including the noise generated by the first clock signal generator 123 is removed by the first filter 131, and the signal including the noise generated by the second clock signal generator 124 is first 2 is removed by the filter 132.

The first filter 131 is designed to have a period of a frequency higher than 35 MHz so as to remove noise of the signal generated by the first clock signal generator 123, and the second filter 132 has a second clock. It is designed to have a period of a frequency lower than 35Mhz so as to remove the noise of the signal generated by the signal generator 124.

The reference frequency of the comparison unit 121 is not limited to 35 MHz, and may be changed according to the driving frequency of the display mode change, and the number of the clock signal generator and the filter may also be changed according to the reference frequency of the recognition unit 121. Can be arranged in dogs.

As shown in FIGS. 1, 2, and 3, the timing controller 140 includes vertical / horizontal synchronization signals (Vsync, Hsync), data enable (DE) signals, and clock signals supplied from the graphics card 120. Noise of the signals generated by the first and second control signal generators 143 and 144 and the first and second control signal generators 143 and 144 that generate the control signal using the DCLK and the like. And first and second filters 133 and 134 for removal.

The first control signal generator 143 generates a control signal with a frequency higher than 35 MHz, and the second control signal generator 144 generates a control signal with a frequency lower than 35 MHz.

A control signal is generated by the first control signal generator 143 using the clock signal DCLK generated by the first clock signal generator 123 according to an external display mode change, and the second clock signal generator The control signal is generated by the second control signal generator 144 using the clock signal DCLK generated at 124.

The first filter 133 is designed to remove noise of a frequency signal higher than 35 MHz, and the second filter 134 is designed to remove noise of a frequency signal lower than 35 MHz.

The noise of the control signal generated by the first control signal generator 143 is removed through the first filter 133, and the noise of the control signal supplied by the second control signal generator 144 is the second filter. 134 is removed.

The control signal from which the noise is removed from the first filter 133 or the second filter 134 is supplied to the gate driver and the data driver.

A method of driving the liquid crystal display device of the first embodiment according to the present invention as described above will be described.

The driving frequency according to the change of the display mode is compared with the reference frequency (35 MHz) by the comparator 121 inside the graphic card 120 to be the first clock signal generator 123 or the second clock signal generator 124. Is supplied.

The first clock signal generator 123 generates a clock signal DCLK having a frequency signal higher than 35 MHz as compared with the comparator 121, and the second clock signal generator 124 generates the comparator 121. In comparison, a clock signal DCLK of a frequency signal lower than 35 MHz is generated.

At this time, the noise of the clock signal DCLK generated by the first clock signal generator 123 is removed by the first filter 131 and the clock signal (generated by the second clock signal generator 124). Noise of DCLK) is removed by the second filter 132.

In the timing controller 140, a control signal is generated by the first control signal generator 143 using the clock signal DCLK supplied from the first clock signal generator 123, and the second clock signal generator The control signal is generated by the second control signal generator 144 using the clock signal DCLK supplied from 124.

The control signals generated by the first or second control signal generators 143 and 144 are removed by the first or second filters 133 and 134, and the control signals from which the noise is removed are gate drivers ( 112 and data driver 114.

An image is displayed on the liquid crystal panel 100 by control signals supplied from the timing controller 140 to the gate driver 112 and the data driver 114.

4 is a view of a second embodiment showing a driving device of the liquid crystal display device according to the present invention.

As shown in FIG. 4, the liquid crystal display according to the second embodiment includes a liquid crystal panel 300 for displaying an image, a gate driver 312 and a data driver 314 for driving the liquid crystal panel 300. The timing controller 340 controls the gate driver 312 and the data driver 314, and a backlight assembly (not shown) to supply light.

The LCD does not include a separate graphics card, and although not shown, vertical / horizontal synchronization signals (Vsync, Hsync), data enable (DE) signals, clock signals (DCLK), etc., depending on the driving frequency in the system are not shown. Supplied.

The timing controller 340 may include a gate control signal for controlling the data driver 312 using the vertical / horizontal synchronization signals Vsync and Hsync, a data enable signal, and a clock signal DCLK, and a data driver. A data control signal for controlling 314 is generated.

The timing controller 340 includes a comparator 321 for comparing a clock signal DCLK of a driving frequency according to an external display mode change. Here, the comparison unit 321 has a reference frequency of 35Mhz.

The timing controller 340 may include a first control signal generator 343 for generating a control signal having a frequency higher than the reference frequency 35Mhz, and a second control signal for generating a control signal having a frequency lower than the reference frequency 35Mhz. The generation unit 344 is included.

The timing controller 340 may include a first filter 333 for removing noise of a control signal generated by the first control signal generator 343 and a control signal generated by the second control signal generator 344. It further includes a second filter 334 for removing noise.

The vertical / horizontal synchronization signals (Vsync, Hsync), the data enable (DE) signal, and the clock signal (DCLK) supplied from the system are compared with a reference frequency (35 MHz) by the comparing unit 321 of the timing controller 340. And supplied to the first control signal generator 343 or the second control signal generator 344, and a control signal is generated by the first control signal generator 343 or the second control signal generator 344. do.

The timing controller 340 may include a comparator having a plurality of reference frequencies, a plurality of control signal generators, and a plurality of filters according to an external display mode change.

The liquid crystal display includes a comparator 321, a plurality of control signal generators 343 and 344, and a plurality of filters 333 and 334 to output a frequency signal according to an external display mode change to improve image quality. can do.

5 is a view of a third embodiment showing a driving device of the liquid crystal display according to the present invention.

As shown in FIG. 5, the liquid crystal display device of the third embodiment includes a liquid crystal panel 400, a gate driver 412 and a data driver 414 for driving the liquid crystal, the gate driver 412 and a data driver ( Timing controller 440 to control 414.

The liquid crystal display does not include a separate graphics card as in the second embodiment of FIG. 4, and enables vertical / horizontal synchronization signals (Vsync, Hsync) and data enable of driving frequencies according to display mode changes in a system not shown. (DE) signal, clock signal DCLK, and the like are supplied.

The timing controller 440 recognizes the clock signal DCLK of the driving frequency according to the change of the display mode, and controls the connection unit 451, and the clock signal recognized by the recognition unit 421. The control signal generating unit 443 generates a control signal using the DCLK, and a filter unit 431 connected to the connection unit 451.

The recognition unit 421 presets a plurality of display modes that can be changed.

The filter unit 431 includes a plurality of filters for removing noise of the control signal due to the change of the display mode, and each filter is designed with a frequency set according to the display mode.

When the control signal according to the display mode is generated, noise is removed by a corresponding filter of the display mode among the filter units 431 connected to the connection means 451.

The connecting means 451 is generally designed as a multiplexer (Mux), and is connected to a plurality of filters of the filter unit 431. As described above, the design of the connecting means 451 is costly and has the effect of being implemented by only one, without having a plurality of bulky control signal generators 443.

Accordingly, the liquid crystal display according to the present invention includes a comparator or a recognizer, a plurality of signal generators, and a plurality of filters, so that the frequency changed according to the driving frequency according to the change of the external display mode is changed by the clock signal and By generating a control signal and removing noise from a corresponding filter, it is possible to improve image quality due to a sudden change in display mode. Here, the present invention is not limited to the above liquid crystal display device, but may be used for a display device having a display panel.

In addition, the display device according to the present invention may include a recognition unit, a signal generator, a connection unit, and a plurality of filters to generate a signal according to a display mode change, and to remove noise from a corresponding filter, thereby improving image quality. have.

According to the present invention, the comparator, a plurality of signal generators, and a plurality of filters are provided to improve image quality due to a sudden change in driving frequency of an external display mode change.

In addition, the present invention includes the recognition unit, the signal generation unit, the connection means, and a plurality of filters, thereby improving the image quality due to the drastic change in the driving frequency of the external display mode change.

Those skilled in the art through the above description will be capable of various changes and modifications without departing from the spirit of the present invention.

Claims (14)

A comparator for comparing clock frequencies according to display mode changes; A plurality of clock signal generators for generating clock signals corresponding to the comparison results; And A plurality of filters for removing noise generated from each clock signal generator; Mode conversion apparatus comprising a. The method of claim 1, And the plurality of filters are connected to correspond to the respective clock signal generators. Comparing clock frequencies according to display mode changes; Generating a corresponding clock signal according to the recognized clock frequency; And removing noise of the clock signal. A comparator for comparing clock signals according to display mode changes; A plurality of control signal generators for generating a control signal using a clock signal corresponding to the comparison result; And A plurality of filters for removing noise with respect to the generated control signal; Mode conversion apparatus comprising a. The method of claim 4, wherein And the plurality of filters are connected to correspond to the respective clock signal generators. Comparing a clock signal according to a display mode change; Generating a corresponding control signal according to the compared clock signal; Removing the noise of the control signal; mode conversion method comprising a. A first mode converter configured to compare clock frequencies according to display mode changes, generate a clock signal according to the comparison result, and remove noise of the clock signal; A second mode converter configured to generate a control signal using the clock signal from which the noise is removed, and to remove noise of the control signal; And And a display panel for displaying predetermined data according to the control signal. A mode conversion device for comparing a clock signal according to a display mode change, generating a control signal using a clock signal corresponding to the comparison result, and removing noise of the control signal; And And a display panel configured to display a predetermined data signal according to the control signal. A recognition unit for recognizing a display mode corresponding to a predetermined clock signal; A control signal generator for generating a control signal according to the recognized display mode; A plurality of filters for removing noise on the generated control signal; Connecting means for selecting the control signal to be input to any one of the plurality of filters; Mode conversion apparatus comprising a. The method of claim 9, And the control signal is generated using the clock signal. The method of claim 9, And a plurality of display modes that can be changed are preset in the recognizing means. The method of claim 9, And the connecting means is connected between the control signal generator and the plurality of filters. Recognizing a clock signal according to a display mode change; Generating a control signal using the clock signal; Connecting to a filter for removing noise of the control signal; Removing noise of the control signal; Mode conversion method comprising a. A mode converter configured to recognize a clock signal according to a display mode change, generate a predetermined control signal, connect to a filter for removing noise of the generated control signal, and remove noise of the control signal; A display panel displaying predetermined data according to the control signal; Display device comprising a.

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