KR20070028001A - Apparatus and method for driving liquid crystal display device - Google Patents

Abstract

A method and an apparatus for driving a liquid crystal display device are provided to improve image quality by minimizing a vertical dim by changing the charging sequence of odd and even numbered pixel columns every frame. An apparatus for driving a liquid crystal display device includes an LCD(Liquid Crystal Display) panel(110), a gate driver, plural data ICs(140), and a timing controller(122). The LCD panel has plural data lines and plural gate lines. The LCD panel includes an image display unit, which includes odd-numbered pixel columns and even-numbered pixel columns. The odd-numbered pixel columns are connected to first sides of the respective data lines. The even-numbered pixel columns are connected to second sides of the respective data lines. The gate driver supplies gate pulses to the gate lines so that the charging sequence of the data voltage for the odd-numbered and even-numbered pixels is changed every frame. The data ICs supply the data voltage to the data lines correspondingly to the charging sequence of the data voltage. The timing controller rearranges source data from the outside correspondingly to the charging sequence and controls the respective data ICs and the gate driver.

Description

Driving apparatus and driving method of liquid crystal display device {APPARATUS AND METHOD FOR DRIVING LIQUID CRYSTAL DISPLAY DEVICE}

1A and 1B illustrate line inversion according to the related art.

FIG. 2 is a waveform diagram showing a polarity and a gate pulse of a data voltage supplied to each pixel shown in FIGS. 1A and 1B.

3 is a view showing a driving device of a liquid crystal display according to a first embodiment of the present invention.

4 is a block diagram schematically illustrating a timing controller shown in FIG. 3.

FIG. 5 is a waveform diagram illustrating a data voltage, a gate, and a data control signal output from the timing controller shown in FIG. 4.

FIG. 6 is a block diagram schematically illustrating the first and second gate driving circuits shown in FIG. 3. FIG.

FIG. 7 is a waveform diagram showing driving waveforms in N frame periods in the first embodiment of the present invention; FIG.

8 is a diagram illustrating a pixel charging procedure in an N frame period in the first embodiment of the present invention.

9 is a waveform diagram showing a drive waveform of an N + 1 frame period in the first embodiment of the present invention;

FIG. 10 is a diagram illustrating a pixel charging procedure in an N + 1 frame period according to the first embodiment of the present invention. FIG.

FIG. 11 is a view schematically illustrating a driving device of a liquid crystal display according to a second exemplary embodiment of the present invention. FIG.

12 is a waveform diagram showing a driving waveform of an N frame period in the second embodiment of the present invention;

FIG. 13 is a diagram illustrating a pixel charging procedure in an N frame period according to the second embodiment of the present invention. FIG.

FIG. 14 is a waveform diagram showing driving waveforms in an N + 1 frame period in the second embodiment of the present invention; FIG.

FIG. 15 is a diagram illustrating a pixel charging procedure in an N + 1 frame period in the second embodiment of the present invention. FIG.

<Explanation of Signs of Major Parts of Drawings>

16, 116 pixels 110: liquid crystal panel

112, 212: image display unit 120: printed circuit board

122, 222: timing controller 124: data processor

126: data control signal generator 128: gate control signal generator

134: TCP 140: data integrated circuit

150: first gate driving circuit 160: second gate driving circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a driving device and a driving method of a liquid crystal display device for improving image quality.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Such flat panel displays include a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among such flat panel display devices, the liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field.

For this purpose, an active matrix liquid crystal display using a TFT (Thin Film Transistor) as a switching element is known. This active matrix type liquid crystal display device arranges gate lines and data lines in a matrix shape, and forms a liquid crystal material between a TFT array substrate having TFTs arranged at intersections thereof and an opposing substrate disposed at predetermined intervals from the substrate. It encloses and controls the voltage applied to this liquid crystal material by TFT, and enables display using the electro-optical effect of a liquid crystal.

As the number of pixels with high definition of the active matrix type liquid crystal display increases, the number of gate lines and data lines increases with increasing number of pixels, and the number of driving integrated circuits increases, thereby increasing costs. It is causing. In addition, the pitch between the driving integrated circuit and the pads for connection in the array substrate is narrowed, making it difficult to connect with each other, thereby lowering the yield of the connection work.

In order to solve this problem at the same time, Korean Patent Publication No. 2005-0000105 (published date, January 03, 2005) discloses a data driving integrated circuit by supplying potentials from one data line to two adjacent pixels in time division. A liquid crystal display and a driving method thereof are proposed which can reduce cost by reducing the number.

In Korean Patent Publication No. 2005-0000105, in order to prevent degradation of a liquid crystal and to improve display quality, the polarity of the data voltage is inverted to one of a frame, a line, and a dot, and a gate pulse is 1/2 horizontal for one horizontal period. Overlapping for each period is supplied to the gate line.

FIG. 2 is a waveform diagram illustrating polarities and gate pulses of data voltages supplied to each pixel illustrated in FIGS. 1A and 1B.

First, the polarity of the data voltage is inverted in the unit of frame and inverted in the unit of horizontal line, and the gate pulse is supplied so that the gate pulse supplied to the previous gate line GL overlaps with the one-half horizontal period. At this time, the gate pulse supplied to the gate line GL has the same width.

Accordingly, each pixel 16 pre-charges the data voltage during the first period overlapping with the gate pulse supplied to the previous gate line GL during one horizontal period, and actually performs the second period. It will charge the data voltage.

2 will be described in detail with reference to FIGS. 1A and 1B.

First, odd-numbered pixels 16 connected to the first gate line GL1 during a period before the first period of the first horizontal period are each formed by a gate pulse overlapping the gate pulse supplied to the n-th gate line GLn. It is preliminarily charged by the negative data voltage supplied to each pixel 16 of the last horizontal line from the data line DL.

Then, the odd numbered pixels 16 connected to the first gate line GL1 precharged with the negative data voltage during the first period of the first horizontal period are each data line DL by the gate pulse. Data voltage of the positive polarity (+) for the odd-numbered pixels from &quot;

At the same time, the even-numbered pixel 16 connected to the second gate line GL2 during the first period of the first horizontal period is provided by the gate pulse supplied to overlap the gate pulse supplied to the first gate line GL1. The data voltage of the positive polarity (+) for odd-numbered pixels from each data line DL is precharged.

Subsequently, the odd-numbered pixel 16 connected to the second gate line GL2 precharged with the data voltage of the positive polarity (+) for the odd-numbered pixels during the second period of the first horizontal period is each data by the gate pulse. The data voltage of the positive polarity (+) for the even pixels from the line DL is charged.

At the same time, the odd-numbered pixel 16 connected to the third gate line GL3 during the second period of the first horizontal period is provided by the gate pulse supplied to overlap the gate pulse supplied to the second gate line GL2. The data voltage of the positive polarity (+) for even-numbered pixels from each data line DL is precharged.

Accordingly, the odd-numbered and even-numbered pixels 16 connected to the left and right sides of each data line DL charge the positive data voltage in the first horizontal period.

Then, the odd-numbered pixels 16 connected to the third gate line GL3 precharged with the positive data voltage during the first period of the second horizontal period are each data line DL by the gate pulse. Data voltage of the negative polarity (-) for the odd-numbered pixels from &quot;

At the same time, the even-numbered pixel 16 connected to the fourth gate line GL4 during the first period of the second horizontal period is provided by the gate pulse supplied to overlap the gate pulse supplied to the third gate line GL3. The data voltage of the negative polarity (-) for the odd pixel from each data line DL is precharged.

Subsequently, the even-numbered pixel 16 connected to the fourth gate line GL4 precharged with the negative-voltage data voltage for the odd-numbered pixels during the second period of the second horizontal period is generated by the gate pulse. The data voltage of the negative polarity (−) for the even pixels from the line DL is charged.

At the same time, the odd-numbered pixel 16 connected to the fifth gate line GL5 during the second period of the second horizontal period is provided by the gate pulse supplied to overlap the gate pulse supplied to the fourth gate line GL4. The data voltage of the negative polarity (−) for even-numbered pixels from each data line DL is precharged.

Accordingly, the odd-numbered and even-numbered pixels 16 connected to the left and right sides of each data line DL in the second horizontal period charge the negative data voltage.

As described above, the gate pulses having the same width are supplied to the gate lines GL to the pixels 16 during the third to nth horizontal periods in the same manner as the first and second horizontal periods, and at the same time, the positive polarity is applied to each data line. The data voltages of the positive and negative polarities are supplied.

Accordingly, Korean Patent Publication No. 2005-0000105 is intended to drive a liquid crystal display by a line inversion driving method.

However, Korean Patent Publication No. 2005-0000105 described above supplies the gate pulses of the same width sequentially to each gate line GL, so that the first side of each data line DL and the odd-numbered gate lines GL1, GL3, Between the odd-numbered pixel column Po connected to ..., the second side of each data line DL, and the even-numbered pixel column Pe connected to the even-numbered gate lines GL2, GL4, ... There is a problem in that a vertical dim occurs due to a luminance difference.

Specifically, the odd pixel column Po is precharged with the polarity opposite to the data voltage of the actual polarity, while the even pixel column Pe is precharged with the same polarity as the data voltage of the actual polarity. That is, the odd-numbered pixel column Po is precharged with negative polarity (-) and then charged with a positive data voltage, or precharged with positive polarity (+) and then with a negative data voltage. Is charged. On the other hand, the even-numbered pixel column Pe is precharged with negative polarity (-) and then charged with a negative data voltage or precharged with positive polarity (+) and then with a positive data voltage. Is charged. As a result, the polarities of the data voltages applied to the odd-numbered pixel columns Po and the even-numbered pixel columns Pe during preliminary charging are different.

Therefore, the above-described Korean Patent Publication No. 2005-0000105 discloses the actual data voltage charged in each pixel 16 of the odd pixel column Po and the actual data charged in each pixel 16 of the even pixel column Pe. There is a problem that the image quality is degraded by the vertical dim due to the difference between the data voltage.

Accordingly, in order to solve the above problems, the present invention is to provide a driving device and a driving method of the liquid crystal display device to improve the image quality.

In order to achieve the above object, a driving apparatus of a liquid crystal display according to an exemplary embodiment of the present invention has a plurality of data lines and a plurality of gate lines, an odd pixel column connected to a first side of each data line, A liquid crystal panel including an image display unit having an even-numbered pixel column connected to a second side of each data line; A gate driver supplying gate pulses to the gate lines so that the order of charging the data voltages charged in the odd and even pixels is changed in units of frames; A plurality of data integrated circuits supplying the data voltages to the data lines so as to correspond to the charging order of the data voltages; And a timing control unit for rearranging source data supplied from the outside so as to correspond to the charging order of the data voltages, supplying the source data to the data integrated circuits, and controlling the data integrated circuits and the gate driver.

The gate driver may supply a gate pulse to each gate line such that a charging order of data voltages charged in the odd-numbered and even-numbered pixels is reversed in a horizontal period unit.

A driving method of a liquid crystal display according to an exemplary embodiment of the present invention has a plurality of data lines and a plurality of gate lines, an odd pixel column connected to a first side of each data line, and a second side of each data line. A liquid crystal display comprising a liquid crystal panel comprising an image display having an even numbered pixel column connected thereto; Supplying a gate pulse to each gate line such that a charging order of data voltages charged in the odd and even pixels is changed in units of frames; And supplying the data voltage to each data line so as to correspond to the charging order of the data voltage.

The driving method may further include supplying a gate pulse to each of the gate lines such that the charging order of the data voltages charged in the odd-numbered and even-numbered pixels in a horizontal period is reversed.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

3 is a view schematically illustrating a driving device of the liquid crystal display according to the first embodiment of the present invention.

Referring to FIG. 3, the driving apparatus of the liquid crystal display according to the first exemplary embodiment of the present invention has a plurality of data lines DL and n gate lines GL, and a first side of each data line DL. And odd-numbered pixel columns Po connected to odd-numbered gate lines GL1, GL3, ..., second-side and even-numbered gate lines GL2, GL4, ... of each data line DL. A liquid crystal panel 110 including an image display unit 112 having an even-numbered pixel column Pe connected thereto; The odd-numbered gate lines GL1, GL3,... And the even-numbered gate lines GL2, so that the charging order of the data voltages charged in the odd-numbered pixel column Po and the even-numbered pixel column Pe are changed in units of frames. A gate driver for supplying a gate pulse to GL4, ...); A plurality of data integrated circuits (140) for supplying a positive (+) or a negative (-) data voltage to each data line DL so as to correspond to the data charging order of each pixel 116; A timing controller 122 is provided to align source data supplied from the outside and to supply the data data to each data integrated circuit 140 and to control the data integrated circuit 140 and the gate driver.

In addition, the driving apparatus of the liquid crystal display according to the first embodiment of the present invention includes a timing controller 122, a printed circuit board 120 on which a power circuit (not shown) is mounted, and each data integrated circuit. 140 further includes a plurality of Tape Carrier Packages (hereinafter, referred to as TCP) 134 connected between the printed circuit board 120 and the liquid crystal panel 110.

In addition, in the driving apparatus of the liquid crystal display according to the first embodiment of the present invention, the gate driver may include a first gate driving circuit 150 for supplying a gate pulse to the odd-numbered gate lines GL1, GL3,... ; A second gate driving circuit 160 for supplying a gate pulse to the even-numbered gate lines GL2, GL4, ... is provided.

The image display unit 112 adjusts the light transmittance of each pixel 116 according to a data voltage supplied to each pixel column Po and Pe through a gate pulse supplied to each gate line GL and a data line, thereby realizing an image. Will be displayed.

Each TCP 134 is electrically connected between the printed circuit board 120 and the liquid crystal panel 110 by a tape automated bonding (TAB) method. In this case, input pads of each TCP 134 are electrically connected to the printed circuit board 120, and output pads are electrically connected to the liquid crystal panel 110.

As shown in FIG. 4, the timing controller 122 aligns the source data RGB supplied from the outside to be suitable for driving the liquid crystal panel 110 and supplies the data data to the data integrated circuit 140. And a data control signal DCS for controlling the driving timing of each data integrated circuit 140 by using the vertical and horizontal synchronization signals Vsync and Hsync and the data enable signal DE. Driving timing of the gate driver by using the data control signal generator 126 supplied to each data integrated circuit 140 and the vertical and horizontal synchronization signals Vsync and Hsync and the data enable signal DE supplied from the outside. The gate control signal generator 128 generates a gate control signal GCS for controlling the control signal and supplies the gate control signal GCS to the gate driver.

The data processor 124 aligns the source data RGB supplied from the outside to be suitable for driving the liquid crystal panel 110, and rearranges the sorted data so that the order of the arranged data is different from each other in units of frames as shown in FIG. 5. Each data integrated circuit 140 is supplied. Specifically, the data processing unit 124 may be configured for the odd-numbered pixel Po (1A, 2A, 3A to NA) and the even-numbered pixel Pe in the N (where N is a positive integer) frame period. 2B, 3B to NB are rearranged and supplied to each data integrated circuit 140, and in the N + 1 frame period, the data for even-numbered pixels Pe 1B, 2B, 3B to NB. And the data arranged for the odd-numbered pixel Po (1A, 2A, 3A to NA) are rearranged and supplied to each data integrated circuit 140. As a result, data supplied from the data processing unit 124 to each data integrated circuit 140 in the N frame period is supplied in the order of 1A, 1B, 2A, 2B, 3A, 3B, ..., NA, NB. In the N frame period, the data supplied from the data processing unit 124 to each data integrated circuit 140 is supplied in the order of 1B, 1A, 2B, 2A, 3B, 3A, ..., NB, NA.

The data control signal generator 126 may start a source for controlling driving timing of each data integrated circuit 140 using vertical and horizontal synchronization signals Vsync and Hsync and a data enable signal DE. Generate a data control signal (DCS) including a pulse (Source Start Pulse: SSP), a source shift clock (SSC), a polarity control signal (Polarity: POL), and a source output enable signal (SOE). It is supplied to the data integrated circuit 140. At this time. The timing controller 122 generates the polarity control signal POL such that the polarity of the data supplied to the image display unit 112 is inverted, that is, line inverted, in units of horizontal lines.

The gate control signal generator 128 uses the vertical and horizontal synchronization signals Vsync and Hsync and the data enable signal DE to be supplied from the outside to each of the first and second gate driver circuits 150 and 160. A gate control signal (GCS) including a gate start pulse (GSP), a plurality of gate shift clocks (GSC), and a gate output enable signal (GOE) for controlling driving timing. ) Is supplied to the first and second gate driving circuits 150 and 160, respectively.

The gate control signal generator 128 may include a plurality of gate shift clocks GSC according to the number of gate shift clocks GSC for driving the shift registers constituting the first and second gate driving circuits 150 and 160. Will occur). At this time, when it is assumed that each of the first and second gate driving circuits 150 and 160 generates gate pulses using two gate shift clocks GSC, the gate control signal generator 128 is frame-by-frame unit. In order to change the charging order of the data voltages, as shown in FIG. 5, first to fourth gate shift clocks GSC1 to GSC4 are sequentially generated for N frame periods, and during N + 1 frame periods. The first to fourth gate shift clocks GSC1 to GSC4 are generated such that the phases are delayed in the second, first, fourth, and third order. Accordingly, the first and second gate shift clocks GSC1 and GSC2 are supplied to the first gate driving circuit 150, and the third and fourth gate shift clocks GSC3 and GSC4 are second gate driving circuits 160. Is supplied.

Each data integrated circuit 140 receives a data signal from the data processor 124 of the timing controller 122 according to a data control signal DCS input from the timing controller 122 through an input pad of the TCP 130. ) Is converted into an analog data voltage and supplied to each data line DL of the liquid crystal panel 110 through an output pad of the TCP 130. At this time, each data integrated circuit 140 generates a positive (+) or a negative (-) data voltage according to the polarity control signal POL from the timing controller 122 to generate a source from the timing controller 122. The data is supplied to each data line DL according to the output enable signal SOE.

As illustrated in FIG. 6, the first gate driving circuit 150 includes first and third gate shift clocks GSC1 and GSC3 input lines directly formed on the liquid crystal panel 110, a driving voltage Vdd, and a pre-set. I which is connected to the low voltage (Vss) input line, the gate start pulse (GSP) input line, and each input line dependently and supplies the gate pulse to the odd-numbered gate lines GL1, GL3 to GLn-1 (where, i Is a positive integer n / 2) stages 1521 to 152i.

As shown in FIG. 5, the first and third gate shift clocks GSC1 and GSC3 have a phase delayed and repeated in one horizontal period from the gate control signal generator 128 of the timing controller 122 and are frame-wise. The first and third gate shift clocks GSC1 and GSC3 are switched in order.

Each stage 1521 to 152i is connected to any one of the input lines of the first and third gate shift clocks GSC1 and GSC3 according to the output signal from the front stages 1522 to 152i except for the first stage 1521. The supplied first and third gate shift clocks GSC1 and GSC3 are supplied to the corresponding odd-numbered gate lines GL1 and GL3 to GLn-1. At this time, the first stage 1521 first applies the first gate shift clock GSC1 supplied from the first gate shift clock GSC1 input line according to the gate start pulse GSP from the gate control signal generator 128. Supply to one gate line GL1.

The first gate driving circuit 150 is driven by the gate start pulse GSP from the gate control signal generation unit 128 to generate one horizontal period unit according to the first and third gate shift clocks GSC1 and GSC3. The gate phase is sequentially delayed and the gate pulses are changed in units of frames. The gate pulses are generated in response to the gate output enable signal GOE from the gate control signal generator 128, and the gate pulses GL1, GL3 to GLn-1) are supplied sequentially.

The second gate driving circuit 160 may include second and fourth gate shift clocks GSC2 and GSC4 input lines directly formed on the liquid crystal panel 110, a driving voltage Vdd and a base voltage Vss input line. A gate start pulse (GSP) input line and i stages 1621 to 162i connected to each input line to supply gate pulses to even-numbered gate lines GL2 and GL4 to GLn.

At one end of the input lines of the second and fourth gate shift clocks GSC2 and GSC4, the phase is delayed and repeated in one horizontal period from the gate control signal generator 128 of the timing controller 122 as shown in FIG. 5. The second and fourth gate shift clocks GSC2 and GSC4 are supplied in order by frame unit.

Each stage 1621 to 162i is driven from one of the second and fourth gate shift clocks GSC2 and GSC4 input lines according to the output signal from the front stages 1622 to 152i except for the first stage 1621. The supplied second and fourth gate shift clocks GSC2 and GSC4 are supplied to the even-numbered gate lines GL2 and GL4 to GLn. At this time, the first stage 1621 performs the second gate shift clock GSC2 supplied from the second gate shift clock GSC2 input line according to the gate start pulse GSP from the gate control signal generator 128. 2 is supplied to the gate line GL2.

The second gate driving circuit 160 is driven by the gate start pulse GSP from the gate control signal generation unit 128 to generate one horizontal period unit according to the second and fourth gate shift clocks GSC2 and GSC4. The low phase is sequentially delayed and repeated, and the gate pulses are sequentially changed in units of frames. The gate pulses are even-numbered gate lines GL2 and GL4 according to the gate output enable signal GOE from the timing controller 122. To GLn).

Accordingly, the first and second gate driving circuits 150 and 160 are sequentially supplied with the gate pulses to the gate lines GL of the image display unit 112 so that the first and second gate driving circuits 150 and 160 overlap each other.

7 is a waveform diagram illustrating a driving waveform of an N frame period in the driving method of the liquid crystal display according to the first embodiment of the present invention, and FIG. 8 is a liquid crystal display according to the first embodiment of the present invention. The pixel charging procedure in the N frame period is shown in the driving method of FIG. 9 is a waveform diagram illustrating a driving waveform of an N + 1 frame period in the driving method of the liquid crystal display according to the first embodiment of the present invention, and FIG. 10 is a liquid crystal display according to the first embodiment of the present invention. In this driving method, the pixel charging procedure in the N + 1 frame period is shown.

A driving method of the liquid crystal display according to the first exemplary embodiment of the present invention will be described with reference to FIGS. 7 to 10 as follows.

First, in the N frame period, as shown in FIG. 7, the data voltages for odd-numbered pixels (1A, 2A, 3A, ...) and the data voltages for even-numbered pixels whose polarities of the data voltages are inverted in units of horizontal lines (one horizontal period) as shown in FIG. (1B, 2B, 3B, ...) are alternately supplied to each data line, and the phase pulses are delayed in units of 1/2 horizontal period to overlap the gate pulses 1, 2, 3, 4, 5, 6, It is sequentially supplied to the gate line GL in the order of 7, 8, .... At this time, the odd-numbered pixel 116 connected to the first gate line GL1 in the previous period of the first horizontal period is randomly negative data by the gate pulse supplied from the first gate driving circuit 150. Assume that the voltage is precharged.

In the first horizontal period of the N frame period, the gate pulses overlapped for half a horizontal period from the first and second gate driving circuits 150 and 160 are supplied to the first and second gate lines GL1 and GL2. Accordingly, during the first period of the first horizontal period in which the gate pulse supplied to the first gate line GL1 and the gate pulse supplied to the second gate line GL2 overlap, the negative data voltage is negative. The odd-numbered pixel 116 connected to the pre-charged first gate line GL1 charges the data voltage 1A of the positive polarity (+) for odd-numbered pixels from each data line DL by a gate pulse. The even-numbered pixel 116 connected to the second gate line GL2 precharges the data voltage 1A of the positive polarity (+) for the odd-numbered pixel from each data line DL by the gate pulse. .

Subsequently, a gate pulse is supplied to the third gate line GL3 to overlap the gate pulse supplied from the first gate driving circuit 150 to the second gate line GL2 for a half horizontal period. Accordingly, during the second period of the first horizontal period in which the gate pulse supplied to the second gate line GL2 and the gate pulse supplied to the third gate line GL3 overlap, the positive data voltage (+) The even-numbered pixel 116 connected to the second gate line GL2 precharged with 1A is a data voltage 1B of positive polarity (+) for even-numbered pixels from each data line DL by a gate pulse. And the odd-numbered pixel 116 connected to the third gate line GL3 reserves the data voltage 1B of the positive polarity (+) for the even-numbered pixel from each data line DL by the gate pulse. Will charge.

Accordingly, odd-numbered and even-numbered pixels 116 connected to the left and right sides of each data line DL charge the positive data voltages 1A and 1B during the first horizontal period. At this time, the odd-numbered pixel 116 is charged with the positive polarity (+) at the negative precharge voltage, while the even-numbered pixel 116 is charged with the positive polarity (+) at the preliminary charge voltage of the positive polarity (+). ) Is charged. Therefore, the final charging voltage of the odd pixel 116 is lower than the final charging voltage of the even pixel 116.

Then, in the second horizontal period of the N frame period, the fourth gate line GL4 overlaps with the gate pulse supplied from the second gate driving circuit 160 to the third gate line GL3 for 1/2 horizontal period. The gate pulse is supplied. Accordingly, during the first period of the second horizontal period in which the gate pulse supplied to the third gate line GL3 and the gate pulse supplied to the fourth gate line GL4 overlap, the positive data voltage (+) The odd-numbered pixel 116 connected to the third gate line GL3 precharged with 1B is a data voltage 2A of negative polarity (-) for odd-numbered pixels from each data line DL by a gate pulse. And the even-numbered pixel 116 connected to the fourth gate line GL4 reserves the data voltage 2A of the negative polarity (-) for the odd-numbered pixel from each data line DL by the gate pulse. Will charge.

Subsequently, a gate pulse is supplied to the fifth gate line GL5 so as to overlap the gate pulse supplied from the first gate driving circuit 150 to the fourth gate line GL4 for a half horizontal period. Accordingly, during the second period of the second horizontal period in which the gate pulse supplied to the fourth gate line GL4 and the gate pulse supplied to the fifth gate line GL5 overlap, the data voltage of negative polarity (−) The even-numbered pixel 116 connected to the fourth gate line GL4 precharged with 2A) has a negative voltage (-) for the even-numbered pixel from each data line DL by a gate pulse. And the odd-numbered pixel 116 connected to the fifth gate line GL5 reserves the data voltage 2B of the negative polarity (-) for the even-numbered pixel from each data line DL by the gate pulse. Will charge.

Accordingly, odd-numbered and even-numbered pixels 116 connected to the left and right sides of each data line DL charge the negative data voltages 2A and 2B during the second horizontal period. At this time, the odd-numbered pixel 116 is charged with negative polarity (−) at the positive charging voltage of positive polarity (+), while the even-numbered pixel 116 is charged with negative polarity (−) at the preliminary charging voltage of negative polarity (−). ) Is charged. Therefore, the final charging voltage of the odd pixel 116 is lower than the final charging voltage of the even pixel 116.

On the other hand, in the third to nth horizontal periods of the N frame period, the positive (+) or negative polarity is applied to the odd pixel column Po and the even pixel column Pe in the same manner as the first and second horizontal periods described above. The data voltage of negative polarity is charged.

As a result, in the N frame period, the data voltage is charged in the odd-numbered pixel column Po as shown in the arrow direction shown in FIG. 8, and then the data voltage is charged in the even-numbered pixel column Pe. Accordingly, each pixel 116 of the odd-numbered pixel column Po in the N frame period has a different polarity of the voltage supplied during the preliminary charging and the voltage supplied during the charging, whereas each pixel of the even-numbered pixel column Pe is different. The pixel 116 has the same polarity of the voltage supplied during precharge and the voltage supplied during charging. Accordingly, in the N frame period, since the charging voltages of the odd-numbered pixel columns Po and the even-numbered pixel columns Pe are different, the charging characteristics of the odd-numbered pixel columns Po are reduced on the image display unit 112. Vertical dim occurs.

In order to eliminate the vertical dim caused by the luminance difference between the odd pixel column Po and the even pixel column Pe generated in the N frame period, the odd pixel column Po and the even pixel in the N + frame period. The charging order of each of the columns Pe is reversed.

First, in the N + 1 frame period, as shown in FIG. 9, the data voltages 1B, 2B, 3B, ... for the even pixels and the odd pixels for which the polarities of the data voltages are inverted in units of horizontal lines (one horizontal period) as shown in FIG. 9. Data voltages (1A 2A, 3A, ...) are alternately supplied to each data line, and the phase pulses are delayed in units of 1/2 horizontal period to overlap gate pulses 2, 1, 4, 3, 6, 5 , 8, 7, .. are sequentially supplied to the gate line GL. At this time, the even-numbered pixel 116 connected to the second gate line GL2 in the previous period of the first horizontal period may have any positive (+) data by the gate pulse supplied from the second gate driving circuit 160. Assume that the voltage is precharged.

In the first horizontal period of the N + 1 frame period, gate pulses superimposed from the first and second gate driving circuits 150 and 160 for 1/2 horizontal period are supplied to the second and first gate lines GL2 and GL1. do. Accordingly, during the first period of the first horizontal period in which the gate pulse supplied to the second gate line GL2 and the gate pulse supplied to the first gate line GL1 overlap, the positive data voltage is positive. The even-numbered pixel 116 connected to the pre-charged second gate line GL2 charges the data voltage 1B of the negative polarity (-) for the even-numbered pixel from each data line DL by the gate pulse. The odd-numbered pixel 116 connected to the first gate line GL1 precharges the negative-voltage (-) data voltage 1B for the even-numbered pixel from each data line DL by the gate pulse. .

Subsequently, the gate pulse is supplied to the fourth gate line GL4 so as to overlap the gate pulse supplied from the second gate driving circuit 160 to the first gate line GL1 for 1/2 horizontal period. Accordingly, during the second period of the first horizontal period in which the gate pulse supplied to the first gate line GL1 and the gate pulse supplied to the fourth gate line GL4 overlap, the negative data voltage (−) The odd pixel 116 connected to the first gate line GL1 precharged with 1B is a data voltage 1A of negative polarity (-) for the odd pixel from each data line DL by a gate pulse. And the even-numbered pixel 116 connected to the fourth gate line GL4 reserves the data voltage 1A of the negative polarity (-) for the odd-numbered pixel from each data line DL by the gate pulse. Will be charged.

Accordingly, odd-numbered and even-numbered pixels 116 connected to the left and right sides of each data line DL charge the negative data voltages 1B and 1A during the first horizontal period. At this time, the even-numbered pixel 116 is charged negatively at the preliminary charging voltage of positive polarity (+), while the odd-numbered pixel 116 is negatively charged at the preliminary charging voltage of negative-polarity (-). ) Is charged. Therefore, the final charging voltage of the even-numbered pixel 116 is lower than the final charging voltage of the odd-numbered pixel 116.

Then, in the second horizontal period of the N + 1 frame period, the third gate line GL3 is supplied with the gate pulse supplied from the first gate driving circuit 150 to the fourth gate line GL4 for a half horizontal period. The gate pulses are supplied to overlap. Accordingly, during the first period of the second horizontal period in which the gate pulse supplied to the fourth gate line GL4 and the gate pulse supplied to the third gate line GL3 overlap, the negative data voltage (−) The even-numbered pixel 116 connected to the fourth gate line GL4 precharged with 1A is a data voltage of positive polarity (+) for even-numbered pixels from each data line DL by a gate pulse. And the odd-numbered pixel 116 connected to the third gate line GL3 reserves the data voltage 2B of the positive polarity (+) for the even-numbered pixel from each data line DL by the gate pulse. Will be charged.

Subsequently, the gate pulse is supplied to the sixth gate line GL6 so as to overlap the gate pulse supplied from the second gate driving circuit 160 to the third gate line GL3 for a half horizontal period. Accordingly, during the second period of the second horizontal period in which the gate pulse supplied to the third gate line GL3 and the gate pulse supplied to the sixth gate line GL6 overlap, the positive data voltage (+) The odd-numbered pixel 116 connected to the third gate line GL3 precharged with 2B) has a data voltage of positive polarity (+) for odd-numbered pixels from each data line DL by a gate pulse. And the even-numbered pixel 116 connected to the sixth gate line GL6 reserves a data voltage 2A of positive polarity (+) for odd-numbered pixels from each data line DL by a gate pulse. Will be charged.

Accordingly, the odd-numbered and even-numbered pixels 116 connected to the left and right sides of each data line DL charge the positive data voltages 2B and 2A during the second horizontal period. At this time, the even-numbered pixel 116 is charged with the positive polarity (+) at the negative precharging voltage, while the odd-numbered pixel 116 is charged with the positive polarity (+) at the preliminary charging voltage of the positive polarity (+). ) Is charged. Therefore, the final charging voltage of the even-numbered pixel 116 is lower than the final charging voltage of the odd-numbered pixel 116.

On the other hand, in the third to nth horizontal periods of the N + 1 frame period, the positive polarity (+) is applied to the even-numbered pixel columns Pe and the odd-numbered pixel columns Po in the same manner as the first and second horizontal periods described above. Or a negative data voltage is charged.

As a result, in the N + 1 frame period, the data voltage is charged in the even-numbered pixel column Pe as shown in the arrow direction shown in FIG. 10, and then the data voltage is charged in the odd-numbered pixel column Po. Accordingly, in the N + 1 frame period, each pixel 116 of the even-numbered pixel column Pe has a different polarity of the voltage supplied during precharging and the polarity of the voltage supplied during charging, while the odd-numbered pixel column Po Each pixel 116 has the same polarity as that of the voltage supplied during preliminary charging. Accordingly, since the charging voltages of the even-numbered pixel columns Pe and the odd-numbered pixel columns Po are different in the N + 1 frame period, the image display unit 112 may be deteriorated due to the deterioration of the charging characteristics of the even-numbered pixel columns Pe. Vertical dim occurs in the phase.

Therefore, the driving apparatus and driving method of the liquid crystal display according to the first exemplary embodiment of the present invention are based on the data voltages of the odd pixel column Po and the even pixel column Pe in frame units N and N + 1. By reversing the charging order, it is possible to minimize the vertical dim generated during the line inversion driving of the image display unit 112.

FIG. 11 is a view schematically illustrating a driving device of a liquid crystal display according to a second exemplary embodiment of the present invention.

Referring to FIG. 11, a driving apparatus of a liquid crystal display according to a second exemplary embodiment of the present invention has a plurality of data lines DL and n gate lines GL, and a first side of each data line DL. And odd-numbered pixel columns Po connected to odd-numbered gate lines GL1, GL3, ..., second-side and even-numbered gate lines GL2, GL4, ... of each data line DL. A liquid crystal panel 110 including an image display unit 212 having an even-numbered pixel column Pe connected thereto; A gate driver supplying gate pulses to the gate lines GL so that the data charging order of adjacent pixels is changed in units of frames and units of horizontal periods; A plurality of data integrated circuits (140) for supplying a positive (+) or a negative (-) data voltage to each data line DL so as to correspond to the data charging order of each pixel; A timing controller 122 is provided to align source data supplied from the outside and to supply the data data to each data integrated circuit 140 and to control the data integrated circuit 140 and the gate driver.

In addition, the driving apparatus of the liquid crystal display according to the second embodiment of the present invention includes a timing controller 122 and a printed circuit board 120 on which a power circuit (not shown) is mounted, and each data integrated circuit ( 140 further includes a plurality of Tape Carrier Packages (hereinafter, referred to as TCP) 134 connected between the printed circuit board 120 and the liquid crystal panel 110.

In addition, in the driving apparatus of the liquid crystal display according to the second embodiment of the present invention, the gate driver may include a first gate driving circuit 150 for supplying a gate pulse to the odd-numbered gate lines GL1, GL3,... ; A second gate driving circuit 160 for supplying a gate pulse to the even-numbered gate lines GL2, GL4, ... is provided.

The driving apparatus of the liquid crystal display according to the second exemplary embodiment of the present invention has the same configuration as the first exemplary embodiment of the present invention shown in FIG. 3 except for the image display unit 212 and the timing controller 222. Have Accordingly, in the driving apparatus of the liquid crystal display according to the second embodiment of the present invention, descriptions of other components except for the image display unit 212 and the timing control unit 222 will be described in the first embodiment of the present invention. The description will be replaced.

The image display unit 212 includes an odd-numbered pixel column Po connected to the first side of each data line DL and odd-numbered gate lines GL1, GL3,..., And a second of each data line DL. The even-numbered pixel column Pe is connected to the side and even-numbered gate lines GL2, GL4, ....

At this time, the odd-numbered pixels 116 of the odd-numbered pixel columns Po are connected to the first side of each data line DL and the odd-numbered gate lines GL1, GL3,... The even-numbered pixels 116 of the odd-numbered pixel columns Po are connected to the first side of each data line DL and the even-numbered gate lines GL2, GL4,...

The odd-numbered pixels 116 of the even-numbered pixel columns Pe are connected to the second side of each data line DL and even-numbered gate lines GL2, GL4,... The even-numbered pixels 116 of the even-numbered pixel columns Pe are connected to the second side of each data line DL and the odd-numbered gate lines GL1, GL3,...

The timing controller 222 arranges the source data RGB supplied from the outside so as to be suitable for driving the liquid crystal panel 110, and rearranges the sorted data so as to differ from each other in units of frames. To feed. Specifically, the timing controller 222 may be configured for the odd-numbered pixels Po (1A, 2A, 3A to NA) and the even-numbered pixels Pe (1B, 2B, 3B) in units of one horizontal period in the N frame period. To NB), the data arranged in alternating order are rearranged and supplied to each data integrated circuit 140, and in the N + 1 frame period, the data is rearranged so as to be reversed from the data order in the N frame period and supplied to each data integrated circuit 140. do. As a result, the data supplied from the timing controller 222 to each data integrated circuit 140 in the N frame period is 1A, 1B, 2B, 2A, 3A, 3B, 4B, 4A, ..., NB, NA in order. The data supplied to each data integrated circuit 140 from the timing controller 222 in the N frame period is 1B, 1A, 2A, 2B, 3B, 3A, 4A, 4B, ..., NA, NB. Supplied in order.

As described above, the driving device and the driving method of the liquid crystal display according to the second embodiment of the present invention are the same as the first embodiment of the present invention, and the data voltage charging order of the pixels in frame units (N, N + 1). By reversing the above, the vertical dim generated during the line inversion driving of the image display unit 212 can be minimized.

12 is a waveform diagram illustrating a driving waveform of an N frame period in the second embodiment of the present invention, and FIG. 13 is a diagram illustrating a pixel charging procedure of the N frame period in the second embodiment of the present invention. to be. FIG. 14 is a waveform diagram illustrating driving waveforms in an N + 1 frame period in the second embodiment of the present invention. FIG. 15 is a pixel charging sequence in the N + 1 frame period in the second embodiment of the present invention. The figure shown.

A driving method of the liquid crystal display according to the second exemplary embodiment of the present invention will be described with reference to FIGS. 12 to 15 as follows.

First, in the N frame period, as shown in FIG. 12, the polarities of the data voltages are inverted in units of horizontal lines (one horizontal period) and the data voltages 1A, 2A, 3A,. The data voltages 1B, 2B, 3B, ... for even-numbered pixels are alternately supplied to each data line, and the gate pulses overlapped with phase delays in units of 1/2 horizontal period are overlapped with 1, 2, 3, 4, 5, 6, 7, 8, ... are sequentially supplied to the gate line GL. At this time, the odd-numbered pixel 116 connected to the first gate line GL1 in the previous period of the first horizontal period is randomly negative data by the gate pulse supplied from the first gate driving circuit 150. Assume that the voltage is precharged.

In the first horizontal period of the N frame period, the gate pulses overlapped for half a horizontal period from the first and second gate driving circuits 150 and 160 are supplied to the first and second gate lines GL1 and GL2. Accordingly, during the first period of the first horizontal period in which the gate pulse supplied to the first gate line GL1 and the gate pulse supplied to the second gate line GL2 overlap, a negative data voltage is applied. The odd-numbered pixel 116 connected to the pre-charged first gate line GL1 charges the data voltage 1A of the positive polarity (+) for odd-numbered pixels from each data line DL by a gate pulse. The even-numbered pixel 116 connected to the second gate line GL2 precharges the data voltage 1A of the positive polarity (+) for the odd-numbered pixel from each data line DL by the gate pulse. .

Subsequently, a gate pulse is supplied to the third gate line GL3 to overlap the gate pulse supplied from the first gate driving circuit 150 to the second gate line GL2 for a half horizontal period. Accordingly, during the second period of the first horizontal period in which the gate pulse supplied to the second gate line GL2 and the gate pulse supplied to the third gate line GL3 overlap, the positive data voltage (+) The even-numbered pixel 116 connected to the second gate line GL2 precharged with 1A is a data voltage 1B of positive polarity (+) for even-numbered pixels from each data line DL by a gate pulse. And the even-numbered pixel 116 connected to the third gate line GL3 reserves the data voltage 1B of the positive polarity (+) for the even-numbered pixel from each data line DL by the gate pulse. Will be charged.

Accordingly, odd-numbered and even-numbered pixels 116 connected to the left and right sides of each data line DL charge the positive data voltages 1A and 1B during the first horizontal period. At this time, the odd-numbered pixel 116 is charged with the positive polarity (+) at the negative precharge voltage, while the even-numbered pixel 116 is charged with the positive polarity (+) at the preliminary charge voltage of the positive polarity (+). ) Is charged. Therefore, the final charging voltage of the odd pixel 116 is lower than the final charging voltage of the even pixel 116.

Then, in the second horizontal period of the N frame period, the fourth gate line GL4 overlaps with the gate pulse supplied from the second gate driving circuit 160 to the third gate line GL3 for 1/2 horizontal period. The gate pulse is supplied. Accordingly, during the first period of the second horizontal period in which the gate pulse supplied to the third gate line GL3 and the gate pulse supplied to the fourth gate line GL4 overlap, the positive data voltage (+) The even-numbered pixel 116 connected to the third gate line GL3 precharged with 1B) has a negative voltage (-) for the even-numbered pixel from each data line DL by a gate pulse. And the odd-numbered pixel 116 connected to the fourth gate line GL4 reserves the data voltage 2B of the negative polarity (-) for the even-numbered pixel from each data line DL by the gate pulse. Will be charged.

Subsequently, a gate pulse is supplied to the fifth gate line GL5 so as to overlap the gate pulse supplied from the first gate driving circuit 150 to the fourth gate line GL4 for a half horizontal period. Accordingly, during the second period of the second horizontal period in which the gate pulse supplied to the fourth gate line GL4 and the gate pulse supplied to the fifth gate line GL5 overlap, the data voltage of negative polarity (−) The odd-numbered pixel 116 connected to the fourth gate line GL4 precharged with 2B) has a data voltage 2A of negative polarity (-) for odd-numbered pixels from each data line DL by a gate pulse. And the odd-numbered pixel 116 connected to the fifth gate line GL5 reserves the data voltage 2A of the negative polarity (-) for the odd-numbered pixel from each data line DL by a gate pulse. Will be charged.

Accordingly, the even-numbered and odd-numbered pixels 116 connected to the left and right sides of each data line DL charge the negative data voltages 2B and 2A during the second horizontal period. At this time, the even-numbered pixel 116 is charged negatively at the preliminary charging voltage of positive polarity (+), while the odd-numbered pixel 116 is negatively charged at the preliminary charging voltage of negative-polarity (-). ) Is charged. Therefore, the final charging voltage of the even-numbered pixel 116 is lower than the final charging voltage of the odd-numbered pixel 116.

On the other hand, in the third to nth horizontal periods of the N frame period, the positive (+) or negative polarity is applied to the odd pixel column Po and the even pixel column Pe in the same manner as the first and second horizontal periods described above. The data voltage of negative polarity is charged.

As a result, in the N frame period, the data voltage is charged as shown by the arrow direction shown in FIG. Accordingly, the odd-numbered pixels 116 and the even-numbered pixels 116 alternately have different charging characteristics in units of horizontal periods in the N frame period.

That is, in odd-numbered horizontal periods, each odd-numbered pixel 116 has a different polarity of a voltage supplied during precharging and a polarity of a voltage supplied during charging, while each even-numbered pixel 116 has a voltage of a voltage supplied during preliminary charging. The polarity and the polarity of the voltage supplied during charging become the same. In the even-numbered horizontal period, each of the even-numbered pixels 116 has a different polarity of the voltage supplied at the time of precharging and a polarity of the voltage supplied at the time of charging. The polarity and the polarity of the voltage supplied during charging become the same.

Accordingly, since the charging voltages of the odd-numbered pixels 116 and the even-numbered pixels 116 are different in the N-frame period, a grid-shaped dim occurs on the image display unit 112. .

In order to eliminate the grid pattern dim generated in the N frame period, the data charging order is changed to be opposite to the N frame period in the N + frame period.

To this end, in the N + 1 frame period, as shown in FIG. 14, the data voltages 1B, 2B, 3B,. ) And data voltages for odd-numbered pixels (1A 2A, 3A, ...) are alternately supplied to each data line, and the phase pulses are delayed in units of 1/2 horizontal period to overlap the gate pulses 2, 1, 4, 3, 6, 5, 8, 7, ... are sequentially supplied to the gate line GL. At this time, even-numbered pixels 116 connected to the second gate line GL2 in the previous period of the first horizontal period may have arbitrary positive (+) data by the gate pulse supplied from the second gate driving circuit 160. Assume that the voltage is precharged.

In the first horizontal period of the N + 1 frame period, gate pulses superimposed from the first and second gate driving circuits 150 and 160 for 1/2 horizontal period are supplied to the second and first gate lines GL2 and GL1. do. Accordingly, during the first period of the first horizontal period in which the gate pulse supplied to the second gate line GL2 and the gate pulse supplied to the first gate line GL1 overlap, the positive data voltage is positive. The even-numbered pixel 116 connected to the pre-charged second gate line GL2 charges the data voltage 1B of the negative polarity (-) for the even-numbered pixel from each data line DL by the gate pulse. The odd-numbered pixel 116 connected to the first gate line GL1 precharges the negative-voltage (-) data voltage 1B for the even-numbered pixel from each data line DL by the gate pulse. .

Subsequently, the gate pulse is supplied to the fourth gate line GL4 so as to overlap the gate pulse supplied from the second gate driving circuit 160 to the first gate line GL1 for 1/2 horizontal period. Accordingly, during the second period of the first horizontal period in which the gate pulse supplied to the first gate line GL1 and the gate pulse supplied to the fourth gate line GL4 overlap, the negative data voltage (−) The odd pixel 116 connected to the first gate line GL1 precharged with 1B is a data voltage 1A of negative polarity (-) for the odd pixel from each data line DL by a gate pulse. And the odd-numbered pixel 116 connected to the fourth gate line GL4 reserves the data voltage 1A of the negative polarity (-) for the odd-numbered pixel from each data line DL by the gate pulse. Will charge.

Accordingly, odd-numbered and even-numbered pixels 116 connected to the left and right sides of each data line DL charge the negative data voltages 1B and 1A during the first horizontal period. At this time, the even-numbered pixel 116 is charged negatively at the preliminary charging voltage of positive polarity (+), while the odd-numbered pixel 116 is negatively charged at the preliminary charging voltage of negative-polarity (-). ) Is charged. Therefore, the final charging voltage of the even-numbered pixel 116 is lower than the final charging voltage of the odd-numbered pixel 116.

Then, in the second horizontal period of the N + 1 frame period, the third gate line GL3 is supplied with the gate pulse supplied from the first gate driving circuit 150 to the fourth gate line GL4 for a half horizontal period. The gate pulses are supplied to overlap. Accordingly, during the first period of the second horizontal period in which the gate pulse supplied to the fourth gate line GL4 and the gate pulse supplied to the third gate line GL3 overlap, the negative data voltage is negative. The odd-numbered pixel 116 connected to the fourth gate line GL4 precharged with (1A) has a data voltage of positive polarity (+) for odd-numbered pixels from each data line DL by a gate pulse. ) And the even-numbered pixel 116 connected to the third gate line GL3 receives the data voltage 2A of the positive polarity (+) for odd-numbered pixels from each data line DL by a gate pulse. It will be precharged.

Subsequently, the gate pulse is supplied to the sixth gate line GL6 so as to overlap the gate pulse supplied from the second gate driving circuit 160 to the third gate line GL3 for a half horizontal period. Accordingly, during the second period of the second horizontal period in which the gate pulse supplied to the third gate line GL3 and the gate pulse supplied to the sixth gate line GL6 overlap, the positive data voltage (+) The even-numbered pixel 116 connected to the third gate line GL3 precharged with 2A) has a data voltage of positive polarity (+) for even-numbered pixels from each data line DL by a gate pulse. And the odd-numbered pixel 116 connected to the sixth gate line GL6 reserves a data voltage 2B of positive polarity (+) for even-numbered pixels from each data line DL by a gate pulse. Will charge.

Accordingly, odd-numbered and even-numbered pixels 116 connected to the left and right sides of each data line DL charge the positive data voltages 2A and 2B during the second horizontal period. At this time, the odd-numbered pixel 116 is charged with positive polarity at the negative precharge voltage of negative (-), while the even-numbered pixel 116 is charged with positive polarity at the positive charge voltage of positive polarity (+). ) Is charged. Therefore, the final charging voltage of the odd pixel 116 is lower than the final charging voltage of the even pixel 116.

On the other hand, in the third to nth horizontal periods of the N + 1 frame period, the positive polarity (+) is applied to the even-numbered pixel columns Pe and the odd-numbered pixel columns Po in the same manner as the first and second horizontal periods described above. Or a negative data voltage is charged.

As a result, in the N + 1 frame period, the data voltage is charged as shown in the arrow direction shown in FIG. Accordingly, even-numbered pixels 116 and odd-numbered pixels 116 alternately have different charging characteristics in units of horizontal periods in the N + 1 frame period.

That is, in the odd-numbered horizontal periods, each of the even-numbered pixels 116 has a different polarity of the voltage supplied at the time of precharging and a polarity of the voltage supplied at the time of charging. The polarity and the polarity of the voltage supplied during charging become the same. In the even-numbered horizontal period, each of the odd-numbered pixels 116 has a different polarity of the voltage supplied at the time of precharging and a polarity of the voltage supplied at the time of charging. The polarity and the polarity of the voltage supplied during charging become the same.

Accordingly, in the N + 1 frame period, the lattice dim occurs on the image display unit 112 because the charging voltages of the odd-numbered pixels 116 and the even-numbered pixels 116 are different in units of horizontal periods.

Therefore, the driving device and driving method of the liquid crystal display according to the second embodiment of the present invention reverse the data charging order of pixels in frame units (N, N + 1) and charge data of adjacent pixels in horizontal period units. By reversing the order, the dim of the grid pattern generated during the line inversion driving of the image display unit 112 can be minimized.

Meanwhile, in the above-described driving apparatus and driving method of the liquid crystal display according to the first and second embodiments of the present invention, the data charging order of odd pixels and even pixels is reversed in units of frames, but the present invention is not limited thereto. In order to improve the image quality, the data charging order of odd and even pixels may be reversed in at least one frame unit.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The driving apparatus and driving method of the liquid crystal display according to the embodiment of the present invention as described above are vertical dim by changing the data charging order of odd-numbered pixel columns and even-numbered pixel columns arranged on both sides of the same data line during line inversion driving. The image quality can be improved by minimizing the

In addition, the driving device and the driving method of the liquid crystal display according to an exemplary embodiment of the present invention differ in order of filling data in odd-numbered pixel columns and even-numbered pixel columns on both sides of the same data line in a frame unit and horizontal period unit during line inversion driving. As a result, the image quality can be improved by minimizing the dim of the lattice pattern.

Claims (22)

An image display section having a plurality of data lines and a plurality of gate lines, the odd pixel column connected to a first side of each data line, and an even pixel column connected to a second side of each data line; A liquid crystal panel; A gate driver supplying gate pulses to the gate lines so that the order of charging the data voltages charged in the odd and even pixels is changed in units of frames; A plurality of data integrated circuits supplying the data voltages to the data lines so as to correspond to the charging order of the data voltages; And a timing controller for rearranging and supplying source data supplied from the outside to the respective data integrated circuits so as to correspond to the charging order of the data voltages, and for controlling the respective data integrated circuits and the gate driver. Drive of the device. The method of claim 1, In each horizontal period of N (where N is a positive integer) frame period, the data voltage is charged in the order of the odd pixel and the even pixel, And the data voltage is charged in the order opposite to the N frame in each horizontal period of the N + 1 frame period. The method of claim 2, Wherein each pixel of the odd-numbered pixel column is connected to an odd-numbered gate line, and each pixel of the even-numbered pixel column is connected to an even-numbered gate line. The method of claim 1, And the gate driver supplies a gate pulse to each of the gate lines such that the charging order of data voltages charged in the odd-numbered and even-numbered pixels is reversed in horizontal period units. The method of claim 4, wherein In the N frame period, the data charging order of the odd-numbered pixel and the even-numbered pixel is changed in units of horizontal periods so that the data voltage is charged. And the data voltage is charged in an order opposite to the N frame period in the N + 1 frame period. The method of claim 4, wherein Odd-numbered pixels of the odd-numbered pixel columns and even-numbered pixels of the even-numbered pixel columns are connected to odd-numbered gate lines, And an even-numbered pixel among the odd-numbered pixel columns and an odd-numbered pixel among the even-numbered pixel columns are connected to an even-numbered gate line. The method of claim 1, The timing controller, A data processor for rearranging the source data and supplying the source data to each data integrated circuit; A data control signal generator for generating a data control signal for controlling each of the data integrated circuits; And a gate control signal generator configured to generate a gate control signal including a plurality of gate shift clocks for generating a gate pulse corresponding to the charging order of the data voltage changed in units of frames, and to control the gate driver. A drive device for a liquid crystal display device. The method of claim 7, wherein And the plurality of gate shift clocks are delayed in phase such that they overlap each other in a 1/2 horizontal period. The method of claim 8, The gate driver, A first gate driving circuit sequentially supplying the gate pulses to odd-numbered gate lines by using a portion of the plurality of gate shift clocks delayed in horizontal period units; And a second gate driving circuit which sequentially supplies the gate pulses to even-numbered gate lines by using the remainder of the plurality of gate shift clocks delayed in horizontal period units. The method of claim 9, In the N frame period, the gate pulses are sequentially supplied in the order of the odd gate line and the even gate line. And the gate pulses are sequentially supplied in the order of the even-numbered gate line and the odd-numbered gate line in the N + 1 frame period. The method of claim 7, wherein The data processing unit, In the N frame period, the source data is rearranged in the order of the odd-numbered pixels and the even-numbered pixels to be supplied to the respective data integrated circuits. And in the N + 1 frame period, the source data is rearranged and supplied to each of the data integrated circuits in an order opposite to that of the N frame period. The method of claim 7, wherein The data processing unit, In the N frame period, the source data is rearranged so that the order of the odd-numbered pixels and the even-numbered pixels are reversed and supplied to each data integrated circuit in horizontal period units. And in the N + 1 frame period, the source data is rearranged in the order opposite to the N frame period and supplied to each of the data integrated circuits. An image display section having a plurality of data lines and a plurality of gate lines, the odd pixel column connected to a first side of each data line, and an even pixel column connected to a second side of each data line; A liquid crystal display comprising a liquid crystal panel; Supplying a gate pulse to each gate line such that a charging order of data voltages charged in the odd and even pixels is changed in units of frames; And supplying the data voltage to each data line so as to correspond to the charging order of the data voltage. The method of claim 13, In each horizontal period of the N frame period, the data voltage is charged in the order of the odd pixel and the even pixel. And the data voltage is charged in the order opposite to the N frame in each horizontal period of the N + 1 frame period. The method of claim 13, And supplying a gate pulse to each of the gate lines such that a charging order of data voltages charged in the odd-numbered and even-numbered pixels in a horizontal period is reversed. The method of claim 15, In the N frame period, the data charging order of the odd-numbered pixel and the even-numbered pixel is changed in units of horizontal periods so that the data voltage is charged. And the data voltage is charged in an order opposite to the N frame period in the N + 1 frame period. The method of claim 13, Rearranging the source data from the outside so as to correspond to the charging order of the data voltage; And generating a gate control signal including a plurality of gate shift clocks for generating the gate pulses so as to correspond to the charging order of the data voltages changed in the frame unit. Way. The method of claim 17, And the plurality of gate shift clocks are delayed in phase such that they overlap each other in a 1/2 horizontal period. The method of claim 18, Supplying a gate pulse to each gate line, Sequentially supplying the gate pulses to odd-numbered gate lines by using a portion of the plurality of gate shift clocks delayed by a horizontal period unit, And sequentially supplying the gate pulses to even-numbered gate lines by using the remainder of the plurality of gate shift clocks delayed by the horizontal period. The method of claim 19, In the N frame period, the gate pulses are sequentially supplied in the order of the odd gate line and the even gate line. And in the N + 1 frame period, the gate pulses are sequentially supplied in the order of the even-numbered gate lines and the odd-numbered gate lines. The method of claim 16, Reordering the source data, In the N frame period, the source data is rearranged in the order of the odd pixel and the even pixel, And in the N + 1 frame period, the source data is rearranged in a reverse order to the N frame period. The method of claim 16, Reordering the source data, In the N frame period, the source data is rearranged in units of horizontal periods such that the order of the odd-numbered pixels and the even-numbered pixels is reversed. And in the N + 1 frame period, the source data is rearranged in a reverse order to the N frame period.

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