KR20070024506A - Chip resistor - Google Patents

Abstract

A plurality of pairs of electrodes are formed on a sheet-like insulating substrate, a plurality of resistors to be connected with the plurality of pairs of electrodes are formed on the insulating substrate, and then a protective film covering the resistors is formed. Subsequently, the insulating substrate is split along split grooves formed longitudinally and latitudinally on the insulating substrate into chips. A plating layer is formed on the end electrodes. The split grooves are tapered and the electrode material and the protective film material are removed therefrom. Since projection of plating is minimized after formation of the electrode plating layer, and the split surface of the chip is shaped to absorb the projection of plating, there can be provided a chip resistor having further improved dimensional accuracy. ® KIPO & WIPO 2007

Description

Chip Resistor {CHIP RESISTOR}

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to chip resistors, and more particularly, to chip resistors aimed at further improvement in dimensional accuracy.

This application claims priority to patent application 2004-104384 for which it applied on March 31, 2004, and patent application 2005-68394 for which it applied on March 11, 2005, and uses the content for this application.

In recent years, there has been a trend toward thin and short electronic components, and 1005 type (size 10 × 0.5 mm resistor) has become mainstream also in surface mount type chip resistors, and 0603 type (size 0.6 × 0.3 mm resistor), 0402 Miniaturization is advancing to components of the type (size 0.4 x 0.2 mm of resistor). In addition, the mounting spacing of chip components is also required to increase the mounting density from about 0.2 mm to about 0.1 mm or less.

In addition, in the case where the tapping component is used for the supply and pickup of the chip resistor to the mounting apparatus, the clearance with the rectangular hole of taping is reduced, and the precision of the component shape is desired. In addition, in recent years, attention has been paid to bulk mounting in which dust and the like are less likely to be cleaned. However, even in bulk mounting, high precision of the shape of components is required to align and feed the feeder.

5 to 7 show the internal structure of the chip resistor according to the conventional method.

Conventionally, first, lattice-shaped dividing grooves 2 and 3 are provided on both surfaces (or one surface) of sheet-like insulating substrate 1 such as ceramics in the primary direction and the secondary direction (lateral direction and longitudinal direction) by a blade shape or the like. Put it.

Next, on the insulating substrate 1, a plurality of pairs of first upper electrodes 4a and a plurality of pairs of lower electrodes 5 are formed by printing with the primary dividing grooves 2 therebetween, and then the first The resistor 6 is formed by printing between the upper electrodes 4a, the resistor 6 is trimmed to adjust the resistance value, and then the protective film 7 is formed on the substrate by using glass or a resin material thereon. A plurality of resistors can constitute a chip resistor substrate.

Next, the insulating substrate 1 (that is, the chip resistor substrate) is divided into rectangles along the primary dividing grooves 2, and the terminal electrodes 11 are formed on the divided surfaces by sputtering, conductive paste, or the like. In addition, for the upper electrode, a second layer (second upper electrode) may be printed and formed along the primary dividing groove 2 for the purpose of preventing the inflow of sputter.

After the terminal electrodes are formed, the rectangular chip resistor substrate is divided by the secondary division grooves 3 to form a chip shape, and at the same time, a plating layer 8 made of Ni and Sn is formed on each electrode 11 at both ends of the chip. The chip resistor 10 shown in Fig. 8 is obtained.

By the way, in the chip resistor 10 according to the conventional method, the upper and lower electrodes, the protective film, and the like are also embedded in the dividing grooves 3 along the secondary side dividing surface, and the upper and lower electrodes that enter the dividing grooves when the secondary side is divided. In the formation process of the plating layer 8, Ni or Sn plating grows, protrudes greatly toward the ceramic side surface 10a of the chip resistor 10, and the terminal electrode (above the shape W1 in FIG. 9) or more. 11) was greatly grown (symbol W2 in Fig. 9), and this projected portion d was a cause of deterioration in shape dimensional accuracy.

Patent document 1 is disclosed as a technique for solving such a problem.

Patent Literature 1 discloses a slit (divided groove) for dividing (chips) a plurality of resistors formed on an insulating substrate into respective resistors after the protective film forming step, thereby smoothly dividing the insulating substrate to form a divided surface shape. Disclosed is a method of manufacturing a chip resistor that can be maintained with high accuracy.

Patent Document 1: Japanese Patent Laid-Open No. 2003-86408

In the technique disclosed in Patent Document 1, the slit cross section is formed into a sharp U-shaped groove using a laser beam for slit processing.

As described above, the formation of the slit after the electrode forming step or the protective film forming step including the electrode forming step prevents the adhesion and deposition of the electrode material and the protective film material in the slit, thereby smoothly dividing the insulating substrate. Although the dimensional accuracy of the divided surface shape can be maintained satisfactorily, since the slit shape has a U-shaped cross-sectional shape, the divided side surface of the chip is a vertical surface. When the plating layer is formed on this vertical surface, the plating protrusion due to the plating growth As it is, the width dimension of the chip is increased, which is a great obstacle in further improving the shape and dimensional accuracy of the chip resistor.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and the chip which aims to further improve chip dimensional accuracy by reducing the plating protrusion after forming the electrode plating layer as much as possible and making the chip dividing surface absorb the plating protrusion. It is an object to provide a resistor.

That is, according to one aspect of the present invention, there is provided a chip resistor substrate for manufacturing a chip resistor, the sheet-shaped insulating substrate, a plurality of pairs of electrodes formed on the substrate, and the plurality of pairs of electrodes formed on the insulating substrate. A plurality of resistors connected to the plurality of resistors, a protective film covering the resistors, and split grooves formed vertically and horizontally on the insulating substrate, thereby dividing the insulating substrate into chips, wherein the divided grooves have a taper. Further, a chip resistor substrate is provided in which at least the electrode material is removed in the division grooves.

In the structure of the chip resistor substrate, thereafter, in order to manufacture a chip resistor, the insulating substrate is divided into divided grooves to form a chip shape, and a plating layer is formed on both ends of the electrode (Ni, Sn plating) in the divided grooves. Since the electrode material does not exist, the growth of the plating is suppressed, and the protrusion of the plating can be suppressed as small as possible.

Preferably, in the chip resistor substrate, the by-product of forming the split grooves to be reattached to the edge portions of the split grooves has a height of 3 m or less and a width of 7 m or less.

In this configuration, by dramatically reducing the generation of scattering products (dross, etc.), the shape of the electrode edge portion of the chip resistors manufactured thereafter can be improved, and in particular, the conveyability of the chip resistors in bulk installation can be improved. have.

Preferably, in the chip resistor substrate, the thickness of the molten resolidification layer formed on the wall surface of the dividing groove at the time of forming the dividing groove is 1.5 m or less.

In this configuration, by reducing the thickness of the molten resolidified layer (glass layer) on the divided groove wall surface, the peeling of the glass layer of the chip resistors manufactured thereafter is prevented, and the disconnection of the plating layer or the like is prevented, and the glass layer is protruding. This can avoid the adverse effect on the carrier property of the chip resistor.

Preferably, the taper of the dividing groove in the chip resistance substrate is 1 ㎛ to 7 ㎛.

In this configuration, since the taper is given to the shape of the dividing groove, the dividing surface has a little taper in the dividing direction as compared with the dividing groove having the cross-sectional U-shape. The taper can be absorbed and the protrusion of the plating can be suppressed to 10 µm or less as described later, and the chip dimensional accuracy including electrode plating growth can be further improved. In addition, the taper here means the horizontal distance h from the edge part of a division groove to the groove bottom part in FIG.

Preferably, in the chip resistor substrate, the division grooves are processed with laser light having a wavelength of 360 nm or less.

In order to form a tapered divided groove, the laser groove and the machining parameter may be adjusted to optimize the divided groove width and the divided groove depth.

According to another aspect of the present invention, there is provided a chip resistor which divides the chip resistor substrate according to the division groove into a chip shape, and has a plating layer formed on both ends of the electrode.

Preferably, the plating protrusion after the electrode plating layer is formed in the chip resistor is 10 µm or less.

According to still another aspect of the present invention, a protective film for forming a plurality of pairs of electrodes on a sheet-shaped insulating substrate, forming a plurality of resistors connected to the plurality of pairs of electrodes on the insulating substrate, and covering the resistors. And forming a split groove vertically and horizontally in the insulating substrate, dividing the insulating substrate in accordance with the divided grooves to form a chip, and forming a plating layer on both ends of the electrode. A method of manufacturing a chip resistor is provided in which the dividing groove has a taper when forming a portion, and at least the electrode material is removed in the dividing groove.

1 is a cross-sectional view in a primary dividing direction showing the internal structure of a chip resistor according to the present invention.

Fig. 2 is a sectional view of the secondary dividing direction showing the internal structure of the chip resistor according to the present invention.

3 is a cross-sectional view of the chip end portion showing the internal structure of the chip resistor according to the present invention.

4 is an enlarged external perspective view of the chip resistor according to the present invention.

Fig. 5 is a sectional view of the primary dividing direction showing the structure of a conventional chip resistor.

Fig. 6 is a sectional view of the secondary dividing direction showing the internal structure of a conventional chip resistor.

7 is an enlarged external perspective view of a conventional chip resistor.

8 is an enlarged cross-sectional view showing a state of groove processing by a laser beam (UV laser) according to the present invention.

Fig. 9 is a sectional view of the chip end showing the internal structure of a conventional chip resistor.

[Description of the code]

1: insulating substrate (ceramic substrate)

2: Split groove (primary split groove)

3: Split groove (secondary divide groove)

4: upper electrode

5: lower electrode

6: resistor

7: protective film

8: plating layer

10: chip resistor

20: fly product (attachment)

21: molten resolidification layer (glass layer)

This invention aims at the improvement of the shape-dimensional precision of a chip resistor by making the plating protrusion after electrode plating layer formation in a chip resistor as small as possible. Hereinafter, embodiment of the chip resistor which concerns on this invention is shown to FIG. It demonstrates on a basis.

In addition, in order to simplify description, the same code | symbol was used about the member which is common in the following description.

1 to 3 show the internal structure of the chip resistor according to the present embodiment, and FIG. 4 shows an enlarged appearance of the chip resistor.

In the chip resistor 10 of the present embodiment, the upper electrodes 4a and 4b and the lower electrode 5 are formed on a sheet-shaped ceramic substrate in the same manufacturing process as the conventional method shown in Figs. (6) through the steps of adjusting the resistance value by trimming and forming the protective film 7, and then the primary splitting grooves 2 and the secondary splitting grooves 3 on both sides of the substrate by laser irradiation light. To form.

It is preferable to use the wavelength 360 nm or less (190-360 nm) which does not carbonize a resin layer in order to cut | disconnect the resin layer and electrode layer of a board | substrate for the laser beam L used for grooving.

The process of forming the dividing grooves 2 and 3 and the forming means are different from the conventional method. When the laser beam L is irradiated onto the ceramic substrate 1 containing the electrode material or the protective film material as shown in the figure, In the groove, the electrode material or the protective film material on the substrate can be vaporized by the laser light L to remove most of it. Of course, the division is smooth and no burr or the like occurs on the division surface.

8 shows the state of groove processing by the laser light (UV laser) having the above wavelength 360 nm.

For example, in the case of grooving with a YAG laser or the like, the by-products (dross and the like) removed by grooving are reattached in projection shape to both edges of the dividing groove 2 (3). This deposit 20 deteriorates the edge shape of the electrode mentioned later, and adversely affects the carrying property of the chip resistor at the time of bulk installation. In this embodiment, by using a UV laser, generation | occurrence | production of this flying product is made as small as possible, and the height H of the deposit 20 is 3 micrometers or less, and the width W is 7 micrometers or less. Thereby, an electrode shape can be improved and the conveyance of the chip resistor at the time of bulk installation can be improved.

In the groove processing, a molten resolidified layer 21 (glass layer 21) is formed on the wall surface of the divided groove 2 (3). Since the glass layer 21 is fragile and easily peels off and falls off, there is a possibility that a disconnection accident may occur in a plating layer or the like described below at the time of chip manufacturing, and the glass layer becomes a projection shape, which adversely affects the transferability of the chip resistor. In this embodiment, the thickness T of this glass layer 21 is reduced to 1.5 micrometers or less by using UV laser. Thereby, peeling and a fall of a glass layer can be prevented, disconnection accidents, such as a plating layer, can be prevented, the surface roughness of the wall surface of a division groove can be improved, and the conveyance of the chip resistor at the time of bulk mounting can be improved.

In addition, when the division grooves 2 (3) are formed by UV lasers, it is possible to have a taper angle suitable for the grooves from the processing conditions (irradiation beam parameters, processing parameters, etc.). In this embodiment, the processing conditions are optimized to have a slight taper h of 1 to 7 µm intentionally in the cross-sectional shape of the divided grooves 2 and 3.

Next, the ceramic substrate 1 is divided into rectangles along the primary dividing grooves 2, and the end surface electrodes 11 are formed on the divided surfaces by sputtering, conductive paste, or the like. Next, this rectangular chip resistor substrate is further divided along the secondary dividing groove 3 to form a chip shape.

At this time, the calculation section of each chip dividing surface 10a has a slight taper in the dividing direction. Next, each electrode 11 at both ends of the chip is subjected to Ni and Sn plating by a barrel plating method or the like to form a plating layer 8, thereby obtaining the chip resistor 10 shown in FIG.

After the Ni and Sn plating process, the plating layer 8 grows from the upper and lower electrodes at the ends of the secondary dividing grooves to the dividing side surface 10a side, but as described above, the electrode material and the protective film material in the dividing grooves are photochemically reacted by laser irradiation or high heat. Since most of the plating is removed by evaporation at, the protrusion of plating is very small, and since the taper has a taper suitable for the cross-sectional shape of the dividing grooves 2 and 3, the slight plating protrusion is absorbed by this taper, and the plating growth (d Can be suppressed to a size close to the chip split shape W1 as much as possible, whereby the chip resistor 10 having a very good shape dimensional accuracy can be obtained.

In taping and bulk mounting, the use of chip resistors with good dimensional accuracy enables high-density mounting with narrow desired adjacent spacing.

In order to confirm the effect of the present invention, 10 chip resistors according to the present invention and 10 chip resistors (comparative example) according to the conventional method were manufactured, and plating of the present invention (see Fig. 3) and the comparative example (see Fig. 9). The protrusion dimension d was measured and shown in Table 1, respectively.

In addition, the chip resistor is 0603 type, and the processing conditions of the dividing groove in this invention are as follows.

UV laser power (work position measurement output): 0.75W

Pulse repetition frequency: 30 KHz

Scan Speed: 20 mm / s

Number of injections: 1 time

Width of split groove: 12.1 ㎛

Depth of Split Groove: 42 ㎛

Table 1

 NO Plating protrusion dimension (d) (μm) Invention Comparative example One 7 16 2 8 21 3 5 10 4 6 20 5 6 11 6 8 8 7 7 22 8 5 17 9 8 9 10 7 12 AVE 6.7 14.6 MAX 8 22 MIN 5 8 Sigma 1.2 5.3

From the results in Table 1, the average value of the plated protrusion dimension (d) can be suppressed to less than half at 6.7 μm in the present invention with respect to 14.6 μm of the comparative example, and according to the present invention, the protrusion of the plated layer can be suppressed to 10 μm or less. I could confirm that it could.

In addition, as other confirmation matters, the transferability of the chip resistors to the size (H, W) of the fly ash (Table 2), and the peeling resistance (Table 3) to the thickness (T) of the resolidification layer, and the taper (h) It was investigated about the plating protrusion state (Table 4).

In each table, a mark ○ indicates a good state, and a mark △ shows a state slightly deteriorated.

[Table 2]

NO Height of flytail (H) (μm) Carriability Width of Wings (W) (㎛) Carriability One 1.02 ○ 3.35 ○ 2 2.1 ○ 5.31 ○ 3 3.05 ○ 6.99 ○ 4 6.2 △ 9.13 △

Table 3

NO Thickness of Resolidification Layer (T) (μm) Peeling resistance One 0.24 ○ 2 1.17 ○ 3 1.41 ○ 4 1.72 △

Table 4

NO Taper (h) (μm) Plated protrusion One 1.04 ○ 2 4.11 ○ 3 6.52 ○ 4 8.31 △

With respect to the fly products, if the height (H) is 6.2 μm or more and the width (W) is 9.13 μm or more from the results in Table 2, the carrier property is slightly adversely affected. It was set as follows. In addition, about the resolidification layer, since the peeling resistance fell slightly when the thickness T was 1.72 micrometers or more from the result of Table 3, in this invention, the thickness of the resolidification layer was 1.5 micrometers or less. In addition, about the taper, from the result of Table 4, when taper h is 8.31 micrometers or more, plating protrusion will become large and it will become difficult to ensure 10 micrometers or less of plating protrusion dimensions, In this invention, taper was 1-7 micrometers or less.

As described above, according to the present invention, since the dividing groove of the insulating substrate has a taper and the electrode material is removed in the dividing groove, the plating growth after forming the electrode plating layer is suppressed to actively protrude the plating on the dividing side surface. Since the plating protrusion can be absorbed by the taper of the divided surface, the chip shape dimensional accuracy including the plating growth can be improved.

Chip resistors with good dimensional accuracy enable high-density mounting with narrow adjacent spacing in taping and bulk mounting, and have very few melt resolidification layers on the wall of the dividing grooves and reattachment of fly-byes generated by the formation of the dividing grooves. In addition, the conveyance of the chip in bulk mounting can be remarkably improved.

Claims (8)

A chip resistor substrate for manufacturing chip resistors, A sheet-shaped insulating substrate, A plurality of pairs of electrodes formed on the substrate, A plurality of resistors formed on the insulating substrate and connected to the plurality of pairs of electrodes; A protective film covering the resistor; It is provided in the said insulating board longitudinally and horizontally, and divides an insulating board along this, and has the dividing groove which makes chip shape, The chipping substrate, wherein the split groove has a taper and at least the electrode material is removed in the split groove. The chip resistor substrate according to claim 1, wherein the by-products in forming the divided grooves to be reattached to the edge portions of the divided grooves have a height of 3 m or less and a width of 7 m or less. The chip resistor substrate according to claim 1 or 2, wherein the thickness of the molten resolidified layer formed on the wall surface of the divided grooves at the time of forming the divided grooves is 1.5 µm or less. The chip resistor substrate according to any one of claims 1 to 3, wherein the taper of the dividing grooves is 1 µm to 7 µm. The chip resistor substrate according to any one of claims 1 to 4, wherein the division grooves are processed with a laser beam having a wavelength of 360 nm or less. The chip resistor which divides the chip resistor board | substrate of any one of Claims 1-5 into the said chip | tip by the said dividing groove | channel, and has a chip resistor, Comprising: The chip resistor provided with the plating layer formed in the electrode of both ends. The chip resistor according to claim 6, wherein the plating protrusion after the electrode plating layer is formed is 10 mu m or less. A plurality of pairs of electrodes are formed on the sheet-shaped insulating substrate, A plurality of resistors connected to the plurality of pairs of electrodes are formed on the insulating substrate, Forming a protective film covering the resistor, Forming division grooves in the insulating substrate vertically and horizontally; A method of manufacturing a chip resistor for dividing the insulating substrate in accordance with the dividing groove into a chip shape, and at the same time forming a plating layer on both ends of the electrode, And the dividing groove has a taper when forming the dividing groove, and at least the electrode material is removed in the dividing groove.

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