KR20070020984A - MOS transistor having a recessed gate electrode and fabrication method thereof - Google Patents

Abstract

Provided are a MOS transistor having a recessed gate electrode and a method of manufacturing the same. The MOS transistor has a channel trench that crosses the semiconductor substrate. A lower gate pattern is provided that partially fills the channel trench. An upper gate pattern is disposed on the lower gate pattern. The upper gate pattern has a central axis that does not coincide with the central axis of the channel trench and has a width smaller than the width of the channel trench. A sub trench that exposes a portion of the lower gate pattern is disposed under the upper gate pattern. A gate spacer covering one sidewall of the upper gate pattern is disposed in the sub trench. An insulating pattern is disposed under the gate spacer. The insulating pattern covers the exposed lower gate pattern. A method of manufacturing a MOS transistor having the recessed gate electrode is also provided.

Description

MOS transistor having a recessed gate electrode and a manufacturing method thereof

1 is a cross-sectional view illustrating a MOS transistor having a recessed gate electrode according to the prior art.

2 to 8 are cross-sectional views illustrating a method of manufacturing a MOS transistor having a recessed gate electrode according to an exemplary embodiment of the present invention.

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MOS transistor having a recessed gate electrode and a method of manufacturing the same.

As the degree of integration of semiconductor memory devices such as DRAM devices increases, the planar area occupied by MOS transistors decreases. As a result, the channel length of the MOS transistor is reduced to generate a short channel effect. In particular, when the short channel effect occurs in an access MOS transistor adopted in the memory cell of the DRAM device, the threshold voltage of the DRAM cell is decreased and the leakage current is increased to degrade the refresh characteristic of the DRAM device. Accordingly, a MOS transistor having a recessed gate electrode has been introduced as a MOS transistor capable of suppressing a short channel effect by increasing the gate channel length even if the integration degree of the DRAM device is increased.

The MOS transistor having the recessed gate electrode partially recesses the semiconductor substrate to form a gate in the recessed region, and forms a source / drain in the silicon substrate on both sides of the gate.

A MOS transistor having a recessed gate electrode according to the related art has a channel trench that crosses a predetermined region of a semiconductor substrate. A gate insulating layer covering an inner wall of the channel trench is disposed. A gate pattern crossing the semiconductor substrate is disposed to fill the channel trench surrounded by the gate insulating layer. The gate pattern includes a gate conductive layer pattern and a gate capping layer pattern. In this case, the gate pattern has an outer gate shape having a width equal to or larger than that of the channel trench. The outer gate has an electric field concentration phenomenon in an upper edge region of the semiconductor substrate adjacent to the gate conductive layer pattern. Due to the electric field concentration phenomenon, there is a disadvantage in that the threshold voltage characteristic of the device is lowered and the leakage current is increased.

Meanwhile, in order to prevent electric field concentration at the upper edge of the semiconductor substrate adjacent to the gate conductive layer pattern, a method of forming an inner gate shape in which the width of the gate pattern is smaller than the width of the channel trench has been attempted. .

1 is a cross-sectional view illustrating a MOS transistor having an inner gate electrode according to the prior art.

Referring to FIG. 1, an active region is disposed in a predetermined region of the semiconductor substrate 1. The active region is a region defined by an isolation layer (not shown). The channel trench 3 is disposed across the predetermined area of the active area. The gate insulating film 5 covering the inner wall of the channel trench 3 is disposed. A gate pattern 11 is disposed across the active region while filling the channel trench 3 surrounded by the gate insulating layer 5. The gate pattern 11 includes a polysilicon layer pattern 7 and a gate capping layer pattern 9. A gate spacer 13 surrounding sidewalls of the gate pattern 11 is disposed. The source / drain 15 is disposed in the active regions at both lower sides of the gate pattern 11. A self-aligned contact pad 17 insulated from the polysilicon layer pattern 7 by the gate spacer 13 is disposed on the active region where the source / drain 15 is formed.

As the size of the gate pattern 11 decreases, misalignment may occur as shown in FIG. 1. Therefore, even when the gate spacer 13 surrounding the sidewall of the gate pattern 11 is disposed, a region A through which the polysilicon layer pattern 7 is exposed may be formed. The exposed region A may cause an electrical short circuit between the polysilicon layer pattern 7 and the self-aligned contact pad 17.

It is an object of the present invention to provide a MOS transistor having an improved recessed gate electrode capable of preventing an electrical short circuit with a self-aligned contact pad even when the gate pattern is misaligned, and a method of manufacturing the same.

According to an aspect of the present invention for achieving the above technical problem, a MOS transistor having a recessed gate electrode is provided. The MOS transistor includes a channel trench that crosses the semiconductor substrate and a lower gate pattern that partially fills the channel trench. An upper gate pattern having a width smaller than that of the channel trench is disposed on the lower gate pattern. The upper gate pattern has a central axis that does not coincide with the central axis of the channel trench. A sub trench disposed below the upper gate pattern and exposing a portion of the lower gate pattern is provided. A gate spacer covering one sidewall of the upper gate pattern is disposed in the sub trench. An insulating pattern is provided below the gate spacer to cover the exposed lower gate pattern.

A gate insulating layer covering an inner wall of the channel trench may be provided.

The insulating pattern may be a silicon oxide layer pattern.

Source / drain may be provided on both side surfaces of the channel trench.

According to another aspect of the present invention for achieving the above technical problem, there is provided a MOS transistor manufacturing method having a recessed gate electrode. The method of manufacturing the MOS transistor includes forming a channel trench that crosses the semiconductor substrate and forming a gate layer covering the semiconductor substrate while filling the channel trench. The gate layer is patterned to form a gate pattern having a central axis that does not coincide with the central axis of the channel trench and having a width smaller than the width of the channel trench, and a sub trench exposing a portion of the gate pattern. A gate spacer covering sidewalls of the gate pattern is formed. An insulating pattern is formed to fill the sub trench.

Forming the insulating pattern may include forming an insulating film on the semiconductor substrate having the gate spacer and etching back the insulating film.

The insulating pattern may be formed of a silicon oxide layer.

Source / drain may be formed on both side surfaces of the channel trench.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

2 to 8 are cross-sectional views illustrating a method of manufacturing a MOS transistor having a recessed gate electrode according to an exemplary embodiment of the present invention.

Referring to FIG. 2, an isolation layer (not shown) is formed on the semiconductor substrate 101 to define an active region. A mask film pattern having an opening is formed on the substrate having the active region. The channel trench 103 crossing the active region is formed using the mask layer pattern as an etching mask. As illustrated in FIG. 1, the channel trench 103 may have an upper width greater than a lower width. Alternatively, it may have a vertical profile or may have a profile including a curved surface. After the channel wrench 103 is formed, the mask layer pattern is removed.

Referring to FIG. 3, a gate insulating layer 105 is formed on a substrate from which the mask layer pattern is removed. The gate insulating layer 105 is formed on an inner wall of the channel trench 103 and an upper surface of the semiconductor substrate 101. The gate insulating layer 105 may be formed of a thermal oxide layer.

A gate layer 113 is formed on the substrate having the gate insulating layer 105 to cover the semiconductor substrate 101 while filling the channel trench 103. The gate layer 113 may include a polysilicon layer 107, a metal silicide layer 109, and a gate capping layer 111 that are sequentially stacked.

Referring to FIG. 4, the gate layer 113 is patterned to form a gate pattern 113c having a width smaller than an upper width of the channel trench 103. In this case, the gate pattern 113c may be misaligned so that the central axis of the gate pattern 113c does not coincide with the central axis of the channel trench 103. In this case, a part of the polysilicon layer 107 may be recessed than the upper surface of the semiconductor substrate 101 to form a sub-trench 115. The gate layer 113 patterned by the patterning process becomes the upper gate pattern 113b, and the upper gate pattern 113b includes the stacked polysilicon layer pattern 107b, the metal silicide layer pattern 109b, and the gate cage. It may be composed of a ping film pattern 111b. The polysilicon layer 107 remaining on the lower portion of the upper gate pattern 113b and the lower portion of the sub trench 115 to fill the channel trench 103 forms a lower gate pattern 113a. The upper gate pattern 113b and the lower gate pattern 113a constitute a gate pattern 113c.

Referring to FIG. 5, a gate spacer 117 may be formed to surround sidewalls of the upper gate pattern 113b. The gate spacer 117 may be formed by forming a spacer insulating layer on the substrate having the gate pattern 113c and anisotropically etching the spacer insulating layer. The spacer insulating film may be formed of a silicon nitride film. In this case, the gate spacer 117 formed in the sub trench 115 may be formed on the lower gate pattern 113a and may expose a portion of the upper portion of the lower gate pattern 113a.

Referring to FIG. 6, an additional insulating layer 119 is formed on a substrate having the gate spacer 117. The additional insulating layer 119 is formed to cover the lower gate pattern 113a by filling the sub trench 115. The additional insulating layer 119 may be formed of a silicon oxide layer. The additional insulating layer 119 may be formed to have a thickness of about 1/4 or more and 1/2 or less of the upper width of the channel trench 103.

Referring to FIG. 7, the additional insulating layer 119 is etched until the upper surface of the semiconductor substrate 101 is exposed to form an insulating pattern covering the exposed lower gate pattern 113a while remaining in the sub trench 115. 119a is formed. The etching process may be performed using an etch back process.

The exposed lower gate pattern 113a may be electrically insulated from the self-aligned contact pads formed after the insulating pattern 119a. That is, since the gate pattern 113c is misaligned and a part of the gate pattern 113c is exposed even after the gate spacer 117 is formed, an electrical short circuit with the self-aligned contact pad can be prevented.

Referring to FIG. 8, impurity ions are implanted into semiconductor substrates adjacent to the channel trench 103 by using the gate pattern 113c, the gate spacer 117, and the insulating pattern 119a as an ion implantation mask. The source / drain 121 may be formed. Thereafter, a self-aligning contact pad 123 may be formed to be self-aligned to the gate spacer 117.

According to the related art, when the gate pattern is misaligned and a part of the gate pattern is exposed, an electrical short circuit with the self-aligning contact pad may occur. On the other hand, according to the present invention, the insulating pattern 119a is provided to prevent the electrical short circuit phenomenon.

Referring to FIG. 8 again, a structure of a MOS transistor having a recessed gate electrode according to an embodiment of the present invention will be described.

Referring to FIG. 8, an active region defined by an isolation layer (not shown) is provided in a predetermined region of the semiconductor substrate 101. A channel trench 103 is provided across the active region. The inner wall of the channel trench 103 is covered with the gate insulating layer 105. A lower gate pattern 113a is provided on the gate insulating layer 105 to partially fill the channel trench 103. The lower gate pattern 113a may be a polysilicon layer. An upper gate pattern 113b is disposed on the lower gate pattern 113a and has a central axis that does not coincide with the central axis of the channel trench 103 and has a width smaller than that of the channel trench 103. The upper gate pattern 113b may include a stacked polysilicon layer pattern 107b, a metal silicide layer pattern 109b, and a gate capping layer pattern 111b. A sub trench 115 is disposed under the upper gate pattern and exposes a portion of the lower gate pattern. A gate spacer 117 is disposed in the sub trench 115 to cover one sidewall of the upper gate pattern 113b. The gate spacer 117 is also formed on the other sidewall of the upper gate pattern 113b. The gate spacer 117 may be formed of a silicon nitride layer. The gate spacer 117 disposed in the sub trench 115 may cover a portion of the lower gate pattern 113a exposed by the sub trench 115. An insulating pattern 119a is disposed under the gate spacer 117 to cover the exposed lower gate pattern. The insulating pattern 119a may be formed of a silicon oxide layer. Source / drain 121 may be provided on the semiconductor substrate 101 at both sides of the channel trench 103. A self-aligning contact pad 123 electrically connected to the source / drain 121 may be provided.

According to the present invention, even when the gate pattern 113c is misaligned and a part of the lower gate pattern 113a is exposed, the lower gate pattern 113a and the self-aligning contact pad (exposed to the insulating pattern 119a) are exposed. It is interposed between the 123 to prevent the electrical short circuit phenomenon.

According to the present invention made as described above, by providing an additional insulating pattern, even if the gate pattern is misaligned to expose a portion of the gate pattern to prevent the risk of electrical short-circuit with the subsequent self-aligned contact pads may occur. can do.

Claims (8)

Channel trenches across the semiconductor substrate; A lower gate pattern partially filling the channel trench; An upper gate pattern disposed on the lower gate pattern, the upper gate pattern having a central axis not coincident with the central axis of the channel trench and having a width smaller than the width of the channel trench; A sub trench disposed under the upper gate pattern and exposing a portion of the lower gate pattern; A gate spacer disposed in the sub trench to cover one sidewall of the upper gate pattern; And And a recessed gate electrode disposed under the gate spacer and including an insulating pattern covering the exposed lower gate pattern. The method of claim 1, And a gate insulating film covering an inner wall of the channel trench. The method of claim 1, And the insulating pattern is a silicon oxide film pattern. The method of claim 1, And a source / drain disposed on the semiconductor substrate on both sides of the channel trench. Form a channel trench across the semiconductor substrate, Forming a gate film covering the semiconductor substrate while filling the channel trench; Patterning the gate layer to form a gate pattern having a central axis not coincident with the central axis of the channel trench and having a width smaller than the width of the channel trench and a sub trench exposing a portion of the gate pattern; Forming a gate spacer covering sidewalls of the gate pattern, And forming a dielectric pattern filling the sub trench. The method of claim 5, wherein Forming the insulating pattern is An insulating film is formed on the semiconductor substrate having the gate spacer, And etching back said insulating film. The method of claim 5, wherein And the insulating pattern is formed of a silicon oxide film. The method of claim 5, wherein And forming a source / drain in the semiconductor substrate on both sides of the channel trench.

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