KR20070005336A - Plasma display panel - Google Patents

Abstract

A plasma display panel is provided to reduce capacitance between address electrodes and to reduce power consumption by assigning two address electrodes to one pixel. A front substrate(110) and a rear substrate(140) are disposed opposite to each other. A barrier rib(170) is formed between the front and rear substrates in order to define discharge cells. One pixel is formed with three discharge cells for emitting visible rays of different colors. Y and X display electrodes(122,124) are formed between the front and rear substrates. Two address electrodes are assigned to one pixel. An intermediate electrode(126) corresponding to each discharge cell is disposed between the Y and X display electrodes.

Description

Plasma Display Panel

1 is an exploded perspective view of a plasma display panel according to a first embodiment of the present invention;

2 is a plan view of a discharge cell and electrodes according to the first and second embodiments of the present invention;

3A is a cross-sectional view of a plasma display panel according to a first embodiment of the present invention.

3B is a cross-sectional view of a plasma display panel according to a second embodiment of the present invention.

4 is a driving waveform diagram according to a first embodiment and a second embodiment of the present invention;

5A to 5E are wall charge distribution diagrams according to the driving waveform of FIG. 4.

<Description of Symbols for Major Parts of Drawings>

100-PDP 110-Front Board

120-display electrode 122, 122 '-Y display electrode (Y electrode)

124, 124 '-X display electrode (X electrode) 126-intermediate electrode (M electrode)

122a, 124a, 126a-bus electrode 130-upper dielectric layer

135-Protective Layer 140-Back Board

150-address electrode (A electrode) 160-lower dielectric layer

170-bulkhead 180-phosphor layer

190-Pixels 191, 192, 193-Discharge Cells

The present invention relates to a plasma display panel, and more particularly, to a partition structure having a delta partition wall in which two address electrodes are assigned to one pixel instead of a conventional delta partition wall in which three address electrodes are assigned to one pixel. The present invention relates to a plasma display panel in which light emission efficiency is improved by providing an additional intermediate electrode and lowering discharge voltage.

In general, a plasma display panel (hereinafter referred to as a PDP) is a display device that realizes an image by using visible light generated by excitation of a phosphor by vacuum ultraviolet rays (VUV) emitted from a plasma obtained through gas discharge. to be. Such a PDP can realize an ultra-large screen of 60 inches or more with a thickness of only 10 cm or less, and is a self-luminous display device such as a CRT. In addition, since the manufacturing method is simpler than LCD, it has advantages in terms of productivity and cost, and thus, it is being spotlighted as the next-generation industrial flat panel display and home TV display.

Such a conventional PDP generally includes a front substrate having a plurality of display electrodes and a back substrate having a plurality of address electrodes to intersect the display electrodes. In addition, a plurality of partition walls are formed between the front substrate and the rear substrate so as to partition the plurality of discharge regions. There are various structures of such a partition, such as stripe type, matrix type, and delta type.

Among these, in the case of a PDP having a delta partition, three discharge cells are normally adjacent to each other to form one pixel. Each of the discharge cells has a red (R) fluorescent layer, a green (G) fluorescent layer, and a blue (R) fluorescent layer. Three address electrodes are normally assigned to one pixel.

On the other hand, in recent years, as the resolution of the PDP is increased, that is, as the resolution is increased, the number of address electrodes gradually increases and the pitch between the address electrodes is also reduced. However, as is well known, as the pitch between address electrodes decreases, the capacitance value between address electrodes increases, and energy calculated as approximately CV ² f is consumed between the address electrodes. In other words, it is necessary to increase the power consumption of the address electrode to make a high resolution PDP. Since a discharge voltage much larger than that of the display electrode is applied to the address electrode, an increase in power consumption of the address electrode is directly connected to an increase in power consumption of the entire PDP. Here, C is a capacitance value generated between address electrodes, V is a voltage applied to the address electrode, and f is a frequency applied to the address electrode.

As the size of the cell becomes smaller, the amount of phosphor decreases due to the high resolution, which is a major trend of PDP technology. Therefore, since the luminance is reduced, an increase in the discharge voltage is inevitable in order to have an appropriate luminance. In addition, when the resolution is high, the wall charges are not sufficiently formed on the electrodes because there are not enough charged particles in the discharge space. Therefore, the discharge voltage rises. For high efficiency, another main trend of PDP technology, high discharge voltage is required to use high Xe partial pressure gas. Accordingly, there is a need to propose a barrier rib structure that can reduce capacitance between address electrodes due to high resolution, and an electrode structure that can suppress an increase in discharge voltage due to high resolution.

The present invention has been made to solve the above problems caused by the high resolution of the PDP, and forms a cell structure in which two address electrodes are allocated per pixel for pixels of adjacent R, G, and B subpixels. The purpose of the present invention is to provide a PDP which realizes high efficiency by reducing the capacitance between the electrodes and adding an intermediate electrode between the display electrodes to lower the discharge voltage.

Plasma display panel according to an embodiment of the present invention for achieving the above object, three discharges are formed between the front substrate and the rear substrate facing each other, the front substrate and the rear substrate and emits visible light of different colors A partition wall partitioning the discharge cells so that the cells are adjacent to each other and forming one pixel; one display cell including Y display electrodes and X display electrodes formed between the front substrate and the rear substrate; Two address electrodes are allocated to the pixel, and an intermediate electrode is disposed between the Y display electrode and the X display electrode to correspond to each discharge cell. In this case, one address electrode may be commonly allocated to two selected discharge cells among the three discharge cells constituting the one pixel, and another address electrode may be allocated to the other discharge cell.

In addition, the Y display electrode and the X display electrode may be formed parallel to each other on the rear surface of the front substrate. In this case, the intermediate electrode may be positioned on the rear surface of the front substrate and may be formed between the Y display electrode and the X display electrode. In this case, the Y display electrode, the X display electrode, and the intermediate electrode may include a transparent electrode and a bus electrode.

In addition, the Y display electrode and the X display electrode may be formed in parallel to each other in the partition wall. In this case, the Y display electrode and the X display electrode may be formed of a metal electrode.

In addition, the Y display electrode and the X display electrode may be formed in the transverse direction along the partition wall. In this case, a discharge cell coated with phosphors having different colors is formed around the Y display electrode and the X display electrode. It may be formed to contact.

The intermediate electrode may be formed in parallel with the Y display electrode and the X display electrode. In addition, the discharge cells may be any one of a triangular shape, a square shape, a rhombus shape, and a hexagonal shape. The discharge cells may be repeatedly arranged in plurality along one address electrode, and each discharge cell may have different colors of visible light. Can be arranged to emit light.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

1 is an exploded perspective view of a plasma display panel according to a first embodiment of the present invention. 2 is a plan view of a discharge cell according to the first or second embodiment of the present invention. FIG. 3A is a cross-sectional view (KK cross-sectional view of FIG. 2) of a plasma display panel according to a first embodiment of the present invention, and FIG. 3B is a cross-sectional view (KK cross-sectional view of FIG. 2) of a plasma display panel according to a second embodiment of the present invention. to be.

In the plasma display panel 100 according to the first embodiment of the present invention, referring to FIGS. 1 to 3A, the front substrate 110, the rear substrate 140, the Y display electrodes 122, and the X display electrode ( 124 and the intermediate electrode 126 is formed. In addition, the Y display electrodes 122, the X display electrodes 124, and the intermediate electrodes 126 are covered by the upper dielectric layer 130, and the upper dielectric layer 130 is protected by the protective layer 135. In addition, the address electrodes 150 are covered by the lower dielectric layer 160, and the phosphor layers 180 absorbing vacuum ultraviolet rays and emitting visible light inside discharge cells 191, 192, and 193 partitioned by the barrier rib 170. And a discharge gas for generating vacuum ultraviolet rays by plasma discharge.

The back substrate 140 is formed of a material such as glass having a predetermined thickness to form the plasma display panel 100 together with the front substrate 110. The rear substrate 140 is formed with address electrodes 150 disposed in one direction on the upper surface facing the front substrate 110 and a lower dielectric layer 160 applied to cover the address electrodes 150. The partition wall 170 is formed on the dielectric layer 160. The phosphor layer 180 is formed on the lower dielectric layer 160 and the partition wall 170. Hereinafter, the front substrate 110 direction (the + z direction in FIG. 1) will be divided into the upper direction, and the back substrate 140 direction (the -z direction in FIG. 1) will be described in the lower direction.

The front substrate 110 is formed of a transparent material such as soda glass, and is formed to face the rear substrate 140. The Y display electrodes 122, the X display electrodes 124, and the intermediate electrode 126 are arranged side by side under the front substrate 110, and the Y display electrodes 122 and the X display electrodes 124 are arranged side by side. And the intermediate electrodes 126 are covered by the upper dielectric layer 130, and the upper dielectric layer 130 is protected by the protective layer 135.

The partition wall 170 may be formed to a predetermined thickness on the surface of the lower dielectric layer 160 formed on the rear substrate 140 as shown in FIG. 1, or may be formed separately from the rear substrate 140. The partition wall 170 may be formed of any one selected from triangular, square, rhombus, pentagonal, and hexagonal. Although the partition wall 170 of the hexagonal shape is shown in the figure, it does not limit the present invention in this form. That is, the present invention is applicable to all the partition walls 170 of the closed type. The partition wall 170 maintains a gap between the front substrate 110 and the rear substrate 140 and partitions the discharge cells 191, 192, and 193.

The barrier rib 170 is formed such that three discharge cells 191, 192, and 193 emitting visible light having different colors are adjacent to each other in a substantially triangular form to form one pixel 190. Here, two address electrodes 150 are allocated to one pixel 190 divided by the partition wall 170. That is, one address electrode 150 is commonly assigned to two discharge cells 192 and 193 selected from three discharge cells 191, 192, and 193, and another address electrode is assigned to the other discharge cell 191. 150 may be assigned.

The barrier rib 170 may be formed by screen printing, sand blasting, lift-off, etching, or the like, but the method of forming the barrier rib 170 is not limited thereto. In addition, the partition wall 170 is formed of a glass component containing elements such as Pb, B, Si, Al and O, preferably zirconium oxide (ZrO 2), titanium oxide (TiO 2), aluminum oxide (Al 2 O 3) and It is formed of a dielectric including the same filler and pigments such as chromium (Cr), copper (Cu), cobalt (Co), iron (Fe) and the like. However, the components of the barrier rib 170 are not limited thereto, but may be formed of various dielectric materials.

The upper dielectric layer 130 covers the entire lower surface of the front substrate 110 including the display electrode 120. The upper dielectric layer 130 may be formed by uniformly screen printing a paste including a low melting point glass powder on the entire lower surface of the front substrate 110. The upper dielectric layer 130, as is well known, is a transparent body, acts as a capacitor during discharge, limits the current, and performs a memory function. In addition, a protective layer 135 may be further formed on the surface of the upper dielectric layer 130 to reinforce durability and to emit many secondary electrons during discharge. The protective layer 135 may be formed by an electron beam method or sputtering using any one selected from magnesium oxide (MgO) or equivalents thereof, but the material of the protective layer and the method of forming the protective layer 135 are not limited thereto.

The lower dielectric layer 160 covers the entire upper surface of the back substrate 140 including the address electrode 150. The lower dielectric layer 160 may also be formed of a material similar to or the same as the upper dielectric layer 130.

The address electrodes 150 are formed on an upper side of the rear substrate 140 toward the upper dielectric layer 130 of the front substrate 110. The address electrode 150 has a predetermined pitch on the top surface of the back substrate 140 and is formed in parallel with each other. The address electrode 150 is formed in a direction substantially crossing the display electrode 120. One address electrode 150 is formed to pass through discharge cells 191, 192, and 193 that emit visible light of different colors, respectively, or through different fluorescent layers 180 (y direction in FIG. 1). The address electrode 150 may be formed by sputtering, screen printing, photolithography or the like using Ag paste or the like, but the present invention is not limited to the material and the method of forming the address electrode 150.

The display electrode 120 has a predetermined pitch on the lower surface of the front substrate 110 and is formed in parallel with each other. The display electrode 120 is a pair of the Y display electrode 122 and the X display electrode 124. The display electrode 120 may be formed of any one selected from ITO (an alloy oxide film of In and Sn) having good light transmittance, a nesa film (SnO 2), or an equivalent thereof, but the present invention is not limited thereto. In addition, the display electrode 120 may be formed mainly by sputtering, but the present invention is not limited thereto. In addition, bus electrodes 122a and 124a having low resistance may be further formed on the surface of the display electrode 120 to prevent a voltage drop. The bus electrodes 122a and 124a may be formed of any one selected from Cr-Cu-Cr, Ag, or equivalents thereof, but the present invention is not limited thereto.

Referring to FIG. 2, the display electrode 120 is formed in the transverse direction along the partition wall 170. For example, the Y display electrode Y1 is formed while enclosing the R discharge cells and the G discharge cells laterally. The X display electrode X1 is formed while enclosing the G discharge cells and the B discharge cells laterally. Accordingly, discharge cells coated with phosphors having different colors are in contact with the Y display electrode 122 and the X display electrode 124. For example, the X display electrode X1 forms a boundary between an R discharge cell and a G discharge cell, and also forms a boundary between a G discharge cell and a B discharge cell. The reason for placing the display electrode 120 on the partition wall 170 is to solve the problem of narrowing the discharge space according to the high definition of the PDP. Between the Y display electrode 122 and the X display electrode 124 constituting the display electrode 120, an intermediate electrode corresponding to each discharge cell and parallel to the Y display electrode 122 and the X display electrode 124 is formed. 126 is formed. Accordingly, the intermediate electrode 126 is positioned on the rear surface of the front substrate 110 together with the display electrode 120.

Like the display electrode 120, the intermediate electrode 126 also includes a transparent electrode and a bus electrode, and is covered by the upper dielectric layer 130. The intermediate electrode 126 is a bus electrode 126a that extends long over the discharge cell in a direction (x direction) crossing the address electrode 150, and the Y display electrode 122 from the bus electrode 126a. And transparent electrodes 126 protruding toward each of the X display electrodes 124. At this time, the bus electrode 126a is preferably made of a metal electrode in order to compensate for the high resistance of the transparent electrode to secure the electrical conductivity.

The intermediate electrode 126 may be involved in reset discharge in a reset period. In the addressing period, the intermediate electrode 126 is involved in selecting a discharge cell to be displayed while causing an address discharge between the address electrode 150 and the address electrode 150. However, the role thereof may vary depending on the discharge voltage applied to each electrode, and the present invention is not limited thereto. As the addressing is performed using the intermediate electrode 126 and the address electrode 150, the opaque bus electrodes 122a and 124a that block light generated from the phosphor can be positioned above the barrier 170. The brightness is improved. In addition, as the discharge between the display electrodes 120 becomes a discharge during the sustain discharge period, the gap between the display electrodes 120 increases, which leads to an increase in discharge efficiency.

The phosphor layer 180 has a component for generating visible light by receiving ultraviolet rays. The red phosphor layer formed in the red light emitting discharge cell includes a phosphor such as Y (V, P) O4: Eu, and the green light emitting discharge cell. The green phosphor layer formed at includes a phosphor such as Zn 2 SiO 4: Mn, and the blue phosphor layer formed at the blue light emitting discharge cell may be formed including a phosphor such as BAM: Eu. Accordingly, the phosphor layer 180 is divided into red, green, and blue light emitting phosphor layers, and is formed in each of the discharge cells 191, 192, and 193 adjacent to each other, and the red, green, and blue light emitting phosphor layers are formed. The formed discharge cells 191, 192, and 193 are combined to form unit pixels for implementing a color image.

Looking at the relationship between the phosphor layer 180 and the address electrode 150, one address electrode 150 is commonly assigned to the red phosphor layer and the green phosphor layer among the phosphor layers 180, and the remaining blue Another address electrode 150 may be allocated to the phosphor layer. Of course, one address electrode 150 may be commonly allocated to the green phosphor layer and the blue phosphor layer among the phosphor layers 180, and the other address electrode 150 may be allocated to the other red phosphor layer. . In addition, one address electrode 150 may be allocated to the blue phosphor layer and the red phosphor layer of the phosphor layer 180 in common, and the other address electrode 150 may be allocated to the other green phosphor layer.

The discharge cells 191, 192, and 193 are defined by the lower dielectric layer 160, the partition wall 170, and the upper dielectric layer 130 on the upper surface of the rear substrate 140. The discharge cells 191, 192, and 193 are filled with a discharge gas (eg, a mixed gas including xenon (Xe), neon (Ne), etc.) to cause plasma discharge. In addition, as described above, the discharge cells 191, 192, and 193 have a phosphor layer 180 that absorbs ultraviolet rays and emits visible light in a predetermined region. The discharge cells 191, 192, and 193 may have different widths or lengths depending on the luminous efficiency of each phosphor. In the discharge cells 191, 192, and 193, electrodes which undergo address discharge and sustain discharge are disposed at the center and the bottom thereof.

A plurality of discharge cells 191, 192, and 193 are repeatedly arranged along one address electrode 150, and each discharge cell 191, 192, and 193 is arranged to emit visible light of different colors. have. For example, when centering on the address electrodes 150 in the first column from the left side shown in FIG. 2, the discharge cells R having the red phosphor layer in the upper to the lower direction and the discharge cells G having the green fluorescent layer are present. And the discharge cells B having the blue fluorescent layer may be repeatedly arranged in the vertical direction. In addition, when the center of the address electrode 150 in the second column, the discharge cell (G) having a green fluorescent layer, the discharge cell (B) having a blue fluorescent layer, and the discharge cell (R) having a red fluorescent layer from the top to the bottom direction. ) May be arranged in the vertical direction repeatedly.

A pair of display electrodes 120 may be allocated to one pixel 190 divided by the partition wall 170. That is, the Y1 Y display electrode and the X1 X display electrode are commonly allocated to the two discharge cells 191 and 192, and the X1 X display electrode is allocated to the other discharge cell 193.

Next, the structure of the PDP according to the second embodiment of the present invention will be described. 3B is a cross-sectional view of a PDP according to a second embodiment of the present invention.

Referring to FIG. 3B, the Y display electrode 122 ′ and the X display electrode 124 ′ are formed parallel to each other in the partition wall 170. Since the Y display electrode 122 ′ and the X display electrode 124 ′ are disposed inside the partition wall 170 and do not require transparency, the Y display electrode 122 ′ and the X display electrode 124 ′ may be formed of metal electrodes of a general conductive metal. That is, it may be formed of only the bus electrode without the transparent electrode. The Y display electrode 122 'and the X display electrode 124' are preferably formed of a metal material having high conductivity and low resistance such as silver (Ag), aluminum (Al), copper (Cu), and the like, and discharge The response speed is fast and the signal is not distorted, and power consumption required for maintenance discharge can be reduced. However, the material of the Y display electrode 122 ′ and the X display electrode 124 ′ is not limited, and various metals having excellent conductivity and low resistance may be used. However, like the first embodiment, the intermediate electrode 126 is disposed on the rear surface of the front substrate 110 to contribute to the reset discharge and the address discharge. By disposing the Y display electrode 122 'and the X display electrode 124' inside the partition wall 170 to form a counter electrode structure, the discharge space is larger and the discharge path is longer than that of the surface discharge electrode structure. There is an advantage that the brightness is improved.

In this manner, in the plasma display panel 100 according to the present invention, two address electrodes 150 are allocated to one pixel 190, so that the number of address electrodes 150 is reduced to approximately 2/3 as compared with the related art. Thus, power consumption is also reduced to approximately two thirds. In addition, the power required by one circuit to drive the address electrode 150 is also reduced compared to the conventional, the heat release rate is also significantly smaller than the conventional.

In addition, since the number of address electrodes 150 is reduced in the same area, the pitch between the address electrodes 150 is naturally increased, thereby reducing the capacitance between the address electrodes 150. In other words, it can be seen that the number of address electrodes 150 can be increased in the same area as before, resulting in an advantageous structure for high definition of the PDP.

Next, an embodiment of a driving waveform that can be applied to the PDP according to the present invention will be described in consideration of the fact that the intermediate electrode 126 is further provided. 4 is a driving waveform diagram of a PDP according to an exemplary embodiment of the present invention, and FIGS. 5A to 5E are schematic diagrams showing a wall charge distribution according to the driving waveform shown in FIG. 4. Hereinafter, the driving method according to the present embodiment will be described with reference to FIGS. 4 to 5E.

According to the driving method according to the embodiment of the present invention shown in Fig. 4, each subfield is composed of a reset section, an address section, and a sustain section. The reset section is composed of an erasing section, an intermediate electrode rising waveform section and an intermediate electrode falling waveform section. Hereinafter, the address electrode is referred to as the A electrode, the Y display electrode as the Y electrode, the X display electrode as the X electrode, and the intermediate electrode is referred to as the M electrode.

The erasing section I of the reset section erases wall charges formed in the previous sustain discharge section. According to the present embodiment, it is assumed that the sustain discharge voltage pulse is applied to the X electrode at the last time of the sustain discharge interval, and that a voltage lower than the voltage applied to the X electrode (eg, the ground voltage) is applied to the Y electrode. Then, as illustrated in FIG. 5A, positive wall charges are formed on the Y electrode and the A electrode, and negative wall charges are formed on the X electrode and the M electrode. In the erasing period (I), while the Y electrode is biased with the voltage Vyc, a ramp waveform that gently drops from the Vmc voltage to the ground voltage is applied to the M electrode. Then, as shown in Fig. 5A, the wall charges formed during the sustain discharge section are erased.

The ramp waveform rising slowly from the voltage Vmd to Vset is applied to the M electrode while the X electrode and the Y electrode are biased with the ground voltage in the M electrode rising waveform section II during the reset period. While this rising waveform is applied, a weak reset discharge occurs in all discharge cells from the M electrode to the A electrode, the X electrode, and the Y electrode, respectively. As a result, as shown in Fig. 5B, negative wall charges are accumulated on the M electrode, and positive wall charges are accumulated on the A electrode, the X electrode, and the Y electrode at the same time.

In the M electrode falling waveform section III of the reset section, a ramp waveform that gently falls from the voltage Vme toward the ground voltage is applied to the M electrode while the X and Y electrodes are biased to Vxe and Vye, respectively. At this time, it is preferable to set Vxe = Vye and Vmd = Vme in that the circuit configuration can be simplified, but is not necessarily limited thereto. While this ramp voltage is falling, a weak reset discharge occurs again in all the discharge cells. At this time, since the M electrode falling waveform section is for slowly decreasing the wall charges accumulated by the M electrode rising waveform section, the wall charge amount that decreases with longer time of the falling waveform (that is, the slope is gentle) is precisely reduced. It is advantageous to address discharge because it can be controlled.

As a result of applying the falling waveform to the M electrode, the wall charges accumulated on each electrode of all the cells are evenly erased. As shown in FIG. 5C, positive wall charges are accumulated on the A electrode, and at the same time, the X electrode and the Y electrode (-) Wall charges are stored in the M electrode.

In the address period, while a plurality of M electrodes are biased to the Vsc voltage, scan pulses are sequentially applied to the M electrodes to apply scan pulses, and at the same time, an address voltage Va is applied to a cell to be discharged to the A electrode. ) Is applied. At this time, the X electrode is maintained at the ground voltage, and the voltage Vye is applied to the Y electrode. Then, discharge occurs between the M electrode and the A electrode, and the discharge is extended to the X electrode and the Y electrode. As a result, as shown in FIG. 5D, positive wall charges are accumulated on the X electrode and the M electrode, and Negative wall charges are accumulated in the electrode and the A electrode.

In the sustain discharge section, the sustain discharge voltage pulse is alternately applied to the X electrode and the Y electrode while the M electrode is biased at the sustain discharge voltage Vm. The sustain discharge occurs in the discharge cells selected in the address section through the application of such a voltage. At this time, according to the present embodiment, the discharge is generated by different discharge mechanisms at the initial and normal time of sustain discharge. For convenience of explanation, hereinafter, a discharge generated at the initial stage of sustain discharge is referred to as a short-gap discharge section, and a discharge at a normal time point is referred to as a long-gap discharge section.

In the start period of sustain discharge, as shown in (a) and (b) of FIG. 5E, a positive voltage pulse is applied to the X electrode and a negative voltage pulse is applied to the Y electrode, but at the same time, A positive voltage pulse is applied to the M electrode. Therefore, unlike the conventional case where the discharge occurs only between the X electrode and the Y electrode, the discharge occurs between the M electrode and the Y electrode. In particular, according to the present embodiment, since the distance between the M electrode and the Y electrode is closer than the distance between the X electrode and the Y electrode, the electric field applied between the M electrode and the Y electrode becomes larger. Therefore, the discharge between the M electrode and the Y electrode plays a leading role than the discharge between the X electrode and the Y electrode. As described above, in the present embodiment, since the discharge between the M electrode and the Y electrode having a relatively short distance plays a dominant role in the initial stage of sustain discharge, it is called a short gap discharge.

As described above, according to the present embodiment, since a short gap discharge occurs by applying a relatively high electric field at the initial stage of sustain discharge, sufficient discharge is performed even if sufficient charge particles are not generated in the discharge cell when the first sustain discharge pulse is applied after the address period. can do.

After applying the first sustain discharge pulse of sustain discharge, since the voltage of the M electrode is biased to a constant voltage Vm, the discharge between the M electrode and the X electrode or the discharge between the M electrode and the Y electrode contributes little to the discharge. The former is discharged between the X electrode and the Y electrode, and finally the image inputted by the number of discharge pulses applied to the X electrode and the Y electrode can be displayed. That is, as shown in (d) of FIG. 5E, (-) wall charges continuously accumulate in the M electrode, and (-) wall charge and ( +) Wall charges accumulate.

As described above, according to the present embodiment, since the discharge is performed by the short gap discharge between the X electrode and the M electrode or the Y electrode and the M electrode at the beginning of the sustain discharge, sufficient discharge is performed even in a state where there are few charged particles, and in the normal state, the X electrode Since the discharge is performed by the long gap discharge between the and Y electrodes, stable discharge can be performed.

As described above, the present invention is not limited to the specific preferred embodiments described above, and any person having ordinary skill in the art to which the present invention pertains without departing from the gist of the present invention claimed in the claims. Various modifications are possible, of course, and such changes are within the scope of the claims.

According to the plasma display panel according to the present invention, by forming a barrier rib structure in which two address electrodes are allocated to one pixel, capacitance between address electrodes can be reduced, and power consumption can be reduced, and an intermediate electrode is provided between display electrodes. It is effective to lower the total voltage and perform a stable discharge.

In addition, it is advantageous for high definition by reducing the number of address electrodes in the same area, and an opaque bus electrode which blocks light emitted from the phosphor can be located on the partition wall by addressing using the intermediate electrode and the address electrode. Has the effect of improving.

Claims (12)

A front substrate and a rear substrate facing each other; A partition wall formed between the front substrate and the rear substrate and partitioning the discharge cells so that three discharge cells emitting different colors of visible light are adjacent to each other to form one pixel; Y display electrodes and X display electrodes formed between the front substrate and the rear substrate; Two address electrodes are allocated to one pixel composed of discharge cells separated by the barrier rib, and include an intermediate electrode disposed between the Y display electrode and the X display electrode to correspond to each discharge cell. Characterized in that the plasma display panel. The method of claim 1, And one address electrode is commonly allocated to two selected discharge cells among the three discharge cells constituting the one pixel, and another address electrode is allocated to the other discharge cell. The method of claim 1, And the Y display electrode and the X display electrode are formed on the rear surface of the front substrate in parallel with each other. The method of claim 3, wherein And the intermediate electrode is disposed on a rear surface of the front substrate and is formed between the Y display electrode and the X display electrode. The method of claim 4, wherein The Y display electrode, the X display electrode, and the intermediate electrode include a transparent electrode and a bus electrode. The method of claim 1, And the Y display electrode and the X display electrode are formed in parallel to each other in the partition wall. The method of claim 6, And the Y display electrode and the X display electrode are formed of a metal electrode. The method of claim 1, And the Y display electrode and the X display electrode are formed in a transverse direction along the partition wall. The method of claim 8, And a discharge cell coated with phosphors of different colors bordering on the Y display electrode and the X display electrode. The method of claim 8, And the intermediate electrode is formed in parallel with the Y display electrode and the X display electrode. The method of claim 1, The discharge cell has a plasma display panel, characterized in that any one of a triangle, a square, a rhombus, a hexagon. The method of claim 1, And a plurality of discharge cells are repeatedly arranged along one address electrode, and each discharge cell is arranged to emit visible light of different colors.

Images